== Series Details ==
Series: series starting with [CI,1/8] drm/i915/dg1: add more PCI ids
URL : https://patchwork.freedesktop.org/series/82422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104_full -> Patchwork_18642_full
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/dg1: add more PCI ids
URL : https://patchwork.freedesktop.org/series/82422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18642
Summary
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/dg1: add more PCI ids
URL : https://patchwork.freedesktop.org/series/82422/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
From: Matt Roper
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
Synchronize with the current list of DG1 PCI IDs.
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
include/drm/i915_pciids.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1..095463ff7cb9
From: Matt Roper
DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
frequencies on CNP+. Note that register bits associated with this
frequency confusingly use 37 for the divider field rather than 38 as you
might expect.
For simplicity, let's just assume that this 38.4 MHz frequency
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
>From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.
The values for VBT seem wrong in BSpec. For the current boards we
actually have a 1:1 mapping.
BSpec: 49311, 49945, 20124
Cc:
From: Matt Roper
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B. It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL
From: Matt Roper
As with RKL, DG1's PHY C acts as a comp master for PHY D.
Bspec: 49291
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Venkata Sandeep Dhanalakota
On DGFX the register range has been extended to go up to 8MB. However we
only actually use up to address 28h, so let's increase it to 4MB.
v2 (Lucas): add bspec reference and reword commit message to explain
the 4 vs 8 MB used (requested by Matt Roper)
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
v2: Reword the comment to state that the last few entries are reserved
instead of
On Mon, Oct 05, 2020 at 10:54:49PM +0530, Tejas Upadhyay wrote:
> Split the basic platform definition, macros, and PCI IDs to
> differentiate between EHL and JSL platforms.
>
> Changes since V3 :
> - Changed IS_EHL_JSL to IS_JSL_EHL
A grep of drm/i915 after applying this patch still shows
On Fri, Oct 02, 2020 at 12:58:56PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 02, 2020 at 02:54:34AM +0530, Tejas Upadhyay wrote:
> > Split the basic platform definition, macros, and PCI IDs to
> > differentiate between EHL and JSL platforms.
> >
> > Changes since V2 :
> > - Added IS_EHL_JSL
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
URL : https://patchwork.freedesktop.org/series/82411/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9104_full -> Patchwork_18640_full
== Series Details ==
Series: ALSA: hda/i915 - fix list corruption with concurrent probes
URL : https://patchwork.freedesktop.org/series/82414/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9104_full -> Patchwork_18639_full
== Series Details ==
Series: drm/i915/ehl: Remove require_force_probe protection
URL : https://patchwork.freedesktop.org/series/82413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104_full -> Patchwork_18638_full
Summary
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev7)
URL : https://patchwork.freedesktop.org/series/68081/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9104_full -> Patchwork_18636_full
Summary
== Series Details ==
Series: series starting with [1/3] drm/i915: Reorder hpd init vs. display resume
URL : https://patchwork.freedesktop.org/series/82417/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18641
From: Ville Syrjälä
Add a small wrapper for .hpd_irq_setup() which does the
"do we even have the hook?" and "are display interrupts enabled?"
checks.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 22 +++-
1 file changed, 12 insertions(+), 10
From: Ville Syrjälä
LSPCON requires HPD detection logic to be enabled when we call
its .reset() hook during resume, to check the live state of the
pin. To that end let's reorder the resume sequence such that
we do HPD init before the encoder reset.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Currently we call .hpd_irq_setup() directly just before display
resume, and follow it with another call via intel_hpd_init()
just afterwards. Assuming the hpd pins are marked as enabled
during the open-coded call these two things do exactly the
same thing (ie. enable HPD
== Series Details ==
Series: drm/i915/gt: Track the most recent pulse for the heartbeat (rev3)
URL : https://patchwork.freedesktop.org/series/82339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9104_full -> Patchwork_18633_full
On Tue, Oct 06, 2020 at 09:13:32PM +0300, Jani Nikula wrote:
> On Tue, 06 Oct 2020, Ville Syrjälä wrote:
> > On Tue, Oct 06, 2020 at 12:29:22PM +0300, Jani Nikula wrote:
> >> On Thu, 01 Oct 2020, Ville Syrjala wrote:
> >> > From: Ville Syrjälä
> >> >
> >> > Currently VLV/CHV use a reboot
On Tue, 06 Oct 2020, Ville Syrjälä wrote:
> On Tue, Oct 06, 2020 at 12:29:22PM +0300, Jani Nikula wrote:
>> On Thu, 01 Oct 2020, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Currently VLV/CHV use a reboot notifier to make sure the panel
>> > power cycle delay isn't violated across a
On Tue, 2020-10-06 at 10:55 -0700, Vivi, Rodrigo wrote:
>
> > On Oct 6, 2020, at 10:48 AM, Chris Wilson wrote:
> >
> > Quoting Souza, Jose (2020-10-06 18:46:45)
> > > +Rodrigo and Jani
> > >
> > > On Tue, 2020-10-06 at 14:56 +, Kamati Srinivas wrote:
> > > > Removing force probe protection
> On Oct 6, 2020, at 10:48 AM, Chris Wilson wrote:
>
> Quoting Souza, Jose (2020-10-06 18:46:45)
>> +Rodrigo and Jani
>>
>> On Tue, 2020-10-06 at 14:56 +, Kamati Srinivas wrote:
>>> Removing force probe protection from EHL platform. Did
>>> not observe warnings, errors, flickering or any
Quoting Souza, Jose (2020-10-06 18:46:45)
> +Rodrigo and Jani
>
> On Tue, 2020-10-06 at 14:56 +, Kamati Srinivas wrote:
> > Removing force probe protection from EHL platform. Did
> > not observe warnings, errors, flickering or any visual
> > defects while doing ordinary tasks like browsing
+Rodrigo and Jani
On Tue, 2020-10-06 at 14:56 +, Kamati Srinivas wrote:
> Removing force probe protection from EHL platform. Did
> not observe warnings, errors, flickering or any visual
> defects while doing ordinary tasks like browsing and
> editing documents in a two monitor setup.
One of
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
URL : https://patchwork.freedesktop.org/series/82411/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18640
On Tue, 2020-10-06 at 12:04 +0300, Jani Nikula wrote:
> On Tue, 29 Sep 2020, José Roberto de Souza wrote:
> > Child min_brightness is obsolete from VBT 234+, instead the new
> > min_brightness field in the main structure should be used.
> >
> > This new field is 16 bits wide, so
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
URL : https://patchwork.freedesktop.org/series/82411/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev3)
URL : https://patchwork.freedesktop.org/series/82411/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ac8d5caeb9e4 drm/i915: Sort the mess around ICP TC hotplugs regs
c825eca75000
Deadline is November 1st, just in a few weeks!
Don't forget to submit your XDC 2021 proposal to bo...@foundation.x.org
.
Sam
On Thu, 2020-09-03 at 12:16 -0400, Lyude Paul wrote:
> (Including a bunch more emails in the To: that got missed the first
> time)
>
> Hello everyone!
>
> The X.org
On Sun, Oct 04, 2020 at 06:43:36PM +0300, Leon Romanovsky wrote:
> This series extends __sg_alloc_table_from_pages to allow chaining of
> new pages to already initialized SG table.
>
> This allows for the drivers to utilize the optimization of merging contiguous
> pages without a need to pre
As reported by Sphinx:
./Documentation/gpu/i915:646: ./drivers/gpu/drm/i915/i915_perf.c:1147:
WARNING: Duplicate C declaration, also defined in 'gpu/i915'.
Declaration is 'i915_oa_wait_unlocked'.
./Documentation/gpu/i915:646: ./drivers/gpu/drm/i915/i915_perf.c:1169:
== Series Details ==
Series: ALSA: hda/i915 - fix list corruption with concurrent probes
URL : https://patchwork.freedesktop.org/series/82414/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18639
Summary
On Tue, Oct 06, 2020 at 07:20:46PM +0300, Imre Deak wrote:
> On Tue, Oct 06, 2020 at 05:33:44PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > No reason that I can see why we should enable the hpd detection logic
> > already during irq postinstall phase. We don't even do this on all
From: Ville Syrjälä
Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.
v2: Remember the gvt
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gvt/display.c | 14 +++---
drivers/gpu/drm/i915/i915_irq.c| 18
From: Takashi Iwai
Current hdac_i915 uses a static completion instance to wait
for i915 driver to complete the component bind.
This design is not safe if multiple HDA controllers are active and
communicating with different i915 instances, and can lead to list
corruption and failed audio driver
From: Ville Syrjälä
Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
these have nothing to do with DDI ports or PHYs as such. The only
thing that matters is the HPD pin assignment.
v2: Remember the gvt
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gvt/display.c | 13
On Tue, Oct 06, 2020 at 05:33:44PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No reason that I can see why we should enable the hpd detection logic
> already during irq postinstall phase. We don't even do this on all
> the platforms. We just need it before we actually enable the
== Series Details ==
Series: drm/i915/ehl: Remove require_force_probe protection
URL : https://patchwork.freedesktop.org/series/82413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18638
Summary
---
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev7)
URL : https://patchwork.freedesktop.org/series/68081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18636
Summary
---
== Series Details ==
Series: drm/i915: Futher cleanup around hpd pins and port identfiers
URL : https://patchwork.freedesktop.org/series/82411/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
== Series Details ==
Series: Enable HDR on MCA LSPCON based Gen9 devices (rev7)
URL : https://patchwork.freedesktop.org/series/68081/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
Removing force probe protection from EHL platform. Did
not observe warnings, errors, flickering or any visual
defects while doing ordinary tasks like browsing and
editing documents in a two monitor setup.
Signed-off-by: Kamati Srinivas
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed,
== Series Details ==
Series: series starting with [1/3] drm/i915/cnl: Handle incorrect divider
values during WRPLL HW readout
URL : https://patchwork.freedesktop.org/series/82406/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18635
From: Ville Syrjälä
Parametrize the icp+ TC HPD bits using hpd_pin rather than
tc_port so it's clear what kind of an animal we're dealing
with.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 30 -
drivers/gpu/drm/i915/i915_reg.h | 40
From: Ville Syrjälä
Move intel_hpd_{enabled,hotplug}_irqs() closes to the beginning of
the file so we can use them in more places. No functional changes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 50 -
1 file changed, 25 insertions(+),
From: Ville Syrjälä
ibx_irq_pre_postinstall() looks totally pointless. We can just
init both SDEIMR and SDEIER at the same time before enabling the
master intererupt. It's equally racy as the other order due
to doing all of this from the postinstall stage with the interrupt
handler already in
From: Ville Syrjälä
As with the VBT DVO port, RKL uses PHY based mapping for the
VBT AUX CH. Adjust the code to use the new AUX_USBCn names
and add a comment to explain the situation.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 ++--
1 file changed, 6
From: Ville Syrjälä
No reason not to use GEN3_IRQ_INIT() on icp+.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index
From: Ville Syrjälä
Let's enable the hardware hpd logic only for the ports we
can actually use.
In theory this may save some miniscule amounts of power,
and more importantly it eliminates a lot if platform specific
codepaths since the generic thing can now deal with any
combination of ports
From: Ville Syrjälä
Let's make the AUX CH names match the spec (AUX A-F for pre-tgl,
AUX A-C or AUX USBC1-6 for tgl+). And while at it let's include
the full encoder name in the AUX CH name as well (as opposed to
just using port_name() which wouldn't give us the right thing on
tgl+).
From: Ville Syrjälä
Replace this silly tmp_mask with hotplug_trigger/te_trigger
where appropriate.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
From: Ville Syrjälä
No reason to stuff both type-c and tbt into the same function.
Let's split this so we may more easily handle platforms that
lack the tbt spefific bits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 13 ++---
1 file changed, 10 insertions(+), 3
From: Ville Syrjälä
Let's pimp the DDI encoder->name to reflect what the spec calls them.
Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.
Also since each encoder is really a combination of the DDI and the PHY
we include the PHY name as well.
ICL is a bit special since it already has the
From: Ville Syrjälä
We no longer unmask all HPD irqs, so we can drop the ugly per-platform
HPD IIR masking. IMR will prevent unsupported bits from appearing in
IIR.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h |
From: Ville Syrjälä
Just like with the DDIs tgl+ renamed the AUX CHs to reflect
the type of the DDI. Let's add the aliasing enum values for
the type-C AUX CHs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.h | 8 +++
drivers/gpu/drm/i915/display/intel_dp.c
From: Ville Syrjälä
Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 18 +-
drivers/gpu/drm/i915/i915_reg.h | 10 +-
2 files
From: Ville Syrjälä
Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3...
Add the appropriate enum values for the TC DDIs to enum port.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c| 10 +++
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
From: Ville Syrjälä
Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
these have nothing to do with DDI ports or PHYs as such. The only
thing that matters is the HPD pin assignment.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 12 ++--
From: Ville Syrjälä
Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG()
to make it clear what they refer to.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 48 -
drivers/gpu/drm/i915/i915_reg.h | 37 -
2
From: Ville Syrjälä
Continuing the saga of trying to remove most of the nasty platform
if-ladders from the irq code where they don't belong.
Also adding some aliases for the TC DDIs/AUX CHs to make
the code less confusing. And some other cleanup around the affected
areas that kept bugging me.
From: Ville Syrjälä
Make the namespacing for enum tc_port better by adding
the TC_ to the actual enum values.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 14 ++--
drivers/gpu/drm/i915/display/intel_tc.c
From: Ville Syrjälä
No reason that I can see why we should enable the hpd detection logic
already during irq postinstall phase. We don't even do this on all
the platforms. We just need it before we actually enable the hotplug
interrupts in .hpd_irq_setup(), and in fact we already do it there as
From: Ville Syrjälä
Move the DSC stuff out from the middle of the ICP HPD register
definitions. The location seems to have been selected by a
dice roll.
SHPD_FILTER_CNT addition also went astray due to the DSC
mess, so we also fix that vs. ICP_TC_HPD_{SHORT,LONG}_DETECT().
Signed-off-by: Ville
From: Ville Syrjälä
Use hpd_pin instead of port in the parametrized ICP+ DDI HPD
macros. Makes it clear what these refer to.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 12 ++--
drivers/gpu/drm/i915/i915_reg.h | 34 -
2 files
== Series Details ==
Series: drm/i915/gt: Track the most recent pulse for the heartbeat (rev3)
URL : https://patchwork.freedesktop.org/series/82339/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9104 -> Patchwork_18633
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev2)
URL : https://patchwork.freedesktop.org/series/82098/
State : failure
== Summary ==
Applying: drm/edid: Add additional HFVSDB fields for HDMI2.1
Applying: drm/edid: Parse MAX_FRL field from HFVSDB block
Applying:
On Tue, Oct 06, 2020 at 12:29:22PM +0300, Jani Nikula wrote:
> On Thu, 01 Oct 2020, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently VLV/CHV use a reboot notifier to make sure the panel
> > power cycle delay isn't violated across a system reboot. Replace
> > that with the new
LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
DPCD register. LSPCON implementations capable of supporting
HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
reads the same, detects the HDR capability and adds this to
intel_lspcon struct.
v2: Addressed Jani
Non-HDMI sinks shouldn't be sent Dynamic Range and Mastering infoframes.
Check for that when using LSPCON.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
Gen9 hardware supports HDMI2.0 through LSPCON chips.
Extending HDR support for MCA LSPCON based GEN9 devices.
SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
Mastering
Attach HDR property for Gen9 devices with MCA LSPCON
chips.
v2: Cleaned HDR property attachment logic based on capability
as per Jani Nikula's suggestion.
v3: Fixed the HDR property attachment logic as per the new changes
by Kai-Feng to align with lspcon detection failure on some devices.
Blanking needs to be reduced to incorporate DP and HDMI timing/link
bandwidth limitations for CEA modes (4k@60 at 10 bpp). DP can drive
17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps.
This will cause mode to blank out. Reduced Htotal by shortening the
back porch and front porch
Implement Read back of HDR metadata infoframes i.e Dynamic Range
and Mastering Infoframe for LSPCON devices.
v2: Added proper bitmask of enabled infoframes as per Ville's
recommendation.
v3: Dropped a redundant wrapper as per Ville's comment.
Signed-off-by: Uma Shankar
---
Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe).
Create a separate mechanism for lspcon compared to HDMI in order to
address the same and ensure future scalability.
Suggested-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c| 10
Implemented Infoframes enabled readback for LSPCON devices.
This will help align the implementation with state readback
infrastructure.
v2: Added proper bitmask of enabled infoframes as per Ville's
recommendation.
v3: Added pcon specific infoframe types instead of using the HSW
one's, as
Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
data for HDR using AVI infoframe. LSPCON firmware expects this and though
SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device
which transfers the same to HDMI sink.
v2: Dropped state managed in drm core as
Enable HDR for LSPCON based on Parade along with MCA.
v2: Added a helper for status reg as suggested by Ville.
Signed-off-by: Uma Shankar
Signed-off-by: Vipin Anand
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR
support for MCA and Parade LSPCON based GEN9 devices.
SOC will drive LSPCON as DP and send HDR metadata as standard
DP SDP packets. LSPCON will be set to operate in PCON mode,
will receive the metadata and create Dynamic Range and
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, October 6, 2020 2:39 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 06/11] drm/i915/display: Implement infoframes readback for
> LSPCON
>
> On Mon, Oct 05, 2020 at 09:36:35PM +, Shankar,
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, October 6, 2020 2:36 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9
> devices
>
> On Mon, Oct 05, 2020 at 09:32:22PM +,
Add the MISSING_CASE() for the p0, p2 decoding during WRPLL HW readout
and move the corresponding check for p1 next to where it's read out.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git
The p0 divider (aka PDIV) doesn't support the div-by-5 configuration, so
in case the effective divider (p0*p1*p2) value is 5, either p1 (QDIV) or
p2 (KDIV) must be used. p1 can't be used either since it must match p0
if p0 is 1, so using p2 is the only possibility.
This didn't cause an actual
Move the check of p1 divider value next to where it's read out.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Fix DMA mapped scatterlist walks
URL : https://patchwork.freedesktop.org/series/82402/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9102_full -> Patchwork_18631_full
On Tue, Oct 06, 2020 at 08:00:03PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> On Thu, 10 Sep 2020 14:18:54 +1000 Stephen Rothwell
> wrote:
> >
> > Today's linux-next merge of the extcon tree got a conflict in:
> >
> > MAINTAINERS
> >
> > between commit:
> >
> > f61249dddecc
On Tue, Oct 06, 2020 at 01:32:58PM +0300, Imre Deak wrote:
> On Tue, Oct 06, 2020 at 02:39:51AM +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
> > clock (rev6)
> > URL :
On Mon, Oct 05, 2020 at 08:56:50PM -0300, Jason Gunthorpe wrote:
> On Sun, Oct 04, 2020 at 06:43:36PM +0300, Leon Romanovsky wrote:
> > This series extends __sg_alloc_table_from_pages to allow chaining of
> > new pages to already initialized SG table.
> >
> > This allows for the drivers to
Chris Wilson writes:
> Currently we do a final scrub of the HW state upon release. However,
> when rebinding the device, this is too late as the device may either
> have been partially rebound or the device is no longer accessible. If
> the device has been removed before release, the reset goes
On Tue, Oct 06, 2020 at 02:39:51AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
> clock (rev6)
> URL : https://patchwork.freedesktop.org/series/82173/
> State : failure
>
> == Summary ==
>
> CI Bug Log -
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Fix DMA mapped scatterlist walks
URL : https://patchwork.freedesktop.org/series/82402/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9102 -> Patchwork_18631
On Tue, Oct 06, 2020 at 01:00:21PM +0300, Jani Nikula wrote:
> On Tue, 06 Oct 2020, Imre Deak wrote:
> > On Tue, Oct 06, 2020 at 12:42:58PM +0300, Jani Nikula wrote:
> >> On Tue, 06 Oct 2020, Imre Deak wrote:
> >> > +static bool gen11_dsi_initial_fastset_check(struct intel_encoder
> >> >
On Tue, 06 Oct 2020, Imre Deak wrote:
> On Tue, Oct 06, 2020 at 12:42:58PM +0300, Jani Nikula wrote:
>> On Tue, 06 Oct 2020, Imre Deak wrote:
>> > +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
>> > + struct intel_crtc_state
Quoting Ville Syrjala (2020-10-01 16:16:35)
> From: Ville Syrjälä
>
> Implement the pci .shutdown() hook in order to quiesce the
> hardware prior to reboot. The main purpose here is to turn
> all displays off. Some displays/other drivers tend to get
> confused if the state after reboot isn't
On Tue, Oct 06, 2020 at 12:42:58PM +0300, Jani Nikula wrote:
> On Tue, 06 Oct 2020, Imre Deak wrote:
> > Move the checks to decide whether a fastset is possible during the
> > initial commit to an encoder hook. This check is really encoder specific
> > and the next patch will also require this
This patch series attempts to add support for a DP-HDMI2.1 Protocol
Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata
E5 to DisplayPort_v2.0:
https://vesa.org/join-vesamemberships/member-downloads/?action=stamp=42299
The details are mentioned in DP to HDMI2.1 PCON Enum/Config
From: Swati Sharma
This patch adds support for link status and link recovery. There
are specific DPCD’s defined for link status check and recovery in
case of any issues. PCON will communicate the same using an IRQ_HPD
to source. HDMI sink would have indicated the same to PCON using
SCDC
1 - 100 of 125 matches
Mail list logo
