== Series Details ==
Series: series starting with [v2,1/6] drm/i915/display/psr: Calculate selective
fetch plane registers
URL : https://patchwork.freedesktop.org/series/83119/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18793
== Series Details ==
Series: drm/i915: Fix encoder lookup during PSR atomic check
URL : https://patchwork.freedesktop.org/series/83102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18787_full
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/display/psr: Calculate selective
fetch plane registers
URL : https://patchwork.freedesktop.org/series/83119/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit
== Series Details ==
Series: series starting with [v2,1/5] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes
URL : https://patchwork.freedesktop.org/series/83118/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18792
== Series Details ==
Series: series starting with [v2,1/5] drm/i915/dp: Some reshuffling in
mode_valid as prep for bigjoiner modes
URL : https://patchwork.freedesktop.org/series/83118/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
10e42fe832c7 drm/i915/dp: Some reshuffling in
== Series Details ==
Series: drm/i915: Fix error handling during DPRX link training
URL : https://patchwork.freedesktop.org/series/83097/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18785_full
== Series Details ==
Series: drm/i915: Remainder of dbuf state stuff
URL : https://patchwork.freedesktop.org/series/83114/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18791
Summary
---
== Series Details ==
Series: drm/i915: Remainder of dbuf state stuff
URL : https://patchwork.freedesktop.org/series/83114/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: drm/i915: Remainder of dbuf state stuff
URL : https://patchwork.freedesktop.org/series/83114/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
202be8e23dc4 drm/i915: Extract intel_crtc_ddb_weight()
bda46a35b586 drm/i915: Pass the crtc to
== Series Details ==
Series: Prep for Big joiner + Allow bigjoiner modes
URL : https://patchwork.freedesktop.org/series/83110/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18790
Summary
---
== Series Details ==
Series: drm/i915: Acquire connector reference before prop_work
URL : https://patchwork.freedesktop.org/series/83090/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18784_full
== Series Details ==
Series: Prep for Big joiner + Allow bigjoiner modes
URL : https://patchwork.freedesktop.org/series/83110/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
025d836673b7 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:10:
== Series Details ==
Series: drm/i915/gem: Avoid synchronous binds deep within locks
URL : https://patchwork.freedesktop.org/series/83108/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18789
Summary
== Series Details ==
Series: series starting with [1/3] drm/i915: Guard debugfs against invalid
access without display
URL : https://patchwork.freedesktop.org/series/83070/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18782_full
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18788
Summary
---
== Series Details ==
Series: drm/i915: Fix encoder lookup during PSR atomic check
URL : https://patchwork.freedesktop.org/series/83102/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18787
Summary
---
== Series Details ==
Series: drm/i915/gt: Start timeline with a wrap
URL : https://patchwork.freedesktop.org/series/83099/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18786
Summary
---
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL : https://patchwork.freedesktop.org/series/82998/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb73b788c82a drm/i915/hdcp: Update CP property in update_pipe
1b2040195053 drm/i915/hdcp: Get conn
== Series Details ==
Series: series starting with [1/3] drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83069/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18781_full
== Series Details ==
Series: drm/i915: Fix error handling during DPRX link training
URL : https://patchwork.freedesktop.org/series/83097/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18785
Summary
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
between commit:
ff72bc403170 ("drm/amdgpu: Add debugfs entry for printing VM info")
from the amdgpu tree and commit:
4671078eb8e3 ("drm/amdgpu: switch over to the new pin
== Series Details ==
Series: drm/i915: Acquire connector reference before prop_work
URL : https://patchwork.freedesktop.org/series/83090/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18784
Summary
On Fri, Oct 23, 2020 at 10:44:29PM +0300, Ville Syrjälä wrote:
On Fri, Oct 23, 2020 at 12:29:37PM -0700, Lucas De Marchi wrote:
On Fri, Oct 23, 2020 at 04:34:17PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä
>
>We no longer unmask all HPD irqs, so we can drop the ugly per-platform
>HPD IIR
On Tue, Oct 27, 2020 at 5:06 PM Lucas De Marchi
wrote:
>
> Missing braces after rebase and surprisingly not caught by checkpatch.
>
> Fixes: 229f31e2d370 ("drm/i915/dg1: add hpd interrupt handling")
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_irq.c | 4 ++--
> 1 file
== Series Details ==
Series: series starting with [1/3] drm/i915: Guard debugfs against invalid
access without display
URL : https://patchwork.freedesktop.org/series/83070/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18782
== Series Details ==
Series: Big joiner enabling (rev5)
URL : https://patchwork.freedesktop.org/series/82944/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M]
Missing braces after rebase and surprisingly not caught by checkpatch.
Fixes: 229f31e2d370 ("drm/i915/dg1: add hpd interrupt handling")
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
== Series Details ==
Series: series starting with [1/3] drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83069/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18781
Summary
Add the calculations to set plane selective fetch registers depending
in the value of the area damaged.
It is still using the whole plane area as damaged but that will change
in next patches.
v2:
- fixed new_plane_state->uapi.dst.y2 typo in
intel_psr2_sel_fetch_update()
- do not shifthing
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
v2:
- do not shifthing new_plane_state->uapi.dst only src is in 16.16 format
Cc: Ville Syrjälä
Cc:
Enabling it to check if it causes regressions in CI but the feature is
still not ready to be enabled by default.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c |
Planes can individually have transparent, move or have visibility
changed if any of those happens, planes bellow it will be visible or
have more pixels of it visible than before.
This patch is taking care of this case for selective fetch by adding
to each plane damaged area all the intersections
Do the calculation of x and y offsets using
skl_calc_main_surface_offset().
RFC/WIP: This causes the value of the calculated x to be different than
plane_state->color_plane[color_plane].x, not sure if that is expected.
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
== Series Details ==
Series: series starting with [1/3] drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83069/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: series starting with [1/3] drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83069/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8bd39690adad drm/i915/dg1: map/unmap pll clocks
-:253: WARNING:LONG_LINE: line length
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: skip disabling CTBs before
sanitizing the GuC (rev2)
URL : https://patchwork.freedesktop.org/series/83020/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18780
No functional changes here. Just pass intel_atomic_state
along with crtc_state to certain atomic_check functions.
This will lay the foundation for adding bigjoiner master/slave
states in atomic check.
v2:
* More prep with intel_atomic_state (Ville)
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v7:
* Remove redundant comment (Ville)
* Just keep mode instead of pipe_mode
No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make
> -Original Message-
> From: Josh Boyer
> Sent: Friday, October 23, 2020 4:58 AM
> To: Srivatsa, Anusha
> Cc: linux-firmw...@kernel.org; Kyle McMartin ;
> b...@decadent.org.uk; intel-gfx@lists.freedesktop.org
> Subject: Re: i915 Update : DG1 DMC
>
> Pulled and pushed out.
>
> josh
>
On Tue, Oct 27, 2020 at 10:54:18PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 27, 2020 at 01:43:15PM -0700, Navare, Manasi wrote:
> > On Tue, Oct 27, 2020 at 10:09:20PM +0200, Ville Syrjälä wrote:
> > > On Tue, Oct 27, 2020 at 12:30:33PM -0700, Manasi Navare wrote:
> > > > No functional changes
On Tue, Oct 27, 2020 at 01:43:15PM -0700, Navare, Manasi wrote:
> On Tue, Oct 27, 2020 at 10:09:20PM +0200, Ville Syrjälä wrote:
> > On Tue, Oct 27, 2020 at 12:30:33PM -0700, Manasi Navare wrote:
> > > No functional changes just use hw_mode to retrive
> > > hw.adjusted_mode during HW state readout
On Tue, Oct 27, 2020 at 10:06:53PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 27, 2020 at 12:30:32PM -0700, Manasi Navare wrote:
> > No functional changes here. Just pass intel_atomic_state
> > along with crtc_state to certain atomic_check functions.
> > This will lay the foundation for adding
On Tue, Oct 27, 2020 at 10:17:35PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 27, 2020 at 12:30:34PM -0700, Manasi Navare wrote:
> > From: Maarten Lankhorst
> >
> > Small changes to intel_dp_mode_valid(), allow listing modes that
> > can only be supported in the bigjoiner configuration, which is
Chris Wilson writes:
> On bxt, we require a VT'd w/a to serialise all GGTT updates with memory
> transfers, and use stop_machine() for this purpose. stop_machine() is a
> global serialisation barrier and so dangerous to use from within
> critical sections, as the stop_machine() will wait for all
On Tue, Oct 27, 2020 at 11:17:40AM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's first gvt fixes for 5.10 which includes more vGPU
> suspend/resume fix in HWSP reset handling, and also fix for host i915
> suspend regression when vGPU is created (not need to be active), and
> one workaround for
On Tue, Oct 27, 2020 at 10:09:20PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 27, 2020 at 12:30:33PM -0700, Manasi Navare wrote:
> > No functional changes just use hw_mode to retrive
> > hw.adjusted_mode during HW state readout for clarity
> > in bigjoiner case.
>
> Still don't understnad what
From: Ville Syrjälä
Readout the dbuf related stuff during driver init/resume and
stick it into our dbuf state.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4 --
drivers/gpu/drm/i915/intel_pm.c | 48 +++-
From: Ville Syrjälä
Generalize icl_get_first_dbuf_slice_offset() into something that
just gives us the start+end of the dbuf chunk covered by the
specified slices as a standard ddb entry. Initial idea was to use
it during readout as well, but we shall see.
Cc: Stanislav Lisovskiy
From: Ville Syrjälä
Extract the code to calculate the weights used to chunk up the dbuf
between pipes. There's still extra stuff in there that shouldn't be
there and must be moved out, but that requires a bit more state to
be tracked in the dbuf state.
Cc: Stanislav Lisovskiy
Signed-off-by:
From: Ville Syrjälä
Put the code into a function with a descriptive name. Also relocate
the code a bit help future work.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 36 +++--
drivers/gpu/drm/i915/intel_pm.h | 1 -
2
From: Ville Syrjälä
skl_ddb_get_pipe_allocation_limits() doesn't care how the weights
for distributing the ddb are caclculated for each pipe. Put that
calculation into a separate function so that such mundane details
are hidden from view.
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä
The remainder of my original dbuf state series. We merged most of it
in but would be good to get rid of the remaining warts as some of
those have been causing grief to actual users.
Ville Syrjälä (8):
drm/i915: Extract intel_crtc_ddb_weight()
drm/i915: Pass the crtc to
From: Ville Syrjälä
In order to make the dbuf state computation less fragile
let's make it stand on its own feet by now requiring someone
to peek into a crystall ball ahead of time to figure out
which pipes need to be added to the state under which potential
future conditions. Instead we compute
From: Ville Syrjälä
skl_compute_dbuf_slices() has no use for the crtc state, so
just pass the crtc itself.
Reviewed-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff
From: Ville Syrjälä
The dbuf state will be where we collect all the inter-pipe dbuf
allocation stuff. Start by moving the actual per-pipe ddb entries
there.
v2: Rebase
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21
On Tue, Oct 27, 2020 at 12:30:34PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst
>
> Small changes to intel_dp_mode_valid(), allow listing modes that
> can only be supported in the bigjoiner configuration, which is
> not supported yet.
>
> v11:
> * Make intel_dp_can_bigjoiner non static
On Tue, 2020-10-27 at 01:04 +, Souza, Jose wrote:
> On Mon, 2020-10-26 at 21:40 +, Mun, Gwan-gyeong wrote:
> > On Tue, 2020-10-13 at 16:01 -0700, José Roberto de Souza wrote:
> > > Now using plane damage clips property to calcualte the damaged area.
> > > Selective fetch only supports one
On Tue, Oct 27, 2020 at 12:30:33PM -0700, Manasi Navare wrote:
> No functional changes just use hw_mode to retrive
> hw.adjusted_mode during HW state readout for clarity
> in bigjoiner case.
Still don't understnad what this has to do with bigjoiner. Looks
like a simple introduction of a strangely
On Tue, Oct 27, 2020 at 12:30:32PM -0700, Manasi Navare wrote:
> No functional changes here. Just pass intel_atomic_state
> along with crtc_state to certain atomic_check functions.
> This will lay the foundation for adding bigjoiner master/slave
> states in atomic check.
>
> v2:
> * More prep
On Tue, Oct 27, 2020 at 12:30:30PM -0700, Manasi Navare wrote:
> From: Maarten Lankhorst
>
> With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
> because of this, we need a pipe_mode for various calculations, including
> for example watermarks, plane clipping, etc.
>
> v6:
>
No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
1 file changed, 6
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v11:
* Make intel_dp_can_bigjoiner non static
so it can be used in intel_display (Manasi)
v10:
* Simplify logic (Ville)
*
No functional changes here. Just pass intel_atomic_state
along with crtc_state to certain atomic_check functions.
This will lay the foundation for adding bigjoiner master/slave
states in atomic check.
v2:
* More prep with intel_atomic_state (Ville)
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
From: Maarten Lankhorst
With bigjoiner, there will be 2 pipes driving 2 halfs of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.
v6:
* renaming in separate function, only pipe_mode here (Ville)
* Add description
No functional changes just use hw_mode to retrive
hw.adjusted_mode during HW state readout for clarity
in bigjoiner case.
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 22 +++-
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git
Big joiner enabling prep
Maarten Lankhorst (2):
drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
Manasi Navare (3):
drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner
modes
On Tue, Oct 27, 2020 at 11:19:16AM -0700, Navare, Manasi wrote:
> On Tue, Oct 27, 2020 at 03:42:30PM +0200, Ville Syrjälä wrote:
> > On Mon, Oct 26, 2020 at 03:41:48PM -0700, Navare, Manasi wrote:
> > > On Mon, Oct 26, 2020 at 10:18:54PM +0200, Ville Syrjälä wrote:
> > > > On Wed, Oct 21, 2020 at
On Tue, Oct 27, 2020 at 7:51 PM Christoph Hellwig wrote:
> Is there a list that has the cover letter and the whole series?
> I've only found fragments (and mostly the same fragments) while
> wading through my backlog in various list folders..
Typoed git send-email command that I only caught
On bxt, we require a VT'd w/a to serialise all GGTT updates with memory
transfers, and use stop_machine() for this purpose. stop_machine() is a
global serialisation barrier and so dangerous to use from within
critical sections, as the stop_machine() will wait for all cpus to enter
the stop_machine
On Tue, Oct 27, 2020 at 03:42:30PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 26, 2020 at 03:41:48PM -0700, Navare, Manasi wrote:
> > On Mon, Oct 26, 2020 at 10:18:54PM +0200, Ville Syrjälä wrote:
> > > On Wed, Oct 21, 2020 at 10:42:21PM -0700, Manasi Navare wrote:
> > > > From: Maarten Lankhorst
On 10/27/20 5:25 PM, Thomas Hellström (Intel) wrote:
+
+ if (WARN_ON(!i915_gem_object_trylock(tl->hwsp_ggtt->obj)))
+ return -EBUSY;
I think we should either annotate this properly as an isolated lock,
or allow a silent -EBUSY.
This is done in a controlled selftest where we mock
On Tue, Oct 27, 2020 at 03:39:08PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 26, 2020 at 03:33:36PM -0700, Navare, Manasi wrote:
> > On Fri, Oct 23, 2020 at 09:00:25PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 21, 2020 at 10:42:20PM -0700, Manasi Navare wrote:
> > > > Skip iterating over
On Tue, 2020-10-27 at 13:34 +, Mun, Gwan-gyeong wrote:
> On Tue, 2020-10-13 at 16:01 -0700, José Roberto de Souza wrote:
> > Planes can individually have transparent, move or have visibility
> > changed if any of those happens, planes bellow it will be visible or
> > have more pixels of it
On Mon, 2020-10-26 at 21:46 -0700, Lucas De Marchi wrote:
> Do not create the display debugfs files when we don't have display.
>
> Based on previous patch by José Souza.
>
Reviewed-by: José Roberto de Souza
> Cc: José Roberto de Souza
> Cc: Jani Nikula
> Signed-off-by: Lucas De Marchi
>
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
It is based upon the actual number of MST streams and size
of wired_cmd_repeater_auth_stream_req_in.
Excluding the size of hdcp_cmd_header.
v2:
hdcp_cmd_header size annotation nitpick. [Tomas]
Cc: Tomas Winkler
Cc: Ramalingam C
Let's define Maximum MST content streams up to four
generically which can be supported by modern display
controllers.
Cc: Sean Paul
Cc: Ramalingam C
Acked-by: Maarten Lankhorst
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
include/drm/drm_hdcp.h | 8
1 file changed, 4
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
v2:
Init the hdcp port data k for HDMI/DP SST strem.
v3:
Cosmetic changes. [Uma]
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++
1 file changed, 30 insertions(+)
diff --git
Enable HDCP 2.2 over DP MST.
Authenticate and enable port encryption only once for
an active HDCP 2.2 session, once port is authenticated
and encrypted enable encryption for each stream that
requires encryption on this port.
Similarly disable the stream encryption for each encrypted
stream, once
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
Added a WARN_ON() instead of drm_err. [Uma]
Cosmetic chnages. [Uma]
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
Enable HDCP 1.4 over DP MST for Gen12.
This also enable the stream encryption support for
older generations, which was missing earlier.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
v3:
- Cosmetic change, removed the value less
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
fastset instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actual hdcp->value was ENABLED.
This
This is v4 version to test with IGT
https://patchwork.freedesktop.org/series/82987/
This has addressed the review comments from Uma.
It has been also tested manually with IGT above series.
[PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
has an Ack from Tomas to merge it via
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Signed-off-by: Anshuman
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä"
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp.c
On 10/27/20 3:31 PM, Maarten Lankhorst wrote:
Op 27-10-2020 om 12:03 schreef Thomas Hellström (Intel):
On 10/15/20 1:25 PM, Maarten Lankhorst wrote:
We're starting to require the reservation lock for pinning,
so wait until we have that.
Update the selftests to handle this correctly, and
The atomic check hooks must look up the encoder to be used with a
connector from the connector's atomic state, and not assume that it's
the connector's current attached encoder. The latter one can change
under the atomic check func, or can be unset yet as in the case of MST
connectors.
This fixes
Op 27-10-2020 om 12:03 schreef Thomas Hellström (Intel):
>
> On 10/15/20 1:25 PM, Maarten Lankhorst wrote:
>> We're starting to require the reservation lock for pinning,
>> so wait until we have that.
>>
>> Update the selftests to handle this correctly, and ensure pin is
>> called in
Once upon a time we used to do this by default, back when it was a
global seqno with a global barrier on wrap. Since the switch of
per-client timelines, handling the wrap is cheaper and yet more
complicated, and so worth encouraging early wraps once more.
Suggested-by: Thomas Hellström
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