== Series Details ==
Series: series starting with [1/8] drm/i915/display: add namespace to
intel_prepare_reset
URL : https://patchwork.freedesktop.org/series/83596/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9285_full -> Patchwork_18870_full
===
== Series Details ==
Series: series starting with [1/8] drm/i915/display: add namespace to
intel_prepare_reset
URL : https://patchwork.freedesktop.org/series/83596/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9285 -> Patchwork_18870
=
== Series Details ==
Series: series starting with [1/8] drm/i915/display: add namespace to
intel_prepare_reset
URL : https://patchwork.freedesktop.org/series/83596/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be che
On Fri, Nov 06, 2020 at 02:55:28PM -0800, Lucas De Marchi wrote:
From: José Roberto de Souza
Power wells are only part of display block and not necessary when
we don't have display.
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/
On 11/6/20 1:00 PM, Lucas De Marchi wrote:
> DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
> DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
> single macro that chooses the correct register according to the phy
> being accessed, use the correct bitfie
Rename intel_finish_reset to intel_display_finish_reset, so it's clear
from gt/ that we are calling out the display code.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/gt/intel_res
In intel_irq_init() move what's display/hpd related after what is gt and
guc. This makes it easier to support !HAS_DISPLAY() in future.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i
== Series Details ==
Series: drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83592/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9284_full -> Patchwork_18869_full
Summary
---
**FAIL
From: Jani Nikula
!HAS_DISPLAY() implies !HAS_OVERLAY(), skipping overlay setup anyway, so
return earlier from intel_modeset_init() for clarity.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file chang
From: José Roberto de Souza
Power wells are only part of display block and not necessary when
we don't have display.
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 +
1 file changed, 5 inserti
Rename intel_prepare_reset to intel_display_prepare_reset, so it's clear
from gt/ that we are calling out the display code.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/gt/intel_r
Now that hpd/display related calls are split from the rest in
intel_irq_init(), skip all of that in case we don't have display.
Cc: José Roberto de Souza
Cc: Jani Nikula
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/dr
From: José Roberto de Souza
Display is always disabled and enabled when resetting any engine, but if
there is no display it should not do anything with display and only
reset the needed engines.
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/g
Use the convention of new platforms first. No need to special case
HAS_GMCH() since that stopped being true at the lattest on gen8 (for
cherryview).
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions
On Thu, Nov 05, 2020 at 05:18:42PM -0800, Daniele Ceraolo Spurio wrote:
> From: Venkata Sandeep Dhanalakota
>
> SFC capability of video engines is not set correctly because i915
> is testing for incorrect bits.
>
> Fixes: c5d3e39caa45 ("drm/i915: Engine discovery query")
> Cc: Matt Roper
> Cc:
== Series Details ==
Series: drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83592/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9284 -> Patchwork_18869
Summary
---
**SUCCESS**
N
== Series Details ==
Series: drm/i915/dg1: map/unmap pll clocks
URL : https://patchwork.freedesktop.org/series/83592/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a589e37423a2 drm/i915/dg1: map/unmap pll clocks
-:187: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functio
> On Nov 4, 2020, at 9:17 PM, Anshuman Gupta wrote:
>
> On 2020-11-03 at 17:06:42 -0500, Rodrigo Vivi wrote:
>> On Fri, Oct 30, 2020 at 11:46:58AM +0530, Anshuman Gupta wrote:
>>> From: Bob Paauwe
>>>
>>> The WA specifies that we need to toggle a SDE chicken bit on and then
>>> off as the fi
== Series Details ==
Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from
skl+ wm code
URL : https://patchwork.freedesktop.org/series/83589/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9283 -> Patchwork_18868
==
== Series Details ==
Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from
skl+ wm code
URL : https://patchwork.freedesktop.org/series/83589/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: drm/vgem: replace idr_init() by idr_init_base()
URL : https://patchwork.freedesktop.org/series/83586/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9281_full -> Patchwork_18867_full
Summary
From: Ville Syrjälä
In order to remove intel_atomic_crtc_state_for_each_plane_state()
from skl_crtc_can_enable_sagv() we can simply precompute whether
each wm level can tolerate the SAGV block time latency or not.
This has the nice side benefit that we remove the duplicated
wm level latency calc
From: Ville Syrjälä
Document what each of the "raw" vs. "optimal" vs. "intermediate"
watermarks do.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 48 ++-
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
From: Ville Syrjälä
Replace skl_adjusted_plane_pixel_rate() with the generic
intel_plane_pixel_rate(). The two should produce identical
results.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 27 ++-
1 file changed, 2 insertions(+), 25 deletions(-)
From: Ville Syrjälä
intel_atomic_crtc_state_for_each_plane_state() peeks at the
plane's current state without holding the plane's mutex, trusting
that the crtc's mutex will protect it. In practice that does work
since our planes can't move between pipes, but it sets a bad
example. intel_atomic_cr
From: Ville Syrjälä
Get rid of intel_atomic_crtc_state_for_each_plane_state() from the
skl+ wm code so that we don't have to bother messing with it for
bigjoiner support.
Ville Syrjälä (6):
drm/i915: Pass intel_atomic_state around
drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state()
From: Ville Syrjälä
Store the relative data rate for planes in the crtc state
so that we don't have to use
intel_atomic_crtc_state_for_each_plane_state() to compute
it even for the planes that are no part of the current state.
Should probably just nuke this stuff entirely an use the normal
plane
From: Ville Syrjälä
Pass the whole intel_atomic_state to skl_build_pipe_wm()
and skl_allocate_pipe_ddb() so we can start to iterate
stuff containerd in the commit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 24 +---
1 file changed, 13 insertions(+),
== Series Details ==
Series: drm/vgem: replace idr_init() by idr_init_base()
URL : https://patchwork.freedesktop.org/series/83586/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9281 -> Patchwork_18867
Summary
---
**S
idr_init() uses base 0 which is an invalid identifier. The new function
idr_init_base allows IDR to set the ID lookup from base 1. This avoids
all lookups that otherwise starts from 0 since 0 is always unused.
References: commit 6ce711f27500 ("idr: Make 1-based IDRs more efficient")
Signed-off-by
On 05/11/2020 18:43, Chris Wilson wrote:
Use userfault to arbitrarily delay the completion of copy_from_user() in
order to trap many, many threads inside the core of
gem_pread/gem_pwrite. This allows us to exhaust the preferred paths and
potentially trip over unexpected fallback paths.
Suggested
Quoting Tvrtko Ursulin (2020-11-06 15:17:12)
>
> On 04/11/2020 17:09, Chris Wilson wrote:
> > Use MI_MATH and MI_COND_BBE we can construct a loop that runs for a
> > precise number of clock cycles, as measured by the CTX_TIMESTAMP. We use
> > the CTX_TIMESTAMP (as opposed to the CS_TIMESTAMP) so t
On 04/11/2020 17:09, Chris Wilson wrote:
Use MI_MATH and MI_COND_BBE we can construct a loop that runs for a
precise number of clock cycles, as measured by the CTX_TIMESTAMP. We use
the CTX_TIMESTAMP (as opposed to the CS_TIMESTAMP) so that the elapsed
time is measured local to the context, and
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83577/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9281_full -> Patchwork_18866_full
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83577/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9281 -> Patchwork_18866
==
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83577/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be chec
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/83577/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
389cbe50c345 drm/i915/display: Support PSR Multiple Transcoders
-:1
On 2020-10-27 at 22:11:55 +0530, Anshuman Gupta wrote:
> Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
> It requires to call intel_hdcp_handle_cp_irq() in case
> of CP_IRQ is triggered by a sink in DP-MST topology.
>
> Cc: "Ville Syrjälä"
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
Reviewed
On 2020-10-27 at 22:12:08 +0530, Anshuman Gupta wrote:
> Enable HDCP 2.2 over DP MST.
> Authenticate and enable port encryption only once for
> an active HDCP 2.2 session, once port is authenticated
> and encrypted enable encryption for each stream that
> requires encryption on this port.
>
> Simi
On 2020-10-27 at 22:12:01 +0530, Anshuman Gupta wrote:
> hdcp_port_data is specific to a port on which HDCP
> encryption is getting enabled, so encapsulate it to
> intel_digital_port.
> This will be required to enable HDCP 2.2 stream encryption.
>
> Cc: Ramalingam C
> Reviewed-by: Uma Shankar
>
On 2020-11-06 at 12:05:14 +0530, Anshuman Gupta wrote:
> On 2020-11-05 at 22:04:15 +0530, Ramalingam C wrote:
> > On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> > > Add support for multiple mst stream in hdcp port data
> > > which will be used by RepeaterAuthStreamManage msg and
> > > HDC
On Tue, Oct 27, 2020 at 10:39:53PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract the code to calculate the weights used to chunk up the dbuf
> between pipes. There's still extra stuff in there that shouldn't be
> there and must be moved out, but that requires a bit more state to
>
On Tue, Oct 27, 2020 at 10:39:52PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The dbuf state will be where we collect all the inter-pipe dbuf
> allocation stuff. Start by moving the actual per-pipe ddb entries
> there.
>
> v2: Rebase
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Vill
On 2020-11-06 at 14:57:25 +0530, Ramalingam C wrote:
> On 2020-11-03 at 11:57:00 +0530, Anshuman Gupta wrote:
> > Add support for HDCP 2.2 DP MST shim callback.
> > This adds existing DP HDCP shim callback for Link Authentication
> > and Encryption and HDCP 2.2 stream encryption
> > callback.
> >
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
---
.../drm/i915/display/intel
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handlin
Quoting Chris Wilson (2020-11-06 10:02:46)
> Quoting Tvrtko Ursulin (2020-11-06 09:30:05)
> >
> > On 06/11/2020 01:18, Daniele Ceraolo Spurio wrote:
> > > From: Venkata Sandeep Dhanalakota
> > >
> > > SFC capability of video engines is not set correctly because i915
> > > is testing for incorrec
Quoting Tvrtko Ursulin (2020-11-06 09:30:05)
>
> On 06/11/2020 01:18, Daniele Ceraolo Spurio wrote:
> > From: Venkata Sandeep Dhanalakota
> >
> > SFC capability of video engines is not set correctly because i915
> > is testing for incorrect bits.
> >
> > Fixes: c5d3e39caa45 ("drm/i915: Engine d
On 06/11/2020 01:18, Daniele Ceraolo Spurio wrote:
From: Venkata Sandeep Dhanalakota
SFC capability of video engines is not set correctly because i915
is testing for incorrect bits.
Fixes: c5d3e39caa45 ("drm/i915: Engine discovery query")
Cc: Matt Roper
Cc: Tvrtko Ursulin
Signed-off-by: Ve
On 2020-11-03 at 11:57:00 +0530, Anshuman Gupta wrote:
> Add support for HDCP 2.2 DP MST shim callback.
> This adds existing DP HDCP shim callback for Link Authentication
> and Encryption and HDCP 2.2 stream encryption
> callback.
>
> v2:
> Added a WARN_ON() instead of drm_err. [Uma]
> Cosmetic ch
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