On Tue, Nov 17, 2020 at 07:33:11PM +, Jose Souza wrote:
On Tue, 2020-11-17 at 11:28 -0800, Lucas De Marchi wrote:
On Tue, Nov 17, 2020 at 07:03:05PM +, Jose Souza wrote:
> On Tue, 2020-11-17 at 10:50 -0800, Aditya Swarup wrote:
> > Fix macros for applying TGL SOC WAs by using
+Rodrigo, +Joonas
On Tue, Nov 17, 2020 at 10:50:08AM -0800, Aditya Swarup wrote:
v2 of the patch series to introduce ADL-S.
v1 for the series is posted at:
https://patchwork.freedesktop.org/series/82917/
This series is rebased after hotplug refactors and review
comments addressed from v1.
== Series Details ==
Series: drm/i915: Register DMAR fault handler
URL : https://patchwork.freedesktop.org/series/83967/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9350_full -> Patchwork_18925_full
Summary
---
On Mon, 16 Nov 2020 11:17:56 +0100 Mauro Carvalho Chehab wrote:
> Kernel-doc has always be limited to a probably bad documented
> rule:
>
> The kernel-doc markups should appear *imediatelly before* the
> function or data structure that it documents.
Applied 1-3 to net-next, thanks!
On Tue, Nov 17, 2020 at 05:40:28PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
I totally fumbled the ?: usage when generating the DDI encoder
names. Reverse the things that need reversing, and to make it
a bit less messy add a few macros to hide the arithmetic on the
port enums.
Cc: Jani
== Series Details ==
Series: drm/i915: Fix the DDI encoder names
URL : https://patchwork.freedesktop.org/series/83966/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350_full -> Patchwork_18924_full
Summary
---
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced this warning:
Documentation/gpu/todo.rst:302: WARNING: Unexpected indentation.
Documentation/gpu/todo.rst:303: WARNING: Block quote ends without a blank line;
unexpected unindent.
Introduced by commit
== Series Details ==
Series: drm/i915/lspcon: enter standby mode to enhance power saving (rev2)
URL : https://patchwork.freedesktop.org/series/83886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18931
== Series Details ==
Series: drm/i915/rkl: new rkl ddc map for different PCH (rev5)
URL : https://patchwork.freedesktop.org/series/83154/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9350_full -> Patchwork_18923_full
After system boot up, LSPCON will be configured as PCON mode.
But it never go into power saving state. Source driver can
do the following. Then LSPCON can enter standby mode
automatically to save more power.
1. At PCON mode, source driver write 0x2 to DPCD 600h.
2. At LS mode, try to disable
On Tue, Nov. 17, 2020, 4:29 p.m., Ville Syrjälä wrote:
>On Mon, Nov 16, 2020 at 09:59:13PM +0800, Lee Shawn C wrote:
>> After system boot up, LSPCON will be configured as PCON mode.
>> But it never go into power saving state. Source driver can do the
>> following. Then LSPCON can enter standby
== Series Details ==
Series: drm/i915/perf: workaround register corruption in OATAILPTR
URL : https://patchwork.freedesktop.org/series/83956/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9350_full -> Patchwork_18922_full
== Series Details ==
Series: Rebased remaining big joiner series
URL : https://patchwork.freedesktop.org/series/83990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18928
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gt: Pull intel_gt_init_hw() into
intel_gt_resume() (rev2)
URL : https://patchwork.freedesktop.org/series/71265/
State : failure
== Summary ==
Applying: drm/i915/gt: Pull intel_gt_init_hw() into intel_gt_resume()
Using index
== Series Details ==
Series: i915/gem_flink_race: Fix error in buffer usage
URL : https://patchwork.freedesktop.org/series/83995/
State : failure
== Summary ==
Applying: i915/gem_flink_race: Fix error in buffer usage
error: sha1 information is lacking or useless (tests/i915/gem_flink_race.c).
== Series Details ==
Series: drm/i915/gem: Remove incorrect early dbg print
URL : https://patchwork.freedesktop.org/series/83953/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9350_full -> Patchwork_18921_full
Summary
== Series Details ==
Series: Rebased remaining big joiner series
URL : https://patchwork.freedesktop.org/series/83990/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: Rebased remaining big joiner series
URL : https://patchwork.freedesktop.org/series/83990/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d8255ae03ad0 drm/i915: Copy the plane hw state directly for Y planes
385ac914e475 drm/i915/dp: Allow big joiner
== Series Details ==
Series: Introduce Alderlake-S (rev2)
URL : https://patchwork.freedesktop.org/series/82917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18927
Summary
---
**SUCCESS**
No
On Wed, Nov 04, 2020 at 10:11:53AM +, Chris Wilson wrote:
Quoting Joonas Lahtinen (2020-11-04 10:05:32)
Quoting Chris Wilson (2019-12-22 16:40:46)
> From: Andi Shyti
>
> The GT system is becoming more and more a stand-alone system in
> i915 and it's fair to assign it its own debugfs
== Series Details ==
Series: Introduce Alderlake-S (rev2)
URL : https://patchwork.freedesktop.org/series/82917/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: Introduce Alderlake-S (rev2)
URL : https://patchwork.freedesktop.org/series/82917/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b9c32f37d365 drm/i915/dg1: Enable ports
022d6eeef421 drm/i915/tgl: Fix macros for TGL SOC based WA
d26e247df015
== Series Details ==
Series: drm/i915/phy: Quieten state loss across suspend
URL : https://patchwork.freedesktop.org/series/83980/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18926
Summary
---
== Series Details ==
Series: drm/i915/phy: Quieten state loss across suspend
URL : https://patchwork.freedesktop.org/series/83980/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
388a021a278b drm/i915/phy: Quieten state loss across suspend
-:20: WARNING:BAD_SIGN_OFF: email
== Series Details ==
Series: drm/i915: Register DMAR fault handler
URL : https://patchwork.freedesktop.org/series/83967/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18925
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Fix the DDI encoder names
URL : https://patchwork.freedesktop.org/series/83966/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18924
Summary
---
**SUCCESS**
Sent from my iPhone
> On Nov 17, 2020, at 2:28 PM, Chris Wilson wrote:
>
> Quoting Steve Hampson (2020-11-17 22:23:08)
>> A buffer in function test_flink_name was both too small and never
>> checked for overflow. Both errors are fixed.
>
> That many numbers is not interesting. Show the
== Series Details ==
Series: drm/i915/rkl: new rkl ddc map for different PCH (rev5)
URL : https://patchwork.freedesktop.org/series/83154/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18923
Summary
== Series Details ==
Series: series starting with [01/28] drm/i915/selftests: Improve granularity
for mocs reset checks
URL : https://patchwork.freedesktop.org/series/83951/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9348_full -> Patchwork_18920_full
Quoting Steve Hampson (2020-11-17 22:23:08)
> A buffer in function test_flink_name was both too small and never
> checked for overflow. Both errors are fixed.
That many numbers is not interesting. Show the range and median instead.
-Chris
___
Intel-gfx
A buffer in function test_flink_name was both too small and never
checked for overflow. Both errors are fixed.
Signed-off-by: Steve Hampson
Reviewed-by: Ashutosh Dixit
---
tests/i915/gem_flink_race.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git
== Series Details ==
Series: drm/i915/perf: workaround register corruption in OATAILPTR
URL : https://patchwork.freedesktop.org/series/83956/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18922
Summary
== Series Details ==
Series: drm/i915/gem: Remove incorrect early dbg print
URL : https://patchwork.freedesktop.org/series/83953/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9350 -> Patchwork_18921
Summary
---
On Tue, Nov 17, 2020 at 11:01:28AM +, Chris Wilson wrote:
The OA subsystem would like to enable its privileged clients access to
the OA registers from execbuf. This requires temporarily removing the
HW validation from those registers for the duration of the OA client,
for which we need to
From: Ville Syrjälä
The legacy cursor fastpath code doesn't deal with bigjoiner.
Disable the fastpath for now.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Ville Syrjälä
Add a big of bigjoiner information to the state dump.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Make sure both crtcs participating in the bigjoiner stuff
are in the state.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 25
1 file changed, 25 insertions(+)
diff --git
From: Maarten Lankhorst
We need to look at hw.fb for the framebuffer, and add the translation
for the slave_plane_state. With these changes we set the correct
rectangle on the bigjoiner slave, and don't set incorrect
src/dst/visibility on the slave plane.
v2:
* Manual rebase (Manasi)
v3:
*
From: Maarten Lankhorst
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied
From: Ville Syrjälä
We can't call drm_plane_state_src() this late for the slave plane since
it would consult the wrong uapi state. We've alreayd done the correct
uapi->hw copy earlier, so let's just preserve the unclipped src/dst
rects using a temp copy across the
From: Ville Syrjälä
When doing the plane state copy from the UV plane to the Y plane
let's just copy the hw state directly instead of using the original
uapi state. The UV plane has already had its uapi state copied into
its hw state, so this extra detour via the uapi state for the Y plane
is
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
So remove encoder usage from dsc functions.
Signed-off-by: Manasi Navare
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
From: Ville Syrjälä
When using bigjoiner userspace is only controlling the "master"
plane, so use its uapi state for the "slave" plane as well.
hw.crtc needs a bit of magic since we don't want to copy that from
the uapi state (as it points to the wrong pipe for the "slave
" plane). Instead we
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction
From: Ville Syrjälä
Enough plumbing should be in place to throw the bigjoiner switch.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
Enabling is done in a special sequence and so should plane updates
be. Ideally the end user never notices the second pipe is used.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
This uses generic modeset_enables() calls like trans port sync
From: Ville Syrjälä
Make sure both the bigjoiner "master" and "slave" plane are
in the state whenever either of them is in the state.
Signed-off-by: Ville Syrjälä
Reviewed-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 42
1 file changed, 42
Maarten Lankhorst (4):
drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.
drm/i915: Try to make bigjoiner work in atomic check
drm/i915: Add bigjoiner aware plane clipping checks
drm/i915: Add debugfs dumping for bigjoiner, v3.
Manasi Navare (3):
drm/i915/dp: Modify
From: Maarten Lankhorst
Dump debugfs and planar links as well, this will make it easier to debug
when things go wrong.
v4:
* Rebase
Changes since v1:
- Report planar slaves as such, now that we have the plane_state switch.
Changes since v2:
- Rebase on top of the new plane format dumping
From: Maarten Lankhorst
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
v13:
* Allow bigjoiner if hdisplay >5120
v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in
On Tue, 2020-11-17 at 11:28 -0800, Lucas De Marchi wrote:
> On Tue, Nov 17, 2020 at 07:03:05PM +, Jose Souza wrote:
> > On Tue, 2020-11-17 at 10:50 -0800, Aditya Swarup wrote:
> > > Fix macros for applying TGL SOC WAs by using INTEL_REVID()
> > > as index to fetch correct revision offset in
On Tue, Nov 17, 2020 at 10:50:10AM -0800, Aditya Swarup wrote:
@@ -1579,9 +1579,9 @@ static inline const struct i915_rev_steppings *
tgl_revids_get(struct drm_i915_private *dev_priv)
{
if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
- return tgl_uy_revids;
+
On Tue, Nov 17, 2020 at 07:03:05PM +, Jose Souza wrote:
On Tue, 2020-11-17 at 10:50 -0800, Aditya Swarup wrote:
Fix macros for applying TGL SOC WAs by using INTEL_REVID()
as index to fetch correct revision offset in TGL GT/DISP stepping
table.
Please explain what exactly is the issue you
== Series Details ==
Series: series starting with [01/28] drm/i915/selftests: Improve granularity
for mocs reset checks
URL : https://patchwork.freedesktop.org/series/83951/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9348 -> Patchwork_18920
On Tue, 17 Nov 2020, Aditya Swarup wrote:
> From: Caz Yokoyama
>
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been
> removed from ADLS. Disable PSR2 till we
Hi Anshuman,
Quoted "Currently this api used by Patch 27 of this series, uses gem object
user flag (obj->user_flags) to pass as gem_object_metadata but it is unused ?
why do we need this gem_object_metadata ?"
Yes, you are correct, the argument gem_object_metadata of
On Tue, 2020-11-17 at 10:50 -0800, Aditya Swarup wrote:
> Fix macros for applying TGL SOC WAs by using INTEL_REVID()
> as index to fetch correct revision offset in TGL GT/DISP stepping
> table.
Please explain what exactly is the issue you are fixing, the change you did in
tgl_revids_get() +
== Series Details ==
Series: series starting with [01/28] drm/i915/selftests: Improve granularity
for mocs reset checks
URL : https://patchwork.freedesktop.org/series/83951/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit
== Series Details ==
Series: series starting with [01/28] drm/i915/selftests: Improve granularity
for mocs reset checks
URL : https://patchwork.freedesktop.org/series/83951/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ae32abe5ed3c drm/i915/selftests: Improve granularity for
From: Matt Roper
ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
TGL did, making them all firmware-compatible. Let's re-use TGL's
firmware for ADL-S.
Bspec: 50668
Cc: John Harrison
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
---
From: Matt Roper
ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.
Bspec: 49291
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
---
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and
E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De
From: Caz Yokoyama
The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt
From: Anusha Srivatsa
Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Aditya Swarup
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_csr.c
From: José Roberto de Souza
- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
the cursor plane, let's group the handling together under
HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.
BSpec: 49251
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc:
From: Lucas De Marchi
TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.
Bspec: 53597
Cc: Imre Deak
Cc: Matt Roper
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
From: Tejas Upadhyay
Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms. Update the values used
by our memory bandwidth calculations accordingly.
Bspec: 64631
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
- Inherit the gen12 workarounds.
- Add placeholders to setup GT WA.
- Extend permanent driver WA Wa_1409767108 to adl-s and
Wa_14010685332 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s
- Add Wa_14011765242 for adl-s A0 stepping.
v2:
- Extend Wa_14010919138 and Wa_14010229206 to
Initialize display outputs and add HTI support for ADL-S. ADL-S has 5
display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_display.c | 8
From: Matt Roper
ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.
Bspec: 49291
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
---
ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
Combo PHY A still uses the old ddc pin mapping.
From VBT, ddc pin info suggests the following mapping:
VBTDRIVER
DDI B->ddc_pin=2 should translate to PORT_D->0x9
DDI C->ddc_pin=3 should translate
From: Anusha Srivatsa
Add support for Alderpoint(ADP) PCH used with Alderlake-S.
v2:
- Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Caz Yokoyama
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
Add changes for configuring DPLL for ADL-S
- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
- Extend CNL macro to choose DPLL_ENABLE
for ADL-S.
- Select CFGCR0 and CFGCR1 for ADL-S plls.
On BSpec: 53720 PLL arrangement dig for adls:
DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
DPLL3 cfgcr is
From: Anusha Srivatsa
Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
Reviewed-by:
From: Anusha Srivatsa
ADLS follows ICP/TGP like interrupts.
v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas)
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Signed-off-by: Lucas
Add changes to configure port clock registers for ADL-S. Combo phy port
clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
translates to
DDI A -> DDIA
DDI B -> USBC1
DDI I -> USBC2
For DPCLKA_CFGCR1
DDI J ->
From: Caz Yokoyama
- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been
removed from ADLS. Disable PSR2 till we enable software/
manual tracking.
v2:
- Add support
From: Caz Yokoyama
ADL_S re-uses the same stolen memory registers as TGL and ICL.
This patch has a dependency on:
("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc:
Fix macros for applying TGL SOC WAs by using INTEL_REVID()
as index to fetch correct revision offset in TGL GT/DISP stepping
table.
Also, remove redundant macros and simplify it to use GT and DISP
macros for getting applicable stepping for TGL.
Fixes: ("drm/i915/tgl: Fix stepping WA matching")
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the
v2 of the patch series to introduce ADL-S.
v1 for the series is posted at:
https://patchwork.freedesktop.org/series/82917/
This series is rebased after hotplug refactors and review
comments addressed from v1.
Please ignore the DG1 patch as it is cherry-picked to fix
conflicts.
Aditya Swarup
This is quite different and much cleane from my original patch :), so
you should be the author. With that, this is
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
On Tue, Nov 17, 2020 at 11:01:26AM +, Chris Wilson wrote:
From: Umesh Nerlige Ramappa
Switch the search and grow code of
On Tue, Nov 17, 2020 at 11:01:27AM +, Chris Wilson wrote:
Strip the encoded bits from the register offset so that we only use the
address for looking up the RING_NONPRIV entry.
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
---
Quoting Souza, Jose (2020-11-17 17:19:19)
> On Tue, 2020-11-17 at 17:14 +, Chris Wilson wrote:
> > When the HW is powered down, the register state and links are lost. This
> > may be an issue in the firmware, or in the code expectations; whatever
> > it is, it is expected behaviour now for
On Tue, 2020-11-17 at 17:14 +, Chris Wilson wrote:
> When the HW is powered down, the register state and links are lost. This
> may be an issue in the firmware, or in the code expectations; whatever
> it is, it is expected behaviour now for Tigerlake; stop warning!
>
> References:
When the HW is powered down, the register state and links are lost. This
may be an issue in the firmware, or in the code expectations; whatever
it is, it is expected behaviour now for Tigerlake; stop warning!
References: https://gitlab.freedesktop.org/drm/intel/-/issues/2411
Fixes: 239bef676d8e
On Tue, Nov 17, 2020 at 03:01:24PM +0200, Lionel Landwerlin wrote:
After having written the entire OA buffer with reports, the HW will
write again at the beginning of the OA buffer. It'll indicate it by
setting the WRAP bits in the OASTATUS register.
When a wrap happens and that at the end of
On Mon, Nov 16, 2020 at 09:59:13PM +0800, Lee Shawn C wrote:
> After system boot up, LSPCON will be configured as PCON mode.
> But it never go into power saving state. Source driver can
> do the following. Then LSPCON can enter standby mode
> automatically to save more power.
>
> 1. At PCON mode,
On Tue, Nov 17, 2020 at 04:36:24PM +0530, Anshuman Gupta wrote:
> On 2020-11-11 at 21:48:13 +, Patchwork wrote:
>
> Hi Matt,
> Could you please help to merge the below patch to dinq.
> It is having RB of rodrigo and CI results also green.
Thanks for the reminder; applied to dinq.
Matt
>
On Tue, Nov 17, 2020 at 05:09:06PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 16, 2020 at 04:33:50PM -0800, Navare, Manasi wrote:
> > On Sat, Nov 14, 2020 at 12:03:56AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > We can't call drm_plane_state_src() this late for the slave
On Tue, Nov 17, 2020 at 05:14:56PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 16, 2020 at 04:09:01PM -0800, Navare, Manasi wrote:
> > On Sat, Nov 14, 2020 at 12:03:51AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Make sure both the bigjoiner "master" and "slave" plane are
>
Quoting Chris Wilson (2020-11-17 15:42:52)
> Attach a iommu [DMAR] fault handler for our device and try and reset the
> GPU upon a fault. At worst this will allow us to more quickly recover
> from a fault, rather than wait 10s for the hangcheck to determine a
> stuctk GPU. At best, it will
On Tue, Nov 17, 2020 at 05:17:15PM +0200, Ville Syrjälä wrote:
> On Mon, Nov 16, 2020 at 04:24:15PM -0800, Navare, Manasi wrote:
> > On Sat, Nov 14, 2020 at 12:03:52AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > When using bigjoiner userspace is only controlling the
Attach a iommu [DMAR] fault handler for our device and try and reset the
GPU upon a fault. At worst this will allow us to more quickly recover
from a fault, rather than wait 10s for the hangcheck to determine a
stuctk GPU. At best, it will immediately restart the GPU and paper over
the bad iommu.
From: Ville Syrjälä
I totally fumbled the ?: usage when generating the DDI encoder
names. Reverse the things that need reversing, and to make it
a bit less messy add a few macros to hide the arithmetic on the
port enums.
Cc: Jani Nikula
Fixes: 2d709a5a624c ("drm/i915: Give DDI encoders even
On Tue, Nov 17, 2020 at 04:33:24PM +0200, Jani Nikula wrote:
> On Wed, 28 Oct 2020, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Let's pimp the DDI encoder->name to reflect what the spec calls them.
> > Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.
> >
> > Also since each encoder
On Mon, Nov 16, 2020 at 04:24:15PM -0800, Navare, Manasi wrote:
> On Sat, Nov 14, 2020 at 12:03:52AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > When using bigjoiner userspace is only controlling the "master"
> > plane, so use its uapi state for the "slave" plane as well.
> >
>
On Mon, Nov 16, 2020 at 04:09:01PM -0800, Navare, Manasi wrote:
> On Sat, Nov 14, 2020 at 12:03:51AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make sure both the bigjoiner "master" and "slave" plane are
> > in the state whenever either of them is in the state.
> >
> >
On Mon, Nov 16, 2020 at 04:33:50PM -0800, Navare, Manasi wrote:
> On Sat, Nov 14, 2020 at 12:03:56AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We can't call drm_plane_state_src() this late for the slave plane since
> > it would consult the wrong uapi state. We've alreayd done
On Sat, Nov 14, 2020 at 12:03:53AM +0200, Ville Syrjala wrote:
> From: Maarten Lankhorst
>
> We need to look at hw.fb for the framebuffer, and add the translation
> for the slave_plane_state. With these changes we set the correct
> rectangle on the bigjoiner slave, and don't set incorrect
>
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