Hi,
Progress here seems to have stalled, or did I miss something?
On 20.11.2020 4.21, Lee, Shawn C wrote:
On Thu, Nov. 19, 2020 at 11:51 PM, Matt Roper wrote:
On Tue, Nov 17, 2020 at 10:26:29PM +0800, Lee Shawn C wrote:
After boot into kernel. Driver configured ddc pin mapping based on
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85017/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9495_full -> Patchwork_19165_full
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev10)
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig |
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c |
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
PXP (Protected Xe Path) is an i915 componment, available on
GEN12+ that helps to establish the hardware protected session
and manage the status of the alive software session, as well
as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 159
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
== Series Details ==
Series: drm/i915/cml : Add TGP PCH support
URL : https://patchwork.freedesktop.org/series/85013/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9494_full -> Patchwork_19163_full
Summary
---
== Series Details ==
Series: drm/i915: Encode fence specific waitqueue behaviour into the wait.flags
URL : https://patchwork.freedesktop.org/series/85012/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9494_full -> Patchwork_19162_full
Hi Wilson,
Thanks for bring up this. This is a necessary step during the booting to allow
the ME communicate with display but we don't need turn off for unload actually.
Best regards,
Sean
-Original Message-
From: Chris Wilson
Sent: Thursday, December 10, 2020 12:45 AM
To: Huang,
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85017/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9495 -> Patchwork_19165
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85017/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d46ab2bc6044 drm/i915/gt: Split logical ring
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/gt: Track all timelines created
using the HWSP
URL : https://patchwork.freedesktop.org/series/85007/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9494_full -> Patchwork_19161_full
== Series Details ==
Series: gpu/drm/i915: convert comma to semicolon
URL : https://patchwork.freedesktop.org/series/85006/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9494_full -> Patchwork_19160_full
Summary
---
== Series Details ==
Series: series starting with [v7,1/5] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85015/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9495 -> Patchwork_19164
== Series Details ==
Series: series starting with [v7,1/5] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85015/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used,
Primarily used by selftests, but also by runtime debugging of engine
w/a, is a routine to create a temporarily bound buffer for readback.
Almagamate the duplicated routines into one.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Chris Wilson
Reviewed-by: Daniele Ceraolo Spurio
---
> -Original Message-
> From: Chris Wilson
> Sent: Wednesday, December 16, 2020 12:44 PM
> To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> Cc: stable@
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced
> vma check and vma insert
>
> Quoting Tang, CQ
Quoting Tang, CQ (2020-12-16 21:23:04)
>
>
> > -Original Message-
> > From: Chris Wilson
> > Sent: Wednesday, December 16, 2020 12:53 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Chris Wilson ; Tang, CQ
> > Subject: [PATCH i-g-t] i915/gem_softpin: Check the last 32b page is
== Series Details ==
Series: drm/i915/cml : Add TGP PCH support
URL : https://patchwork.freedesktop.org/series/85013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9494 -> Patchwork_19163
Summary
---
**SUCCESS**
> -Original Message-
> From: Chris Wilson
> Sent: Wednesday, December 16, 2020 12:53 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson ; Tang, CQ
> Subject: [PATCH i-g-t] i915/gem_softpin: Check the last 32b page is excluded
>
> In order to prevent issues with 32b stateless
In order to prevent issues with 32b stateless address, the last page
under 4G is excluded for non-48b objects.
Signed-off-by: Chris Wilson
Cc: CQ Tang
---
tests/i915/gem_softpin.c | 37 +
1 file changed, 37 insertions(+)
diff --git
== Series Details ==
Series: drm/i915: Encode fence specific waitqueue behaviour into the wait.flags
URL : https://patchwork.freedesktop.org/series/85012/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9494 -> Patchwork_19162
Quoting Tang, CQ (2020-12-16 17:27:40)
>
>
> > -Original Message-
> > From: Chris Wilson
> > Sent: Wednesday, December 16, 2020 12:43 AM
> > To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> > Cc: stable@
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced
> >
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/gt: Track all timelines created
using the HWSP
URL : https://patchwork.freedesktop.org/series/85007/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9494 -> Patchwork_19161
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/gt: Track all timelines created
using the HWSP
URL : https://patchwork.freedesktop.org/series/85007/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't
== Series Details ==
Series: gpu/drm/i915: convert comma to semicolon
URL : https://patchwork.freedesktop.org/series/85006/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9494 -> Patchwork_19160
Summary
---
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, December 16, 2020 5:01 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ;
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, December 16, 2020 11:01 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ;
Enabling it to check if it causes regressions in CI but the feature is
still not ready to be enabled by default.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
It programs Plane's calculated x, y, offset to Plane SF register.
It does the calculation of x and y offsets using
skl_calc_main_surface_offset().
v3: Update commit message
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by:
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
Now that we are not complete fetching each plane, there is another
loop needed as all the plane areas
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by:
Much more clear to read one function call than four lines doing this
conversion.
v7:
- function renamed
- calculating width and height before truncate
- inlined
Cc: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
== Series Details ==
Series: drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
URL : https://patchwork.freedesktop.org/series/85001/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9491_full -> Patchwork_19159_full
> -Original Message-
> From: Chris Wilson
> Sent: Wednesday, December 16, 2020 12:43 AM
> To: Tang, CQ ; intel-gfx@lists.freedesktop.org
> Cc: stable@
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix mismatch between misplaced
> vma check and vma insert
>
> Quoting Tang, CQ
We have TGP PCH support for Tigerlake and Rocketlake. Similarly
now TGP PCH can be used with Cometlake CPU.
Cc: Matt Roper
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
Use the wait_queue_entry.flags to denote the special fence behaviour
(flattening continuations along fence chains, and for propagating
errors) rather than trying to detect ordinary waiters by their
functions.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
---
We cannot assume we know how many PMU there are exactly, so pick -1ULL
to represent all invalid metrics. Similarly, we have to rely on explicit
testing for each PMU to prove their existence and correct functioning.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/perf_pmu.c | 56
From: Tvrtko Ursulin
Similarly to how top(1) handles SMP, we can default to showing engines of
a same class as a single bar graph entry.
To achieve this a little bit of hackery is employed. PMU sampling is left
as is and only at the presentation layer we create a fake set of engines,
one for
== Series Details ==
Series: series starting with [v7,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/85000/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9491_full -> Patchwork_19158_full
Quoting Tvrtko Ursulin (2020-12-16 16:01:30)
>
> On 16/12/2020 15:51, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-12-16 15:28:09)
> >> +static int
> >> +print_engines(struct engines *engines, double t, int lines, int w, int h)
> >> +{
> >> + static struct engines *classes;
> >> +
On 16/12/2020 15:51, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-12-16 15:28:09)
From: Tvrtko Ursulin
Similarly to how top(1) handles SMP, we can default to showing engines of
a same class as a single bar graph entry.
To achieve this a little bit of hackery is employed. PMU sampling
Quoting Tvrtko Ursulin (2020-12-16 15:54:20)
> From: Tvrtko Ursulin
>
> Analoguous to top(1) we can enable the user to exit from the tool by
> pressing 'q' on the console.
>
> v2:
> * Fix sleep period with closed stdin. (Chris)
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev8)
URL : https://patchwork.freedesktop.org/series/82098/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9491_full -> Patchwork_19157_full
Summary
---
From: Tvrtko Ursulin
Analoguous to top(1) we can enable the user to exit from the tool by
pressing 'q' on the console.
v2:
* Fix sleep period with closed stdin. (Chris)
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 6
tools/intel_gpu_top.c | 80
Quoting Chris Wilson (2020-12-16 15:51:59)
> Quoting Tvrtko Ursulin (2020-12-16 15:28:09)
> > From: Tvrtko Ursulin
> >
> > Similarly to how top(1) handles SMP, we can default to showing engines of
> > a same class as a single bar graph entry.
> >
> > To achieve this a little bit of hackery is
Quoting Tvrtko Ursulin (2020-12-16 15:28:09)
> From: Tvrtko Ursulin
>
> Similarly to how top(1) handles SMP, we can default to showing engines of
> a same class as a single bar graph entry.
>
> To achieve this a little bit of hackery is employed. PMU sampling is left
> as is and only at the
Quoting Tvrtko Ursulin (2020-12-16 15:28:08)
> From: Tvrtko Ursulin
>
> Analoguous to top(1) we can enable the user to exit from the tool by
> pressing 'q' on the console.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> man/intel_gpu_top.rst | 6
> tools/intel_gpu_top.c | 77
Chris Wilson writes:
> Reduce the pollution of intel_engine.h by moving gen8_emit_pipe_control
> and friends to gen8_engine_cs.h
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/display/intel_overlay.c | 1 +
>
From: Tvrtko Ursulin
Similarly to how top(1) handles SMP, we can default to showing engines of
a same class as a single bar graph entry.
To achieve this a little bit of hackery is employed. PMU sampling is left
as is and only at the presentation layer we create a fake set of engines,
one for
From: Tvrtko Ursulin
Analoguous to top(1) we can enable the user to exit from the tool by
pressing 'q' on the console.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 6
tools/intel_gpu_top.c | 77 +++
2 files changed, 70 insertions(+),
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of
Hi Jani,
url:
https://github.com/0day-ci/linux/commits/Jani-Nikula/drm-i915-refactor-intel-display/20201216-194754
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-m001-20201216 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix
In preparation for removing the has_initial_breadcrumb field, add a
helper function for the existing callers.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++--
When we are not using semaphores with a context/engine, we can simply
reuse the same seqno location across wraps, but we still require each
timeline to have its own address. For LRC submission, each context is
prefixed by a per-process HWSP, which provides us with a unique location
for each
Currently we know that the timeline status page is at most a page in
size, and so we can preserve the lower 12bits of the offset when
relocating the status page in the GGTT. If we want to use a larger
object, such as the context state, we may not necessarily use a position
within the first page
Relative timelines are relative to either the global or per-process
HWSP, and so we can replace the absolute addressing with store-index
variants for position invariance.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 98
A quick test to verify that the backend accepts each type of timeline
and can use them to track and control request emission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 105
1 file changed, 105 insertions(+)
diff --git
Explicitly differentiate between the absolute and relative timelines,
and the global HWSP and ppHWSP relative offsets. When using a timeline
that is relative to a known status page, we can replace the absolute
addressing in the commands with indexed variants.
Signed-off-by: Chris Wilson
We assume that the contents of the HWSP are lost across suspend, and so
upon resume we must restore critical values such as the timeline seqno.
Keep track of every timeline allocated that uses the HWSP as its storage
and so we can then reset all seqno values by walking that list.
Signed-off-by:
On Wed, 2020-12-16 at 14:10 +, Mun, Gwan-gyeong wrote:
> On Wed, 2020-12-16 at 05:17 -0800, Souza, Jose wrote:
> > On Wed, 2020-12-16 at 10:29 +, Mun, Gwan-gyeong wrote:
> > > On Tue, 2020-12-15 at 05:14 -0800, Souza, Jose wrote:
> > > > On Tue, 2020-12-15 at 13:02 +, Mun, Gwan-gyeong
Replace a comma between expression statements by a semicolon.
Signed-off-by: Zheng Yongjun
---
drivers/gpu/drm/i915/intel_region_lmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index
== Series Details ==
Series: drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
URL : https://patchwork.freedesktop.org/series/85001/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9491 -> Patchwork_19159
Summary
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84997/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9490_full -> Patchwork_19155_full
On Wed, 2020-12-16 at 05:17 -0800, Souza, Jose wrote:
> On Wed, 2020-12-16 at 10:29 +, Mun, Gwan-gyeong wrote:
> > On Tue, 2020-12-15 at 05:14 -0800, Souza, Jose wrote:
> > > On Tue, 2020-12-15 at 13:02 +, Mun, Gwan-gyeong wrote:
> > > > On Mon, 2020-12-14 at 09:49 -0800, José Roberto de
== Series Details ==
Series: drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
URL : https://patchwork.freedesktop.org/series/85001/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ad3765dc76e1 drm/i915/gt: Move gen8 CS emitters into gen8_engine_cs.h
-:117:
== Series Details ==
Series: series starting with [v7,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/85000/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9491 -> Patchwork_19158
Reduce the pollution of intel_engine.h by moving gen8_emit_pipe_control
and friends to gen8_engine_cs.h
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_overlay.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 1
On 2020-12-16 at 14:47:42 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's
== Series Details ==
Series: series starting with [v7,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/85000/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [v7,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/85000/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a40676934ae8 drm/i915/display: Support PSR Multiple Transcoders
== Series Details ==
Series: drm/i915: Fix mismatch between misplaced vma check and vma insert (rev2)
URL : https://patchwork.freedesktop.org/series/84975/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9490_full -> Patchwork_19154_full
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev8)
URL : https://patchwork.freedesktop.org/series/82098/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9491 -> Patchwork_19157
Summary
---
**SUCCESS**
On Wed, 2020-12-16 at 10:29 +, Mun, Gwan-gyeong wrote:
> On Tue, 2020-12-15 at 05:14 -0800, Souza, Jose wrote:
> > On Tue, 2020-12-15 at 13:02 +, Mun, Gwan-gyeong wrote:
> > > On Mon, 2020-12-14 at 09:49 -0800, José Roberto de Souza wrote:
> > > > Now using plane damage clips property to
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev8)
URL : https://patchwork.freedesktop.org/series/82098/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev8)
URL : https://patchwork.freedesktop.org/series/82098/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fd6d0019c12b drm/edid: Add additional HFVSDB fields for HDMI2.1
-:61: WARNING:FROM_SIGN_OFF_MISMATCH:
== Series Details ==
Series: drm/i915: refactor intel display
URL : https://patchwork.freedesktop.org/series/84998/
State : failure
== Summary ==
Applying: drm/i915/display: move needs_modeset to an inline in header
Applying: drm/i915/display: move to_intel_frontbuffer to header
Applying:
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt
On Wed, Dec 16, 2020 at 01:29:15PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> Daniel asked for this, but it's a bit messy and I'm not sure
> how best to clean it up yet.
>
> Signed-off-by: Dave Airlie
> [Jani: also moved fdi buf trans to intel_fdi.c.]
> Signed-off-by: Jani Nikula
> ---
On Wed, 16 Dec 2020, Ville Syrjälä wrote:
> On Wed, Dec 16, 2020 at 12:03:37PM +0200, Jani Nikula wrote:
>> On Fri, 11 Dec 2020, Dave Airlie wrote:
>> > From: Dave Airlie
>> >
>> > There may be more crtc code that can be pulled out, but this
>> > is a good start.
>> >
>> > RFC: maybe call the
On 2020-12-16 at 11:38:24 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84997/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9490 -> Patchwork_19155
On Wed, Dec 16, 2020 at 01:29:18PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> This just cleans these up a bit.
>
> Signed-off-by: Dave Airlie
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_gen9_plane.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_sprite.c
On Wed, Dec 16, 2020 at 01:29:17PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> Daniel suggested this should move here.
Slightly better than where it is now I guess. I'd kinda like to put it
next to its callers but not sure that wouldn't end up in a mess.
Reviewed-by: Ville Syrjälä
>
>
On Wed, Dec 16, 2020 at 01:29:16PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> Rework the plane init calls to do the gen test one level higher.
>
> Signed-off-by: Dave Airlie
> [Jani: fixed up sparse warnings.]
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/Makefile
On Wed, Dec 16, 2020 at 01:29:13PM +0200, Jani Nikula wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index dfa3966e5fa1..37a9f304cb55 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84997/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84997/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
144736cb4785 drm/i915/display: Support PSR Multiple Transcoders
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