== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85105/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9506 -> Patchwork_19184
===
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85105/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5dd14c1bb771 drm/i915/gt: Split logical ring context
Primarily used by selftests, but also by runtime debugging of engine
w/a, is a routine to create a temporarily bound buffer for readback.
Almagamate the duplicated routines into one.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Chris Wilson
Reviewed-by: Daniele Ceraolo Spurio
---
driver
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85096/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9506 -> Patchwork_19183
===
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85096/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
15e1c6d96de6 drm/i915/gt: Split logical ring context
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85095/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9506 -> Patchwork_19182
===
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Split logical ring contexts
from execlist submission
URL : https://patchwork.freedesktop.org/series/85095/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0fd013ab16e2 drm/i915/gt: Split logical ring context
== Series Details ==
Series: series starting with [v9,1/5] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85092/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9506 -> Patchwork_19181
===
== Series Details ==
Series: series starting with [v9,1/5] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85092/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, ea
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev13)
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9506 -> Patchwork_19180
Summary
--
Primarily used by selftests, but also by runtime debugging of engine
w/a, is a routine to create a temporarily bound buffer for readback.
Almagamate the duplicated routines into one.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Chris Wilson
Reviewed-by: Daniele Ceraolo Spurio
---
driver
Primarily used by selftests, but also by runtime debugging of engine
w/a, is a routine to create a temporarily bound buffer for readback.
Almagamate the duplicated routines into one.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Chris Wilson
Reviewed-by: Daniele Ceraolo Spurio
---
driver
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev13)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drive
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev13)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
24242191f906 drm/i915/pxp: Introduce Intel PXP component
-:118: WARNING:FILE_PATH_CHANGES
== Series Details ==
Series: drm/i915/dg1: Fix power gate sequence.
URL : https://patchwork.freedesktop.org/series/85082/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9503_full -> Patchwork_19179_full
Summary
---
**
Quoting Rodrigo Vivi (2020-12-18 15:24:12)
> sub-pipe PG is not present on DG1. Setting these bits can disable
> other power gates and cause GPU hangs on video playbacks.
Hmm, all I see is "not valid for pre-gen12".
> Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.")
> Cc: Dale
Enabling it to check if it causes regressions in CI but the feature is
still not ready to be enabled by default.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/d
It programs Plane's calculated x, y, offset to Plane SF register.
It does the calculation of x and y offsets using
skl_calc_main_surface_offset().
v3: Update commit message
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by: Gwan-
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by:
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
Now that we are not complete fetching each plane, there is another
loop needed as all the plane areas t
Much more clear to read one function call than four lines doing this
conversion.
v7:
- function renamed
- calculating width and height before truncate
- inlined
Cc: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
include/drm/drm_r
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 1
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c |
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gp
PXP (Protected Xe Path) is an i915 component, available on
GEN12+ that helps to establish the hardware protected session
and manage the status of the alive software session, as well
as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.i
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after t
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/g
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session n
On 12/17/20 9:33 PM, Stephen Rothwell wrote:
> Hi all,
>
> News: there will be no linux-next releases between Dec 24 and Jan
> 3 inclusive.
>
> Please do not add any v5.12 destined code to your linux-next included
> branches until after v5.11-rc1 has been released.
>
> Changes since 20201217:
>
On Fri, 2020-12-18 at 08:52 -0800, José Roberto de Souza wrote:
> On Fri, 2020-12-18 at 16:31 +, Mun, Gwan-gyeong wrote:
> > On Thu, 2020-12-17 at 13:13 -0800, José Roberto de Souza wrote:
> > > Now using plane damage clips property to calcualte the damaged area.
> > > Selective fetch only supp
On Fri, 2020-12-18 at 16:31 +, Mun, Gwan-gyeong wrote:
> On Thu, 2020-12-17 at 13:13 -0800, José Roberto de Souza wrote:
> > Now using plane damage clips property to calcualte the damaged area.
> > Selective fetch only supports one region to be fetched so software
> > needs to calculate a bound
On 18/12/2020 16:07, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-12-18 15:52:05)
On 18/12/2020 12:24, Chris Wilson wrote:
Since we allow removing the timeline map at runtime, there is a risk
that rq->hwsp points into a stale page. To control that risk, we hold
the RCU read lock while re
On Thu, 2020-12-17 at 13:13 -0800, José Roberto de Souza wrote:
> Now using plane damage clips property to calcualte the damaged area.
> Selective fetch only supports one region to be fetched so software
> needs to calculate a bounding box around all damage clips.
>
> Now that we are not complete
== Series Details ==
Series: drm/i915: Check for rq->hwsp validity after acquiring RCU lock (rev2)
URL : https://patchwork.freedesktop.org/series/85071/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9503_full -> Patchwork_19178_full
== Series Details ==
Series: drm/i915/dg1: Fix power gate sequence.
URL : https://patchwork.freedesktop.org/series/85082/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9503 -> Patchwork_19179
Summary
---
**SUCCESS**
On Fri, 18 Dec 2020, Lucas De Marchi wrote:
> On Fri, Dec 18, 2020 at 01:13:49PM +0200, Jani Nikula wrote:
>>On Fri, 18 Dec 2020, Jani Nikula wrote:
>>> On Thu, 17 Dec 2020, Lucas De Marchi wrote:
Both patches applied. Thanks!
Jani, maybe now you can rebase your patch to get rid o
Quoting Tvrtko Ursulin (2020-12-18 15:52:05)
>
> On 18/12/2020 12:24, Chris Wilson wrote:
> > Since we allow removing the timeline map at runtime, there is a risk
> > that rq->hwsp points into a stale page. To control that risk, we hold
> > the RCU read lock while reading *rq->hwsp, but we missed
On 18/12/2020 12:24, Chris Wilson wrote:
Since we allow removing the timeline map at runtime, there is a risk
that rq->hwsp points into a stale page. To control that risk, we hold
the RCU read lock while reading *rq->hwsp, but we missed a couple of
important barriers. First, the unpinning / rem
On Fri, Dec 18, 2020 at 05:04:09PM +0200, Jani Nikula wrote:
>
> Hi Dave & Daniel -
>
> drm-intel-next-fixes-2020-12-18:
> drm/i915 fixes for the merge window
Pulled, thanks a lot.
-Daniel
>
>
> BR,
> Jani.
>
> The following changes since commit efd3043790c6e92f0bbe1fe385db9b544131c59c:
>
>
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev9)
URL : https://patchwork.freedesktop.org/series/82098/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9503_full -> Patchwork_19177_full
Summary
---
**
sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.
Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.")
Cc: Dale B Stimson
Cc: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_rc6
On Fri, Dec 18, 2020 at 04:04:16PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> Daniel asked for this, but it's a bit messy and I'm not sure
> how best to clean it up yet.
>
> Signed-off-by: Dave Airlie
> [Jani: also moved fdi buf trans to intel_fdi.c.]
> Signed-off-by: Jani Nikula
> ---
On Fri, Dec 18, 2020 at 04:04:17PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> Rework the plane init calls to do the gen test one level higher.
>
> Rework some of the plane helpers so they can live in new file,
> there is still some scope to clean up the plane/fb interactions
> later.
>
>
Hi Dave & Daniel -
drm-intel-next-fixes-2020-12-18:
drm/i915 fixes for the merge window
BR,
Jani.
The following changes since commit efd3043790c6e92f0bbe1fe385db9b544131c59c:
Merge tag 'amd-drm-fixes-5.11-2020-12-16' of
git://people.freedesktop.org/~agd5f/linux into drm-next (2020-12-16 2
On Fri, Dec 18, 2020 at 04:04:15PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> This just refactors out the fdi code to a separate file.
>
> Signed-off-by: Dave Airlie
> [Jani: cleaned up intel_fdi.h a bit.]
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
--
Ville Syrjälä
Inte
On Fri, Dec 18, 2020 at 04:04:13PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> There may be more crtc code that can be pulled out, but this
> is a good start.
>
> v2: move plane before this.
>
> Signed-off-by: Dave Airlie
> [Jani: cleaned up intel_crtc.h a bit.]
> Signed-off-by: Jani Nik
On Fri, Dec 18, 2020 at 04:04:12PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> Ville suggested this as a good idea, let's move this before moving
> the crtc code.
>
> Signed-off-by: Dave Airlie
> ---
> drivers/gpu/drm/i915/Makefile| 3 +-
> drivers/gpu/drm/i915/display/
Allow the caller to specify a dword, or an arbitrary payload, to be
written by the busy spinner, just prior to starting its infinite loop.
This is similar to the dependency method, that makes a target busy
without writing anything.
Signed-off-by: Chris Wilson
---
lib/igt_dummyload.c | 71
== Series Details ==
Series: drm/i915: Check for rq->hwsp validity after acquiring RCU lock (rev2)
URL : https://patchwork.freedesktop.org/series/85071/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9503 -> Patchwork_19178
== Series Details ==
Series: drm/i915: Check for rq->hwsp validity after acquiring RCU lock (rev2)
URL : https://patchwork.freedesktop.org/series/85071/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a93ba5a18bf8 drm/i915: Check for rq->hwsp validity after acquiring RCU lock
-:2
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev9)
URL : https://patchwork.freedesktop.org/series/82098/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9503 -> Patchwork_19177
Summary
---
**SUCCESS**
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev9)
URL : https://patchwork.freedesktop.org/series/82098/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu/drm/amd/amdg
== Series Details ==
Series: Add support for DP-HDMI2.1 PCON (rev9)
URL : https://patchwork.freedesktop.org/series/82098/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
26eb0c2f2ee1 drm/edid: Add additional HFVSDB fields for HDMI2.1
-:61: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Si
== Series Details ==
Series: drm/i915: Check for rq->hwsp validity after acquiring RCU lock
URL : https://patchwork.freedesktop.org/series/85071/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9503 -> Patchwork_19175
Summary
== Series Details ==
Series: Infoframe changes for DP-HDMI2.1 PCON
URL : https://patchwork.freedesktop.org/series/85073/
State : failure
== Summary ==
Applying: drm/i915: Export intel_hdmi_compute_avi_infoframe()
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/displ
On Fri, Dec 18, 2020 at 01:13:49PM +0200, Jani Nikula wrote:
On Fri, 18 Dec 2020, Jani Nikula wrote:
On Thu, 17 Dec 2020, Lucas De Marchi wrote:
Both patches applied. Thanks!
Jani, maybe now you can rebase your patch to get rid of the extern ?
Yes, thanks for the irq so I can stop polling.
== Series Details ==
Series: drm/i915: Check for rq->hwsp validity after acquiring RCU lock
URL : https://patchwork.freedesktop.org/series/85071/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eda31dae2517 drm/i915: Check for rq->hwsp validity after acquiring RCU lock
-:28: WARN
Since we allow removing the timeline map at runtime, there is a risk
that rq->hwsp points into a stale page. To control that risk, we hold
the RCU read lock while reading *rq->hwsp, but we missed a couple of
important barriers. First, the unpinning / removal of the timeline map
must be after all RC
Quoting Chris Wilson (2020-12-18 09:19:44)
> Since we allow removing the timeline map at runtime, there is a risk
> that rq->hwsp points into a stale page. To control that risk, we hold
> the RCU read lock while reading *rq->hwsp, but we missed a couple of
> important barriers. First, the unpinning
== Series Details ==
Series: drm/i915: Try to guess PCH type even without ISA bridge (rev2)
URL : https://patchwork.freedesktop.org/series/84886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9502_full -> Patchwork_19174_full
===
On Fri, 18 Dec 2020, Jani Nikula wrote:
> On Thu, 17 Dec 2020, Lucas De Marchi wrote:
>> Both patches applied. Thanks!
>>
>> Jani, maybe now you can rebase your patch to get rid of the extern ?
>
> Yes, thanks for the irq so I can stop polling. ;)
Huh, why were these applied to drm-intel-gt-next
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, December 18, 2020 4:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Shar
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, December 18, 2020 4:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Sharm
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Friday, December 18, 2020 4:07 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Shar
If PCON has capability to convert RGB->YCbCr colorspace and also
to 444->420 downsampling then for any YUV420 only mode, we can
let the PCON do all the conversion. If the PCON supports
RGB->YCbCr conversion for all BT2020, BT709, BT601, choose
the one that is selected by userspace via connector col
The DP-HDMI2.1 PCON spec provides way for a source to set PPS
parameters: slice height, slice width and bits_per_pixel, based on
the HDMI2.1 sink capabilities. The DSC encoder of the PCON will
respect these parameters, while preparing the 128 byte PPS.
This patch adds helper functions to calculate
When a source supporting DSC1.1 is connected to DSC1.2 HDMI2.1 sink
via DP HDMI2.1 PCON, the PCON can be configured to decode the
DSC1.1 compressed stream and encode to DSC1.2. It then sends the
DSC1.2 compressed stream to the HDMI2.1 sink.
This patch configures the PCON for DSC1.1 to DSC1.2 encod
This patch adds support to read and store the DSC capabilities of the
HDMI2.1 PCon encoder. It also adds a new field to store these caps,
The caps are read during dfp update and can later be used to get the
PPS parameters for PCON-HDMI2.1 sink pair. Which inturn will be used
to take a call to overr
From: Swati Sharma
In this patch enables support for detecting link failures between
PCON and HDMI sink in i915 driver. HDMI link loss indication to
upstream DP source is indicated via IRQ_HPD. This is followed by
reading of HDMI link configuration status (HDMI_TX_LINK_ACTIVE_STATUS).
If the PCON
This patch calls functions to check FRL training requirements
for an HDMI2.1 sink, when connected through PCON.
The call is made before the DP link training. In case FRL is not
required or failure during FRL training, the TMDS mode is selected
for the pcon.
v2: moved check_frl_training() just afte
This patch adds functions to start FRL training for an HDMI2.1 sink,
connected via a PCON as a DP branch device.
This patch also adds a new structure for storing frl training related
data, when FRL training is completed.
v2: As suggested by Uma Shankar:
-renamed couple of variables for better clar
DP Specification for DP2.0 to HDMI2.1 Pcon specifies support for conversion
of colorspace from RGB to YCbCr.
https://groups.vesa.org/wg/DP/document/previewpdf/15651
This patch adds the relavant registers and helper functions to
get the capability and set the color conversion bits for rgb->ycbcr
co
HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON.
This patch captures this in dfp cap structure in intel_dp and uses
this to prune connector modes that cannot be supported by the PCON
and FRL bandwidth.
v2: Addressed review comments from Uma Shankar:
-tweaked the comparison of targ
This patch adds registers for getting DSC encoder capability for
a HDMI2.1 PCon. It also addes helper functions to configure
DSC between the PCON and HDMI2.1 sink.
v2: Corrected offset for DSC encoder bpc and minor changes.
Also added helper functions for getting pcon dsc encoder capabilities
as s
From: Swati Sharma
There are specific DPCDs defined for detecting link failures between
the PCON and HDMI sink and check the link status. In case of link
failure, PCON will communicate the same using an IRQ_HPD to source.
HDMI sink would have indicated the same to PCON using SCDC interrupt
mechan
This patch adds support for configuring a PCON device,
connected as a DP branched device to enable FRL Link training
with a HDMI2.1 + sink.
v2: Fixed typos and addressed other review comments from Uma Shankar.
-changed the commit message for better clarity (Uma Shankar)
-removed unnecessary argume
This patch parses HFVSDB fields for DSC1.2 capabilities of an
HDMI2.1 sink. These fields are required by a source to understand the
DSC capability of the sink, to set appropriate PPS parameters,
before transmitting compressed data stream.
v2: Addressed following issues as suggested by Uma Shankar:
From: Swati Sharma
This patch parses MAX_FRL field to get the MAX rate in Gbps that
the HDMI 2.1 panel can support in FRL mode. Source need this
field to determine the optimal rate between the source and sink
during FRL training.
v2: Fixed minor bugs, and removed extra wrapper function (Uma Shan
From: Swati Sharma
The HDMI2.1 extends HFVSDB (HDMI Forum Vendor Specific
Data block) to have fields related to newly defined methods of FRL
(Fixed Rate Link) levels, number of lanes supported, DSC Color bit
depth, VRR min/max, FVA (Fast Vactive), ALLM etc.
This patch adds the new HFVSDB fields
This patch series attempts to add support for a DP-HDMI2.1 Protocol
Convertor. The VESA spec for the HDMI2.1 PCON are proposed in Errata
E5 to DisplayPort_v2.0:
https://vesa.org/join-vesamemberships/member-downloads/?action=stamp&fileid=42299
The details are mentioned in:
VESA DP-to-HDMI PCON Speci
In this patch readout for AVI infoframes enclosed in GMP
DIP is implemented.
Signed-off-by: Swati Sharma
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 74 -
1 file changed, 72 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/
DP does not support sending AVI info frame to panel. So we need to
send AVI info frame to HDMI through some other DIP.
When DP-to-HDMI protocol converter is present GMP DIP will be used
to send AVI infoframe instead of static HDR infoframes.
While VESA spec indicates support within PCON to built
Instead of re-writing the avi_infoframe_compute func in intel_dp;
exporting hdmi_compute_avi_infoframe func so that it can be called
directly while encapsulating AVI infoframes in GMP dip.
This is required when HDMI 2.1 PCON (dp to hdmi) is used and we need
to send AVI infoframes to PCON in source
These patches should be applied on top of series
https://patchwork.freedesktop.org/series/82098/
(Add support for DP-HDMI2.1 PCON)
This is good to have feature, even if we don't send any AVI info frame,
PCON is able to create and send it based on DP VSC packets. However,
it gives better control wi
== Series Details ==
Series: drm/i915: Try to guess PCH type even without ISA bridge (rev2)
URL : https://patchwork.freedesktop.org/series/84886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9502 -> Patchwork_19174
Summary
On 18/12/2020 04:08, Umesh Nerlige Ramappa wrote:
On Wed, Dec 16, 2020 at 10:30:24AM +0200, Lionel Landwerlin wrote:
On 15/12/2020 23:49, Umesh Nerlige Ramappa wrote:
Variations in OA formats in the different gens has led to creation of
several sparse arrays to store the formats.
Move oa forma
Quoting Tvrtko Ursulin (2020-12-18 08:49:39)
> From: Tvrtko Ursulin
>
> Ask for CLOCK_MONOTONIC which is more stable than the default perf clock.
>
> (Ability to select a clock has been available since kernel version 4.1.)
>
> The change should not have any significant impact on the IGT as whol
Since we allow removing the timeline map at runtime, there is a risk
that rq->hwsp points into a stale page. To control that risk, we hold
the RCU read lock while reading *rq->hwsp, but we missed a couple of
important barriers. First, the unpinning / removal of the timeline map
must be after all RC
On 18/12/2020 02:32, Umesh Nerlige Ramappa wrote:
On Wed, Dec 16, 2020 at 09:25:35AM +, Tvrtko Ursulin wrote:
On 15/12/2020 21:49, Umesh Nerlige Ramappa wrote:
Variations in OA formats in the different gens has led to creation of
several sparse arrays to store the formats.
Move oa format
From: Zhenyu Wang
Some vmm like hyperv and crosvm don't supply any ISA bridge to their guest,
when igd passthrough is equipped on these vmm, guest i915 display may
couldn't work as guest i915 detects PCH_NONE pch type.
When i915 runs as guest, this patch guess pch type through gpu type even
with
From: Tvrtko Ursulin
Ask for CLOCK_MONOTONIC which is more stable than the default perf clock.
(Ability to select a clock has been available since kernel version 4.1.)
The change should not have any significant impact on the IGT as whole
apart from maybe improving the occasional jitter in tests
On Thu, 17 Dec 2020, Lucas De Marchi wrote:
> Both patches applied. Thanks!
>
> Jani, maybe now you can rebase your patch to get rid of the extern ?
Yes, thanks for the irq so I can stop polling. ;)
BR,
Jani.
>
>
> Lucas De Marchi
>
> On Wed, Dec 02, 2020 at 11:23:58PM -0800, Aditya Swarup wro
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