== Series Details ==
Series: series starting with [1/2] drm/i915: Index min_{cdclk, voltage_level}[]
with pipe
URL : https://patchwork.freedesktop.org/series/86673/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9728_full -> Patchwork_19582_full
===
On Wed, Feb 03, 2021 at 03:37:05PM -0800, Dongli Zhang wrote:
> This patch converts several swiotlb related variables to arrays, in
> order to maintain stat/status for different swiotlb buffers. Here are
> variables involved:
>
> - io_tlb_start and io_tlb_end
> - io_tlb_nslabs and io_tlb_used
> -
== Series Details ==
Series: HDMI2.1 PCON Misc Fixes
URL : https://patchwork.freedesktop.org/series/86677/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/
Remove code for resetting frl related members from intel_disable_dp, as
this is not applicable for older platforms.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gp
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration for FRL training.
This patch:
-Defines FRL training type and link bring up sequence mode as enum.
-Fixes the dr
DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
Do not read the registers if DPCD rev < 1.4.
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 d
Patch1: fixes gitlab issue:
https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Patch2: Tweaks the drm_helpers for PCON configuration
Patch3: Removes unwanted code not applicable for older platforms.
Ankit Nautiyal (3):
i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
== Series Details ==
Series: drm/vblank: Avoid storing a timestamp for the same frame twice
URL : https://patchwork.freedesktop.org/series/86672/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9727_full -> Patchwork_19581_full
===
Hi all,
Today's linux-next merge of the drivers-x86 tree got a conflict in:
drivers/gpu/drm/gma500/Kconfig
drivers/gpu/drm/gma500/mdfld_device.c
drivers/gpu/drm/gma500/mdfld_dsi_output.c
drivers/gpu/drm/gma500/mdfld_output.c
drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c
between commits:
== Series Details ==
Series: RFC: dma-buf: Require VM_SPECIAL vma for mmap
URL : https://patchwork.freedesktop.org/series/86667/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9727_full -> Patchwork_19579_full
Summary
--
== Series Details ==
Series: series starting with [1/2] drm/i915: Index min_{cdclk, voltage_level}[]
with pipe
URL : https://patchwork.freedesktop.org/series/86673/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9728 -> Patchwork_19582
=
== Series Details ==
Series: drm/vblank: Avoid storing a timestamp for the same frame twice
URL : https://patchwork.freedesktop.org/series/86672/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9727 -> Patchwork_19581
Summary
On 2/3/2021 5:25 AM, Joonas Lahtinen wrote:
> Quoting Brian Welty (2021-01-26 23:46:24)
>> Single control below is added to DRM cgroup controller in order to track
>> user execution time for GPU devices. It is up to device drivers to
>> charge execution time to the cgroup via drm_cgroup_try_char
From: Ville Syrjälä
Replace the hand rolled intel_hdmi_port_clock() stuff
with the real thing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 27 ---
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i
From: Ville Syrjälä
min_cdclk[] and min_voltage_level[] are supposed to be indexed
with the pipe. Fix up a few cases where we index via the crtc
index (via the atomic iterators) instead.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 8
1 file changed, 4
From: Ville Syrjälä
drm_vblank_restore() exists because certain power saving states
can clobber the hardware frame counter. The way it does this is
by guesstimating how many frames were missed purely based on
the difference between the last stored timestamp vs. a newly
sampled timestamp.
If we s
== Series Details ==
Series: drm/i915/gt: Ratelimit heartbeat completion probing (rev2)
URL : https://patchwork.freedesktop.org/series/86665/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9727 -> Patchwork_19580
Summary
---
== Series Details ==
Series: drm/i915/gt: Ratelimit heartbeat completion probing (rev2)
URL : https://patchwork.freedesktop.org/series/86665/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8272367db0e5 drm/i915/gt: Ratelimit heartbeat completion probing
-:86: ERROR:CODE_INDENT:
== Series Details ==
Series: RFC: dma-buf: Require VM_SPECIAL vma for mmap
URL : https://patchwork.freedesktop.org/series/86667/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9727 -> Patchwork_19579
Summary
---
**SUC
== Series Details ==
Series: RFC: dma-buf: Require VM_SPECIAL vma for mmap
URL : https://patchwork.freedesktop.org/series/86667/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
881e92038f1d RFC: dma-buf: Require VM_SPECIAL vma for mmap
-:27: WARNING:COMMIT_LOG_LONG_LINE: Possible
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: Distinction of memory regions
URL : https://patchwork.freedesktop.org/series/86658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725_full -> Patchwork_19577_full
== Series Details ==
Series: series starting with [CI,1/9] drm/i915: Replace engine->schedule() with
a known request operation
URL : https://patchwork.freedesktop.org/series/86656/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9725_full -> Patchwork_19576_full
===
== Series Details ==
Series: drm/i915/gt: Ratelimit heartbeat completion probing
URL : https://patchwork.freedesktop.org/series/86665/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9726 -> Patchwork_19578
Summary
---
The heartbeat runs through a few phases that we expect to complete
within a certain number of heartbeat intervals. First we must submit the
heartbeat to the queue, and if the queue is occupied it may take a
couple of intervals before the heartbeat preempts the workload and is
submitted to HW. Once
== Series Details ==
Series: drm/i915/gt: Ratelimit heartbeat completion probing
URL : https://patchwork.freedesktop.org/series/86665/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
da83191895fd drm/i915/gt: Ratelimit heartbeat completion probing
-:20: WARNING:TYPO_SPELLING: 'ac
== Series Details ==
Series: drm/i915/display: fix spelling mistake "Couldnt" -> "Couldn't"
URL : https://patchwork.freedesktop.org/series/86637/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725_full -> Patchwork_19573_full
===
On Wed, 2021-02-03 at 15:58 -0500, Rodrigo Vivi wrote:
> On Mon, Jan 25, 2021 at 07:10:30PM -0500, Lyude Paul wrote:
> > Since we're about to implement eDP backlight support in nouveau using the
> > standard protocol from VESA, we might as well just take the code that's
> > already written for this
tldr; DMA buffers aren't normal memory, expecting that you can use
them like that (like calling get_user_pages works, or that they're
accounting like any other normal memory) cannot be guaranteed.
Since some userspace only runs on integrated devices, where all
buffers are actually all resident sys
On Mon, Feb 01, 2021 at 02:01:42PM +0200, Imre Deak wrote:
> Reporting a port as connected if nothing is attached to them leads to
> any i2c transactions on this port trying to use an uninitialized i2c
> adapter, fix this.
>
> Let's account for this case even if branch devices have no good reason
The heartbeat runs through a few phases that we expect to complete
within a certain number of heartbeat intervals. First we must submit the
heartbeat to the queue, and if the queue is occupied it may take a
couple of intervals before the heartbeat preempts the workload and is
submitted to HW. Once
On Mon, Jan 25, 2021 at 07:10:30PM -0500, Lyude Paul wrote:
> Since we're about to implement eDP backlight support in nouveau using the
> standard protocol from VESA, we might as well just take the code that's
> already written for this and move it into a set of shared DRM helpers.
>
> Note that t
== Series Details ==
Series: drm/i915: Reject 446-480MHz HDMI clock on GLK
URL : https://patchwork.freedesktop.org/series/86631/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725_full -> Patchwork_19572_full
Summary
--
== Series Details ==
Series: drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGA
URL : https://patchwork.freedesktop.org/series/86627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725_full -> Patchwork_19571_full
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: Distinction of memory regions
URL : https://patchwork.freedesktop.org/series/86658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19577
On Wed, 3 Feb 2021 at 18:01, Tang, CQ wrote:
>
>
>
> > -Original Message-
> > From: Matthew Auld
> > Sent: Wednesday, February 3, 2021 9:03 AM
> > To: Tang, CQ
> > Cc: Auld, Matthew ; intel-
> > g...@lists.freedesktop.org; Chris Wilson
> > Subject: Re: [Intel-gfx] [PATCH v3 3/3] drm/i91
== Series Details ==
Series: series starting with [CI,1/9] drm/i915: Replace engine->schedule() with
a known request operation
URL : https://patchwork.freedesktop.org/series/86656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19576
=
> -Original Message-
> From: Matthew Auld
> Sent: Wednesday, February 3, 2021 9:03 AM
> To: Tang, CQ
> Cc: Auld, Matthew ; intel-
> g...@lists.freedesktop.org; Chris Wilson
> Subject: Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1: add PTE_LM
> plumbing for GGTT
>
> On Wed, 3 Feb 20
== Series Details ==
Series: series starting with [CI,1/9] drm/i915: Replace engine->schedule() with
a known request operation
URL : https://patchwork.freedesktop.org/series/86656/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each com
== Series Details ==
Series: series starting with [CI,1/9] drm/i915: Replace engine->schedule() with
a known request operation
URL : https://patchwork.freedesktop.org/series/86656/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
836be19c8de4 drm/i915: Replace engine->schedule()
== Series Details ==
Series: drm/i915: Prevent waiting inside ring construction for critical
sections (rev3)
URL : https://patchwork.freedesktop.org/series/86644/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19575
===
== Series Details ==
Series: drm/i915: Prevent waiting inside ring construction for critical
sections (rev3)
URL : https://patchwork.freedesktop.org/series/86644/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c2a787bb37c7 drm/i915: Prevent waiting inside ring construction for
== Series Details ==
Series: series starting with [CI,01/12] drm/i915/gt: Move engine setup out of
set_default_submission
URL : https://patchwork.freedesktop.org/series/86639/
State : failure
== Summary ==
Applying: drm/i915/gt: Move engine setup out of set_default_submission
Using index info
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
BSpec: 45040
v2: just use gen8_pte_encode for dg1
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep D
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
BSpec: 45015
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 24
From: Zbigniew Kempczyński
In preparation for Xe HP multi-tile architecture with multiple memory
regions, we need to be able differentiate multiple instances of device
local-memory.
Note that the region name is just to give it a human friendly
identifier, instead of using class/instance which al
On Wed, 3 Feb 2021 at 16:51, Tang, CQ wrote:
>
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Matthew Auld
> > Sent: Wednesday, February 3, 2021 7:24 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Chris Wilson
> > Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1:
Quoting Tvrtko Ursulin (2021-02-03 13:12:05)
>
> On 03/02/2021 11:00, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-02-03 10:31:04)
> >>
> >> On 01/02/2021 12:07, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2021-02-01 11:57:56)
> From: Tvrtko Ursulin
>
> Slight improve
'--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prevent-waiting-inside-ring-construction-for-critical-sections/20210203-204914
base: git://anongit.freedesktop.org/drm-intel for-linux-next
conf
The core of the scheduling algorithm is that we compute the topological
order of the fence DAG. Knowing that we have a DAG, we should be able to
use a DFS to compute the topological sort in linear time. However,
during the conversion of the recursive algorithm into an iterative one,
the memoization
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilso
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the enti
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend. It already
operates on the common structs, so just a matter of moving and renaming.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execl
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend.
While this operates on the common structs, we do have a bit of backend
knowledge, which is harmless for !lrc but still unsightly.
Signed-off-by: Chris Wilson
Reviewed-by: T
Make the ability to suspend and resume a request and its dependents
generic.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 167 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +-
drivers/gpu/drm/i915/i915_sche
Lift the ability to defer a request until later from execlists into the
common layer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 57 +++--
drivers/gpu/drm/i915/i915_scheduler.c | 63 +--
drivers
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 215 ++
1 file changed, 215 insertions(+)
diff --git a/drivers/
> -Original Message-
> From: Intel-gfx On Behalf Of
> Matthew Auld
> Sent: Wednesday, February 3, 2021 7:24 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson
> Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1: add PTE_LM plumbing
> for GGTT
>
> For the PTEs we get an LM
== Series Details ==
Series: drm/i915/display: fix spelling mistake "Couldnt" -> "Couldn't"
URL : https://patchwork.freedesktop.org/series/86637/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19573
Summary
== Series Details ==
Series: drm/i915: Reject 446-480MHz HDMI clock on GLK
URL : https://patchwork.freedesktop.org/series/86631/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19572
Summary
---
**SUC
On Wed, Feb 03, 2021 at 01:40:05PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 28, 2021 at 09:13:49PM +0200, Imre Deak wrote:
> > On Wed, Jan 27, 2021 at 08:19:09PM +0200, Imre Deak wrote:
> > > At least on some TGL platforms PUNIT wants to access some display HW
> > > registers, but it doesn't handl
== Series Details ==
Series: drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGA
URL : https://patchwork.freedesktop.org/series/86627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19571
Summary
-
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
v2: just use gen8_pte_encode for dg1
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
Re
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 24 +
From: Zbigniew Kempczyński
In preparation for Xe HP multi-tile architecture with multiple memory
regions, we need to be able differentiate multiple instances of device
local-memory.
Note that the region name is just to give it a human friendly
identifier, instead of using class/instance which al
>From some contexts, we may not be allowed to wait during request
construction. For example, in the powermanagement handler that should
never block (as the engine was idle) and the driver would be crippled if
we did. Similarly, the user may request that the execbuf does not block,
and so would pref
>From some contexts, we may not be allowed to wait during request
construction. For example, in the powermanagement handler that should
never block (as the engine was idle) and the driver would be crippled if
we did. Similarly, the user may request that the execbuf does not block,
and so would pref
Quoting Matthew Auld (2021-02-03 14:13:11)
> From: Zbigniew Kempczyński
>
> In preparation for Xe HP multi-tile architecture with multiple memory
> regions, we need to be able differentiate multiple instances of device
> local-memory.
>
> Note that the region name is just to give it a human frie
Quoting Matthew Auld (2021-02-03 14:13:13)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
> b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 4a1d9b5cc75b..55873663d37f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -85,7 +85,8 @@ typedef u64 ge
Quoting Matthew Auld (2021-02-03 14:13:12)
> For the PTEs we get an LM bit, to signal whether the page resides in
> SMEM or LMEM.
>
> v2: just use gen8_pte_encode for dg1
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Niranjana Vi
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
v2: just use gen8_pte_encode for dg1
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
--
From: Zbigniew Kempczyński
In preparation for Xe HP multi-tile architecture with multiple memory
regions, we need to be able differentiate multiple instances of device
local-memory.
Note that the region name is just to give it a human friendly
identifier, instead of using class/instance which al
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 23 ++-
drivers/gpu/drm
Quoting Brian Welty (2021-01-26 23:46:24)
> Single control below is added to DRM cgroup controller in order to track
> user execution time for GPU devices. It is up to device drivers to
> charge execution time to the cgroup via drm_cgroup_try_charge().
>
> sched.runtime
> Read-only value,
Quoting Matthew Auld (2021-02-03 14:11:16)
> From: Zbigniew Kempczyński
>
> In preparation for Xe HP multi-tile architecture with multiple memory
> regions, we need to be able differentiate multiple instances of device
> local-memory.
Would be good to comment here on where this name is used, and
On 03/02/2021 11:00, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-03 10:31:04)
On 01/02/2021 12:07, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-01 11:57:56)
From: Tvrtko Ursulin
Slight improvement with regards to wrapping header components to fit
console width. If a single
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/selftests: Set cache status for
huge_gem_object
URL : https://patchwork.freedesktop.org/series/86626/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721_full -> Patchwork_19570_full
==
>From some contexts, we may not be allowed to wait during request
construction. For example, in the powermanagement handler that should
never block (as the engine was idle) and the driver would be crippled if
we did. Similarly, the user may request that the execbuf does not block,
and so would pref
Quoting Matthew Auld (2021-02-03 12:11:18)
> The vm insert_page is useful to insert a vma-less page into the GGTT,
> which so far is always to map something through the mappable aperture,
> usually when the entire VMA doesn't fit, or if we specifically don't
> want to hog it, since it's generally q
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 19 ---
drivers/gpu/drm/i91
From: Zbigniew Kempczyński
In preparation for Xe HP multi-tile architecture with multiple memory
regions, we need to be able differentiate multiple instances of device
local-memory.
Signed-off-by: Zbigniew Kempczyński
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_gt.c
The vm insert_page is useful to insert a vma-less page into the GGTT,
which so far is always to map something through the mappable aperture,
usually when the entire VMA doesn't fit, or if we specifically don't
want to hog it, since it's generally quite limited in size.
On platforms including DG1 t
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
v2: just use gen8_pte_encode for dg1
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
--
== Series Details ==
Series: drm/i915: Apply VT-d scanout adjustment to the VMA
URL : https://patchwork.freedesktop.org/series/86625/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9721_full -> Patchwork_19569_full
Summary
-
Quoting Tvrtko Ursulin (2021-02-03 11:44:56)
> From: Tvrtko Ursulin
>
> Useful to mimick top view.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> man/intel_gpu_top.rst | 2 +-
> tools/intel_gpu_top.c | 46 +++
> 2 files changed, 34 insertions(+), 14 deletion
On 03/02/2021 11:47, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-03 11:44:55)
From: Tvrtko Ursulin
It is useful to let the user know what is the currently active sort mode.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 15 +--
1 file changed, 13 insertion
Quoting Tvrtko Ursulin (2021-02-03 11:44:55)
> From: Tvrtko Ursulin
>
> It is useful to let the user know what is the currently active sort mode.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> tools/intel_gpu_top.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff -
From: Tvrtko Ursulin
It is useful to let the user know what is the currently active sort mode.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 584aa2
From: Tvrtko Ursulin
Useful to mimick top view.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 2 +-
tools/intel_gpu_top.c | 46 +++
2 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rs
Quoting Tejas Upadhyay (2020-11-30 12:48:55)
> Removing force probe protection from RKL platform. Did
> not observe warnings, errors, flickering or any visual
> defects while doing ordinary tasks like browsing and
> editing documents in a two monitor setup.
>
> Signed-off-by: Tejas Upadhyay
We n
On Thu, Jan 28, 2021 at 09:13:49PM +0200, Imre Deak wrote:
> On Wed, Jan 27, 2021 at 08:19:09PM +0200, Imre Deak wrote:
> > At least on some TGL platforms PUNIT wants to access some display HW
> > registers, but it doesn't handle display power managment (disabling DC
> > states as required) and so
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gt: Move engine setup out of
set_default_submission (rev2)
URL : https://patchwork.freedesktop.org/series/86603/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721_full -> Patchwork_19568_full
===
Since we setup the submission method for the engines once, it is easy to
assign an enum and use that instead of probing into the backends.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 8 +++-
drivers/gpu/drm/i915/gt/inte
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
v2: An overabundance of caution is alw
Make the ability to suspend and resume a request and its dependents
generic.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 167 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +-
drivers/gpu/drm/i915/i915_sche
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend.
While this operates on the common structs, we do have a bit of backend
knowledge, which is harmless for !lrc but still unsightly.
Signed-off-by: Chris Wilson
Reviewed-by: T
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilso
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend. It already
operates on the common structs, so just a matter of moving and renaming.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execl
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the enti
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