i915.live_selftests takes 3 options:
0: do nothing
-1: run selftests and prevent continuation of device probing
1: run selftests, and allow continuation of device probing
Currently, we prevent the device from being loaded if the live selftests
fail. This seems reasonable, since the selftests
On 2021-02-05 9:53 p.m., Daniel Vetter wrote:
On Fri, Feb 5, 2021 at 7:37 PM Kees Cook wrote:
On Fri, Feb 05, 2021 at 04:37:52PM +, Chris Wilson wrote:
Userspace has discovered the functionality offered by SYS_kcmp and has
started to depend upon it. In particular, Mesa uses SYS_kcmp for
o
On 08/02/2021 10:52, Chris Wilson wrote:
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimali
On 2/8/2021 4:45 PM, Jani Nikula wrote:
On Thu, 04 Feb 2021, Ankit Nautiyal wrote:
DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
Do not read the registers if DPCD rev < 1.4.
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Please use Fixes: to reference c
On 08/02/2021 10:52, Chris Wilson wrote:
Whether a scheduler chooses to implement timeslicing is up to it, and
not an underlying property of the HW engine. The scheduler does depend
on the HW supporting preemption.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h
On 2/8/2021 4:43 PM, Jani Nikula wrote:
On Mon, 08 Feb 2021, Ankit Nautiyal wrote:
Legacy LSPCON chip from MCA and Parade is only used for platforms
between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same.
v2: Added the missing 'drm/' to subject (Jani N).
Signed-off-by: Anki
Adjust the KVMGT page tracking callbacks.
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc: intel-gvt-...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Paolo Bonzini
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/
On Fri, Feb 05, 2021 at 06:09:12PM -0800, Daniele Ceraolo Spurio wrote:
> This will be used for communication between the i915 driver and the mei
> one. Defining it in a stand-alone patch to avoid circualr dependedencies
> between the patches modifying the 2 drivers.
>
> Split out from an original
On 08/02/2021 10:52, Chris Wilson wrote:
Centralise the means by which to remove a context from execution to the
scheduler, allowing the backends to specialise as necessary. Note that
without backend support, we can simplify the procedure to forcibly reset
the HW to remove the context.
Signed-
On Thu, 04 Feb 2021, Ankit Nautiyal wrote:
> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> Do not read the registers if DPCD rev < 1.4.
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Please use Fixes: to reference commits that this patch fixes.
Please
On Fri, Feb 05, 2021 at 06:45:11PM -0500, Lyude Paul wrote:
> No functional changes, just move set_vesa_backlight_enable() closer to it's
> only caller: intel_dp_aux_vesa_enable_backlight().
>
> Signed-off-by: Lyude Paul
Reviewed-by: Rodrigo Vivi
> ---
> .../drm/i915/display/intel_dp_aux_back
On Fri, Feb 05, 2021 at 06:45:10PM -0500, Lyude Paul wrote:
> Since we're about to be moving this code into shared DRM helpers, we might
> as well start to cache certain backlight capabilities that can be
> determined from the EDP DPCD, and are likely to be relevant to the majority
> of drivers usi
On Mon, 08 Feb 2021, Ankit Nautiyal wrote:
> Legacy LSPCON chip from MCA and Parade is only used for platforms
> between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same.
>
> v2: Added the missing 'drm/' to subject (Jani N).
>
> Signed-off-by: Ankit Nautiyal
> Acked-by: Jani Nikula
On Fri, Feb 05, 2021 at 06:45:08PM -0500, Lyude Paul wrote:
> This is kind of an annoying aspect of DRM's DP helpers:
> drm_dp_dpcd_readb/writeb() return the size of bytes read/written on
> success, thus we want to check against that instead of checking if the
> return value is less than 0.
>
> I'
On Mon, 08 Feb 2021, Jani Nikula wrote:
> Subject prefix: drm/i915:
>
> On Mon, 08 Feb 2021, Ankit Nautiyal wrote:
>> Legacy LSPCON chip from MCA and Parade is only used for platforms
>> between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same.
>>
>> Signed-off-by: Ankit Nautiyal
Previously, commit 531810caa9f4 ("KVM: x86/mmu: Use
an rwlock for the x86 MMU") replaced KVM's mmu_lock
with type rwlock_t. This will cause a build failure
in kvmgt, which uses the same lock when trying to add/
remove some GFNs to/from the page tracker. Fix it with
write_lock/unlocks in kvmgt.
Rep
Legacy LSPCON chip from MCA and Parade is only used for platforms
between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same.
v2: Added the missing 'drm/' to subject (Jani N).
Signed-off-by: Ankit Nautiyal
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file ch
Legacy LSPCON chip from MCA and Parade is only used for platforms
between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same.
v2: Fixed the prefix to append drm (Jani N).
Signed-off-by: Ankit Nautiyal
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed
When we introduced the saturated workload detection to tell us to back
off from semaphore usage [semaphores have a noticeable impact on
contended bus cycles with the CPU for some heavy workloads], we first
introduced it as a per-context tracker. This allows individual contexts
to try and optimise t
Start extracting the scheduling flags from the engine. We begin with its
own existence by declaring whether or not the scheduler supports any
task reordering. This information can then be passed directly to the
user (using the SCHEDULER_CAPS) without having to infer in the user
interface.
Signed-o
The first "scheduler" was a topographical sorting of requests into
priority order. The execution order was deterministic, the earliest
submitted, highest priority request would be executed first. Priority
inheritance ensured that inversions were kept at bay, and allowed us to
dynamically boost prio
Primarily to smooth over differences with the guc backend that struggles
with smaller quanta, bump the default timeslicing to 5ms from 1ms.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.profile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i91
As we know when we expect the heartbeat to be checked for completion,
pass this information along as its deadline. We still do not complain if
the deadline is missed, at least until we have tried a few times, but it
will allow for quicker hang detection on systems where deadlines are
adhered to.
S
Centralise the means by which to remove a context from execution to the
scheduler, allowing the backends to specialise as necessary. Note that
without backend support, we can simplify the procedure to forcibly reset
the HW to remove the context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i9
Allow multiple requests to be queued unto a virtual engine, whereas
before we only allowed a single request to be queued at a time. The
advantage of keeping just one request in the queue was to ensure that we
always decided late which engine to use. However, with the introduction
of the virtual dea
To support legacy ring buffer scheduling, we want a virtual ringbuffer
for each client. These rings are purely for holding the requests as they
are being constructed on the CPU and never accessed by the GPU, so they
should not be bound into the GGTT, and we can use plain old WB mapped
pages.
As th
When we are not using semaphores with a context/engine, we can simply
reuse the same seqno location across wraps, but we still require each
timeline to have its own address. For LRC submission, each context is
prefixed by a per-process HWSP, which provides us with a unique location
for each context
For a modeset/pageflip, there is a very precise deadline by which the
frame must be completed in order to hit the vblank and be shown. While
we don't pass along that exact information, we can at least inform the
scheduler that this request-chain needs to be completed asap.
Signed-off-by: Chris Wil
Replace the priolist rbtree with a skiplist. The crucial difference is
that walking and removing the first element of a skiplist is O(1), but
O(lgN) for an rbtree, as we need to rebalance on remove. This is a
hindrance for submission latency as it occurs between picking a request
for the priolist a
Busy-waiting is used for preempt-to-busy by schedulers, if they so
choose. Since it is not a property of the engine, but that of the
submission backend, move the flag from out of the engine to
i915_sched_engine.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilso
Relative timelines are relative to either the global or per-process
HWSP, and so we can replace the absolute addressing with store-index
variants for position invariance.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 98 +--
Allow the sysadmin to specify whether we should prevent the CPU from
entering higher C-states while waiting for the CPU, in order to reduce
the latency of request completions and so speed up client continuations.
The target dma latency can be adjusted per-engine using,
/sys/class/drm/card
The current implementation of walking the children of a deferred
requests lacks the backtracking required to reduce the dfs to linear.
Having pulled it from execlists into the common layer, we can reuse the
dfs code for priority inheritance.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
The heartbeat runs through a few phases that we expect to complete
within a certain number of heartbeat intervals. First we must submit the
heartbeat to the queue, and if the queue is occupied it may take a
couple of intervals before the heartbeat preempts the workload and is
submitted to HW. Once
Whether a scheduler chooses to implement timeslicing is up to it, and
not an underlying property of the HW engine. The scheduler does depend
on the HW supporting preemption.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 6 ++
drivers/gpu/drm/i915/gt/inte
A quick test to verify that the backend accepts each type of timeline
and can use them to track and control request emission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 105
1 file changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/i9
Before we take the irqsafe spinlock to dequeue requests and submit them
to HW, first do the check whether we need to take any action (i.e.
whether the HW is ready for some work, or if we need to preempt the
currently executing context) without taking the lock. We will then
likely skip taking the sp
This was removed in commit 478ffad6d690 ("drm/i915: drop
engine_pin/unpin_breadcrumbs_irq") as the last user had been removed,
but now there is a promise of a new user in the next patch.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 24
Build a bare bones scheduler to sit on top the global legacy ringbuffer
submission. This virtual execlists scheme should be applicable to all
older platforms.
A key problem we have with the legacy ring buffer submission is that it
only allows for FIFO queuing. All clients share the global request
A key prolem with legacy ring buffer submission is that it is an inheret
FIFO queue across all clients; if one blocks, they all block. A
scheduler allows us to avoid that limitation, and ensures that all
clients can submit in parallel, removing the resource contention of the
global ringbuffer.
Hav
Switch over from FIFO global submission to the priority-sorted
topographical scheduler. At the cost of more busy work on the CPU to
keep the GPU supplied with the next packet of requests, this allows us
to reorder requests around submission stalls and so allow low latency
under load while maintaini
Adapt the old legacy ring submission to use a passthrough tasklet so
that we can plug it into the scheduler.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 167 +++---
2 files changed, 107 inserti
If we allow for per-client timelines, even with legacy ring submission,
we open the door to a world full of possiblities [scheduling and
semaphores].
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 72 ++-
drivers/gpu/drm/i915/gt/gen2_engine_cs.h
Re-enable secure dispatch for gen6/gen7, primarily to workaround the
command parser and overly zealous command validation on Haswell. For
example this prevents making accurate measurements using a journal for
store results from the GPU without CPU intervention.
Signed-off-by: Chris Wilson
---
dr
While the HW may support preemption, whether or not the scheduler
enforces preemption by forcibly resetting the current context is
ultimately up to the scheduler.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 7 ++-
driver
Explicitly differentiate between the absolute and relative timelines,
and the global HWSP and ppHWSP relative offsets. When using a timeline
that is relative to a known status page, we can replace the absolute
addressing in the commands with indexed variants.
Signed-off-by: Chris Wilson
Reviewed-
In preparation for removing the has_initial_breadcrumb field, add a
helper function for the existing callers.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++--
drivers/gpu/
Currently we know that the timeline status page is at most a page in
size, and so we can preserve the lower 12bits of the offset when
relocating the status page in the GGTT. If we want to use a larger
object, such as the context state, we may not necessarily use a position
within the first page and
On Fri, Feb 05, 2021 at 10:00:12PM +, Chris Wilson wrote:
> Userspace has discovered the functionality offered by SYS_kcmp and has
> started to depend upon it. In particular, Mesa uses SYS_kcmp for
> os_same_file_description() in order to identify when two fd (e.g. device
> or dmabuf) point to
Subject prefix: drm/i915:
On Mon, 08 Feb 2021, Ankit Nautiyal wrote:
> Legacy LSPCON chip from MCA and Parade is only used for platforms
> between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same.
>
> Signed-off-by: Ankit Nautiyal
I cringe at the VBT having the bit set anyway,
On Fri, 05 Feb 2021, Ville Syrjälä wrote:
> Temptation turned into code. I think I have a decent way forward
> with this idea on top of my other refactorings, so I'd just drop
> this patch.
Thanks for the patches and review and perseverance! Finally pushed
everything except this patch, and nothin
On Fri, Feb 05, 2021 at 11:19:19PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 05, 2021 at 06:24:08PM +0200, Ville Syrjälä wrote:
> > On Fri, Feb 05, 2021 at 04:46:27PM +0100, Daniel Vetter wrote:
> > > On Thu, Feb 04, 2021 at 05:55:28PM +0200, Ville Syrjälä wrote:
> > > > On Thu, Feb 04, 2021 at 04:
== Series Details ==
Series: vfio/pci: Add support for opregion v2.0+ (rev3)
URL : https://patchwork.freedesktop.org/series/84494/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9745 -> Patchwork_19625
Summary
---
**S
== Series Details ==
Series: i915: Fix HAS_LSPCON macro for platforms between GEN9 and GEN10
URL : https://patchwork.freedesktop.org/series/86832/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9745_full -> Patchwork_19624_full
==
== Series Details ==
Series: vfio/pci: Add support for opregion v2.0+ (rev3)
URL : https://patchwork.freedesktop.org/series/84494/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cdc32418f054 vfio/pci: Add support for opregion v2.1+
-:72: CHECK:PARENTHESIS_ALIGNMENT: Alignment sh
Before opregion version 2.0 VBT data is stored in opregion mailbox #4,
However, When VBT data exceeds 6KB size and cannot be within mailbox #4
starting from opregion v2.0+, Extended VBT region, next to opregion, is
used to hold the VBT data, so the total size will be opregion size plus
extended VBT
Hi
Am 06.02.21 um 00:45 schrieb Lyude Paul:
Since we're about to implement eDP backlight support in nouveau using the
standard protocol from VESA, we might as well just take the code that's
already written for this and move it into a set of shared DRM helpers.
Note that these helpers are intend
== Series Details ==
Series: i915: Fix HAS_LSPCON macro for platforms between GEN9 and GEN10
URL : https://patchwork.freedesktop.org/series/86832/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9745 -> Patchwork_19624
Summar
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