== Series Details ==
Series: Non-interface changing GuC CTBs updates (rev2)
URL : https://patchwork.freedesktop.org/series/90552/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/
== Series Details ==
Series: Non-interface changing GuC CTBs updates (rev2)
URL : https://patchwork.freedesktop.org/series/90552/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6b6bffd59ced drm/i915/guc: skip disabling CTBs before sanitizing the GuC
3f9bbaddbf9d drm/i915/guc: us
From: Michal Wajdeczko
We are no longer using descriptor to hold G2H replies and we are
protecting access to the descriptor and command buffer by the
separate spinlock, so we can stop using mutex.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
dri
From: Michal Wajdeczko
In upcoming GuC firmware, CTB size will be removed from the CTB
descriptor so we must keep it locally for any calculations.
While around, improve some debug messages and helpers.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
--
From: Michal Wajdeczko
In irq handler try to receive just single G2H message, let other
messages to be received from tasklet.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 67 ---
dr
From: Daniele Ceraolo Spurio
We have a couple of failure injection points in the CT enablement path,
so we need to use i915_probe_error() to select the appropriate log level.
A new macro (CT_PROBE_ERROR) has been added to the set of CT logging
macros to be used in this scenario and upcoming ones.
As discussed in [1] we are breaking that large series into a several
smaller ones. This series is the non-interface changing part of step #2
- it makes all the changes needed before updating the GuC firwmare to a
new version without breaking any old interfaces.
A follow on series will be squashed
From: Michal Wajdeczko
Stop using fence/status from CTB descriptor as future GuC ABI will
no longer support replies over CTB descriptor.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
.../gt/uc/abi/guc_communication_ctb_abi.h | 4 +-
drivers/
From: Daniele Ceraolo Spurio
If we're about to sanitize the GuC, something might have going wrong
beforehand, so we should avoid trying to talk to it. Even if GuC is
still running fine, the sanitize will reset its internal state and clear
the CTB registration, so there is still no need to explici
Drop the variable guc->interrupts.enabled as this variable is just
leading to bugs creeping into the code.
e.g. A full GPU reset disables the GuC interrupts but forgot to clear
guc->interrupts.enabled, guc->interrupts.enabled being true suppresses
interrupts from getting re-enabled and now we are
Ensure H2G buffer updates are visible before descriptor tail updates by
inserting a barrier between the H2G buffer update and the tail. The
barrier is simple wmb() for SMEM and is register write for LMEM. This is
needed if more than 1 H2G can be inflight at once.
Signed-off-by: Matthew Brost
Cc:
From: Michal Wajdeczko
We can retrieve offsets to cmds buffers and descriptor from
actual pointers that we already keep locally.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 16 ++--
1 file
From: Daniele Ceraolo Spurio
In GuC submission mode the CS is owned by the GuC FW, so all CS status
interrupts are handled by it. We only need the user interrupt as that
signals request completion.
Since we're now starting the engines directly in GuC submission mode
when selected, we can stop sw
From: Michal Wajdeczko
Our fwif.h file is now mix of strict firmware ABI definitions and
set of our helpers. In anticipation of upcoming changes to the GuC
interface try to keep them separate in smaller maintainable files.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-b
From: Michal Wajdeczko
Future GuC will require CTB buffers sizes to be multiple of 4K.
Make these changes now as this shouldn't impact us too much.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_
From: Michal Wajdeczko
Upcoming GuC firmware will always require just two CTBs and we
also plan to configure them with different sizes, so definining
them as array is no longer suitable.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/d
From: Michal Wajdeczko
We want to stop using guc.send_mutex while sending CTB messages
so we have to start protecting access to CTB send descriptor.
For completeness protect also CTB receive descriptor.
Add spinlock to struct intel_guc_ct_buffer and start using it.
Signed-off-by: Michal Wajdec
From: Michal Wajdeczko
Since most of future CT traffic will be based on G2H requests,
instead of copying incoming CT message to static buffer and then
create new allocation for such request, always copy incoming CT
message to new allocation. Also by doing it while reading CT
header, we can safely
From: Rodrigo Vivi
This action is no-op in the GuC side for a few versions already
and it is getting entirely removed soon, in an upcoming version.
Time to remove before we face communication issues.
Cc: Vinay Belgaumkar
Signed-off-by: Rodrigo Vivi
Signed-off-by: Matthew Brost
Acked-by: Mich
From: Michal Wajdeczko
In upcoming patch we will allow more CTB requests to be sent in
parallel to the GuC for processing, so we shouldn't assume any more
that GuC will always reply without 10ms.
Use bigger value from CONFIG_DRM_I915_GUC_CTB_TIMEOUT instead.
v2: Add CONFIG_DRM_I915_GUC_CTB_TIME
From: Michal Wajdeczko
Generic helpers should be placed in i915_utils.h.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/i915_utils.h | 5 +
drivers/gpu/drm/i915/i915_vma.h | 5 -
2 files changed, 5 insertions(+), 5 d
== Series Details ==
Series: drm/i915/gt: Introduce timeslicing for userspace
URL : https://patchwork.freedesktop.org/series/90568/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20195
Summary
---
*
== Series Details ==
Series: Another small batch of reviewed Xe_LPD patches
URL : https://patchwork.freedesktop.org/series/90560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20194_full
Summary
Test-with: 20210524124806.241439-1-tejaskumarx.surendrakumar.upadh...@intel.com
Tejas Upadhyay (1):
drm/i915/gt: Declare when we enabled timeslicing
drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 +
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 2 insertions(+)
--
2.31.
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
V3: %s/TIMESLICE_BIT/HAS_TIMESLICES
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic tim
== Series Details ==
Series: dma-buf: Add an API for exporting sync files (v11)
URL : https://patchwork.freedesktop.org/series/90555/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20193_full
Summary
== Series Details ==
Series: Non-interface changing GuC CTBs updates
URL : https://patchwork.freedesktop.org/series/90552/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20192_full
Summary
---
== Series Details ==
Series: Another small batch of reviewed Xe_LPD patches
URL : https://patchwork.freedesktop.org/series/90560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20194
Summary
---
**S
On Wed, 12 May 2021 at 03:05, Daniel Vetter wrote:
>
> On Tue, May 11, 2021 at 10:31:39AM +0200, Zbigniew Kempczyński wrote:
> > We have established previously we stop using relocations starting
> > from gen12 platforms with Tigerlake as an exception. Unfortunately
> > we need extend transition pe
== Series Details ==
Series: Another small batch of reviewed Xe_LPD patches
URL : https://patchwork.freedesktop.org/series/90560/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/
== Series Details ==
Series: Another small batch of reviewed Xe_LPD patches
URL : https://patchwork.freedesktop.org/series/90560/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6973fd1b00ee drm/i915/xelpd: Enhanced pipe underrun reporting
1a22f3f8ec72 drm/i915/xelpd: Add VRR gua
XE_LPD brings enhanced underrun recovery: the hardware can somewhat
mitigate underruns by using an interpolated replacement pixel (soft
underrun) or the previous pixel (hard underrun). Furthermore, underruns
can now be caused downstream by the port, even if the pipe itself is
operating properly.
From: Manasi Navare
On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield
replacing the pipeline full and deprecating the pipeline override
bit.
This patch adds this corresponding bitfield in the register defs,
crtc state vrr structure and populates this in vrr compute
config and vrr ena
From: Gwan-gyeong Mun
It removes intel_crtc_state from function argument of
intel_psr_enable_source() in order to use intel_psr_enable_source()
without intel_crtc_state on other psr internal functions.
And we can get cpu_trancoder from intel_psr, therefore we don't need to
pass intel_crtc_state t
Another small collection of Xe_LPD patches that have r-b's now and just
need another CI pass to merge.
Gwan-gyeong Mun (1):
drm/i915/display: Remove a redundant function argument from
intel_psr_enable_source()
Manasi Navare (1):
drm/i915/xelpd: Add VRR guardband for VRR CTL
Matt Roper (1
== Series Details ==
Series: drm/i915: Check HDMI sink deep color capabilities during .mode_valid()
(rev3)
URL : https://patchwork.freedesktop.org/series/90036/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10132_full -> Patchwork_20191_full
==
== Series Details ==
Series: dma-buf: Add an API for exporting sync files (v11)
URL : https://patchwork.freedesktop.org/series/90555/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20193
Summary
---
== Series Details ==
Series: drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/90164/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10132_full -> Patchwork_20190_full
Summary
== Series Details ==
Series: dma-buf: Add an API for exporting sync files (v11)
URL : https://patchwork.freedesktop.org/series/90555/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gp
== Series Details ==
Series: dma-buf: Add an API for exporting sync files (v11)
URL : https://patchwork.freedesktop.org/series/90555/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
225a57e84149 dma-buf: Add dma_fence_array_for_each (v2)
-:75: CHECK:MACRO_ARG_REUSE: Macro argumen
== Series Details ==
Series: Non-interface changing GuC CTBs updates
URL : https://patchwork.freedesktop.org/series/90552/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20192
Summary
---
**SUCCESS*
Modern userspace APIs like Vulkan are built on an explicit
synchronization model. This doesn't always play nicely with the
implicit synchronization used in the kernel and assumed by X11 and
Wayland. The client -> compositor half of the synchronization isn't too
bad, at least on intel, because we
This patch is analogous to the previous sync file export patch in that
it allows you to import a sync_file into a dma-buf. Unlike the previous
patch, however, this does add genuinely new functionality to dma-buf.
Without this, the only way to attach a sync_file to a dma-buf is to
submit a batch to
This adds a new "DMA Buffer ioctls" section to the dma-buf docs and adds
documentation for DMA_BUF_IOCTL_SYNC.
Signed-off-by: Jason Ekstrand
Cc: Daniel Vetter
Cc: Christian König
Cc: Sumit Semwal
---
Documentation/driver-api/dma-buf.rst | 8 +++
include/uapi/linux/dma-buf.h | 32
For dma-buf sync_file import, we want to get all the fences on a
dma_resv plus one more. We could wrap the fence we get back in an array
fence or we could make dma_resv_get_singleton_unlocked take "one more"
to make this case easier.
Signed-off-by: Jason Ekstrand
Reviewed-by: Daniel Vetter
Cc:
Add a helper function to get a single fence representing
all fences in a dma_resv object.
This fence is either the only one in the object or all not
signaled fences of the object in a flatted out dma_fence_array.
v2 (Jason Ekstrand):
- Take reference of fences both for creating the dma_fence_arr
None of these helpers actually leak any RCU details to the caller. They
all assume you have a genuine reference, take the RCU read lock, and
retry if needed. Naming them with an _rcu is likely to cause callers
more panic than needed.
v2 (Jason Ekstrand):
- Fix function argument indentation
Sig
From: Christian König
Add a helper to iterate over all fences in a dma_fence_array object.
v2 (Jason Ekstrand)
- Return NULL from dma_fence_array_first if head == NULL. This matches
the iterator behavior of dma_fence_chain_for_each in that it iterates
zero times if head == NULL.
- Retur
Modern userspace APIs like Vulkan are built on an explicit
synchronization model. This doesn't always play nicely with the
implicit synchronization used in the kernel and assumed by X11 and
Wayland. The client -> compositor half of the synchronization isn't too
bad, at least on intel, because we
== Series Details ==
Series: Non-interface changing GuC CTBs updates
URL : https://patchwork.freedesktop.org/series/90552/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/di
== Series Details ==
Series: Non-interface changing GuC CTBs updates
URL : https://patchwork.freedesktop.org/series/90552/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
232417d031b9 drm/i915/guc: skip disabling CTBs before sanitizing the GuC
341c70656750 drm/i915/guc: use probe
Ensure H2G buffer updates are visible before descriptor tail updates by
inserting a barrier between the H2G buffer update and the tail. The
barrier is simple wmb() for SMEM and is register write for LMEM. This is
needed if more than 1 H2G can be inflight at once.
Signed-off-by: Matthew Brost
Cc:
From: Michal Wajdeczko
We are no longer using descriptor to hold G2H replies and we are
protecting access to the descriptor and command buffer by the
separate spinlock, so we can stop using mutex.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
dri
From: Michal Wajdeczko
In irq handler try to receive just single G2H message, let other
messages to be received from tasklet.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 67 ---
dr
From: Michal Wajdeczko
Since most of future CT traffic will be based on G2H requests,
instead of copying incoming CT message to static buffer and then
create new allocation for such request, always copy incoming CT
message to new allocation. Also by doing it while reading CT
header, we can safely
From: Michal Wajdeczko
In upcoming patch we will allow more CTB requests to be sent in
parallel to the GuC for procesing, so we shouldn't assume any more
that GuC will always reply without 10ms.
Use bigger value from CONFIG_DRM_I915_GUC_CTB_TIMEOUT instead.
v2: Add CONFIG_DRM_I915_GUC_CTB_TIMEO
From: Michal Wajdeczko
In upcoming GuC firmware, CTB size will be removed from the CTB
descriptor so we must keep it locally for any calculations.
While around, improve some debug messages and helpers.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
--
From: Michal Wajdeczko
We want to stop using guc.send_mutex while sending CTB messages
so we have to start protecting access to CTB send descriptor.
For completeness protect also CTB receive descriptor.
Add spinlock to struct intel_guc_ct_buffer and start using it.
Signed-off-by: Michal Wajdec
From: Michal Wajdeczko
Future GuC will require CTB buffers sizes to be multiple of 4K.
Make these changes now as this shouldn't impact us too much.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_
From: Michal Wajdeczko
Upcoming GuC firmware will always require just two CTBs and we
also plan to configure them with different sizes, so definining
them as array is no longer suitable.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/d
From: Michal Wajdeczko
Stop using fence/status from CTB descriptor as future GuC ABI will
no longer support replies over CTB descriptor.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
.../gt/uc/abi/guc_communication_ctb_abi.h | 4 +-
drivers/
From: Michal Wajdeczko
We can retrieve offsets to cmds buffers and descriptor from
actual pointers that we already keep locally.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 16 ++--
1 file
From: Michal Wajdeczko
Generic helpers should be placed in i915_utils.h.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/i915_utils.h | 5 +
drivers/gpu/drm/i915/i915_vma.h | 5 -
2 files changed, 5 insertions(+), 5 d
From: Daniele Ceraolo Spurio
In GuC submission mode the CS is owned by the GuC FW, so all CS status
interrupts are handled by it. We only need the user interrupt as that
signals request completion.
Since we're now starting the engines directly in GuC submission mode
when selected, we can stop sw
From: Michal Wajdeczko
Our fwif.h file is now mix of strict firmware ABI definitions and
set of our helpers. In anticipation of upcoming changes to the GuC
interface try to keep them separate in smaller maintainable files.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-b
From: Daniele Ceraolo Spurio
If we're about to sanitize the GuC, something might have going wrong
beforehand, so we should avoid trying to talk to it. Even if GuC is
still running fine, the sanitize will reset its internal state and clear
the CTB registration, so there is still no need to explici
As discussed in [1] we are breaking that large series into a several
smaller ones. This series is the non-interface changing part of step #2
- it makes all the changes needed before updating the GuC firwmare to a
new version without breaking any old interfaces.
A follow on series will be squashed
From: Rodrigo Vivi
This action is no-op in the GuC side for a few versions already
and it is getting entirely removed soon, in an upcoming version.
Time to remove before we face communication issues.
Cc: Vinay Belgaumkar
Signed-off-by: Rodrigo Vivi
Signed-off-by: Matthew Brost
Acked-by: Mic
From: Daniele Ceraolo Spurio
We have a couple of failure injection points in the CT enablement path,
so we need to use i915_probe_error() to select the appropriate log level.
A new macro (CT_PROBE_ERROR) has been added to the set of CT logging
macros to be used in this scenario and upcoming ones.
Hi Daniele,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.13-rc3
next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting
== Series Details ==
Series: drm/i915: Remove the repeated declaration
URL : https://patchwork.freedesktop.org/series/90524/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10131_full -> Patchwork_20187_full
Summary
---
On 25.05.2021 20:15, Matthew Brost wrote:
> On Thu, May 06, 2021 at 12:13:32PM -0700, Matthew Brost wrote:
>> From: Michal Wajdeczko
>>
>> In irq handler try to receive just single G2H message, let other
>> messages to be received from tasklet.
>>
>> Signed-off-by: Michal Wajdeczko
>> Signed-o
On 25.05.2021 20:08, Matthew Brost wrote:
> On Thu, May 06, 2021 at 12:13:29PM -0700, Matthew Brost wrote:
>> From: Michal Wajdeczko
>>
>> In upcoming patch we will allow more CTB requests to be sent in
>> parallel to the GuC for procesing, so we shouldn't assume any more
>> that GuC will alway
On Tue, May 25, 2021 at 9:19 PM Jason Ekstrand wrote:
>
> On Tue, May 25, 2021 at 10:37 AM Daniel Vetter wrote:
> >
> > On Mon, May 24, 2021 at 03:59:54PM -0500, Jason Ekstrand wrote:
> > > This patch is analogous to the previous sync file export patch in that
> > > it allows you to import a sync
On Tue, May 25, 2021 at 10:37 AM Daniel Vetter wrote:
>
> On Mon, May 24, 2021 at 03:59:54PM -0500, Jason Ekstrand wrote:
> > This patch is analogous to the previous sync file export patch in that
> > it allows you to import a sync_file into a dma-buf. Unlike the previous
> > patch, however, this
> -Original Message-
> From: Intel-gfx On Behalf Of
> Daniele Ceraolo Spurio
> Sent: Monday, May 24, 2021 10:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Vetter, Daniel ; Huang Sean Z
> ; dri-de...@lists.freedesktop.org; Chris Wilson
> ; Kondapally Kalyan
> ; Bommu, Krishnaiah
>
>
On Thu, May 06, 2021 at 12:13:33PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> Since most of future CT traffic will be based on G2H requests,
> instead of copying incoming CT message to static buffer and then
> create new allocation for such request, always copy incoming CT
> message
> It's tedious to review this all the time, and my audit showed that
> arcpgu actually forgot to set this.
>
> Make this the default and stop worrying.
>
> Again I sprinkled WARN_ON_ONCE on top to make sure we don't have
> strange combinations of hooks: cleanup_fb without prepare_fb doesn't
> make
On Thu, May 06, 2021 at 12:13:32PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> In irq handler try to receive just single G2H message, let other
> messages to be received from tasklet.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/
On Thu, May 06, 2021 at 12:13:29PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> In upcoming patch we will allow more CTB requests to be sent in
> parallel to the GuC for procesing, so we shouldn't assume any more
> that GuC will always reply without 10ms.
>
> Use bigger value from CO
On Tue, May 25, 2021 at 11:16:12AM +0100, Tvrtko Ursulin wrote:
>
> On 06/05/2021 20:14, Matthew Brost wrote:
> > From: John Harrison
> >
> > The serial number tracking of engines happens at the backend of
> > request submission and was expecting to only be given physical
> > engines. However, i
== Series Details ==
Series: drm/i915: Check HDMI sink deep color capabilities during .mode_valid()
(rev3)
URL : https://patchwork.freedesktop.org/series/90036/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10132 -> Patchwork_20191
On Tue, May 25, 2021 at 07:48:12PM +0200, Noralf Trønnes wrote:
> > It's tedious to review this all the time, and my audit showed that
> > arcpgu actually forgot to set this.
> >
> > Make this the default and stop worrying.
> >
> > Again I sprinkled WARN_ON_ONCE on top to make sure we don't have
>
On Mon, May 24, 2021 at 03:31:25PM +0200, Michal Wajdeczko wrote:
>
>
> On 06.05.2021 21:13, Matthew Brost wrote:
> > CTB writes are now in the path of command submission and should be
> > optimized for performance. Rather than reading CTB descriptor values
> > (e.g. head, tail, size) which could
On Mon, May 24, 2021 at 01:59:54PM +0200, Michal Wajdeczko wrote:
>
>
> On 06.05.2021 21:13, Matthew Brost wrote:
> > Improve the error message when a unsolicited CT response is received by
> > printing fence that couldn't be found, the last fence, and all requests
> > with a response outstanding
On Mon, May 24, 2021 at 02:21:42PM +0200, Michal Wajdeczko wrote:
>
>
> On 06.05.2021 21:13, Matthew Brost wrote:
> > Add non blocking CTB send function, intel_guc_send_nb. In order to
> > support a non blocking CTB send function a spin lock is needed to
>
> spin lock was added in 16/97
>
> > p
On Tue, 2021-05-25 at 06:30 +, Patchwork wrote:
Patch Details
Series: series starting with [1/5] drm/i915/display/adl_p: Drop earlier return
in tc_has_modular_fia()
URL:https://patchwork.freedesktop.org/series/90495/
State: success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip
On Tue, 2021-05-25 at 13:55 +0300, Jani Nikula wrote:
> On Mon, 24 May 2021, José Roberto de Souza wrote:
> > We are missing the implementation of some workarounds to enabled PSR2
> > in Alderlake P, so to avoid any CI report of issues around PSR2
> > disabling it until all PSR2 workarounds are im
On Tue, May 25, 2021 at 10:21:00AM +0100, Tvrtko Ursulin wrote:
>
> On 06/05/2021 20:13, Matthew Brost wrote:
> > Add non blocking CTB send function, intel_guc_send_nb. In order to
> > support a non blocking CTB send function a spin lock is needed to
> > protect the CTB descriptors fields. Also th
On Mon, May 24, 2021 at 12:21:03PM -0700, Anusha Srivatsa wrote:
Move struct intel_dmc from i915_drv.h to intel_dmc.h.
v2: Add includes along with moving the struct.
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.h
== Series Details ==
Series: drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/90164/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10132 -> Patchwork_20190
Summary
---
On Tue, May 25, 2021 at 10:24:09AM +0100, Tvrtko Ursulin wrote:
>
> On 06/05/2021 20:13, Matthew Brost wrote:
> > With the introduction of non-blocking CTBs more than one CTB can be in
> > flight at a time. Increasing the size of the CTBs should reduce how
> > often software hits the case where no
On Tue, May 25, 2021 at 10:43:32AM +0100, Tvrtko Ursulin wrote:
>
> On 06/05/2021 20:13, Matthew Brost wrote:
> > Implement GuC submission tasklet for new interface. The new GuC
> > interface uses H2G to submit contexts to the GuC. Since H2G use a single
> > channel, a single tasklet submits is us
On Tue, May 25, 2021 at 11:06:00AM +0100, Tvrtko Ursulin wrote:
>
> On 06/05/2021 20:14, Matthew Brost wrote:
> > When running the GuC the GPU can't be considered idle if the GuC still
> > has contexts pinned. As such, a call has been added in
> > intel_gt_wait_for_idle to idle the UC and in turn
Hi Tejas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip linus/master v5.13-rc3 next-20210525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we
On Tue, May 25, 2021 at 10:52:01AM +0100, Tvrtko Ursulin wrote:
>
> On 06/05/2021 20:14, Matthew Brost wrote:
> > Disable semaphores when using GuC scheduling as semaphores are broken in
> > the current GuC firmware.
>
> What is "current"? Given that the patch itself is like year and a half old.
On Tue, May 25, 2021 at 03:07:06PM +0200, Michal Wajdeczko wrote:
>
>
> On 25.05.2021 04:53, Matthew Brost wrote:
> > On Thu, May 06, 2021 at 12:13:26PM -0700, Matthew Brost wrote:
> >> From: Michal Wajdeczko
> >>
> >> We can retrieve offsets to cmds buffers and descriptor from
> >> actual point
On Tue, May 25, 2021 at 04:15:15PM +0200, Michal Wajdeczko wrote:
>
>
> On 24.05.2021 20:35, Matthew Brost wrote:
> > On Mon, May 24, 2021 at 02:58:12PM +0200, Michal Wajdeczko wrote:
> >>
> >>
> >> On 06.05.2021 21:13, Matthew Brost wrote:
> >>> Implement a stall timer which fails H2G CTBs once
== Series Details ==
Series: drm/i915: g4x/vlv/chv CxSR/wm fixes/cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/90164/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu
On Tue, May 25, 2021 at 11:32:26AM +0100, Tvrtko Ursulin wrote:
>
> On 06/05/2021 20:13, Matthew Brost wrote:
> > Basic GuC submission support. This is the first bullet point in the
> > upstreaming plan covered in the following RFC [1].
> >
> > At a very high level the GuC is a piece of firmware
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