Hi Matt,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next v5.14-rc2 next-20210723]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base
On Sat, Jul 24, 2021 at 02:28:29AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Program chicken bit during DP MST sequence on TGL+
> URL : https://patchwork.freedesktop.org/series/92958/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
== Series Details ==
Series: drm/i915: Program chicken bit during DP MST sequence on TGL+
URL : https://patchwork.freedesktop.org/series/92958/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10379_full -> Patchwork_20696_full
[AMD Official Use Only]
I just want to make a comment that with this approach (the ns) calculating the
percentage will take at least two reads of the fdinfo per pid over some time.
Some engines may be able to provide a single shot percentage usage over an
internal integration period. That is,
Generally a big fan.
--Jason
On July 23, 2021 19:11:34 Lucas De Marchi wrote:
Patches 1 and 2 are already being reviewed elsewhere. Discussion on 2nd
patch made me revive something I started after comment from Ville
at
== Series Details ==
Series: drm/i915/userptr: Probe existence of backing struct pages upon creation
URL : https://patchwork.freedesktop.org/series/92948/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10379_full -> Patchwork_20695_full
== Series Details ==
Series: Remove CNL support
URL : https://patchwork.freedesktop.org/series/92969/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10383 -> Patchwork_20701
Summary
---
**SUCCESS**
No regressions
On 7/22/2021 4:54 PM, Matthew Brost wrote:
Implement a simple static mapping algorithm of the i915 priority levels
(int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as
follows:
i915 level < 0 -> GuC low level (3)
i915 level == 0 -> GuC normal level (2)
On Fri, Jul 23, 2021 at 12:10:24PM -0700, Matt Roper wrote:
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
v2:
- Re-order intel_gt_info and intel_device_info slightly to avoid
unnecessary padding now that we've increased the
On 7/22/2021 4:53 PM, Matthew Brost wrote:
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function to virtual
engine specific functions, set all other variables / functions to guc
versions, and set the engine mask to
== Series Details ==
Series: Remove CNL support
URL : https://patchwork.freedesktop.org/series/92969/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: Remove CNL support
URL : https://patchwork.freedesktop.org/series/92969/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e27adf09b131 drm/i915: fix not reading DSC disable fuse in GLK
91073b079293 drm/i915/display: split DISPLAY_VER 9 and 10 in
== Series Details ==
Series: drm/i915: fix not reading DSC disable fuse in GLK
URL : https://patchwork.freedesktop.org/series/92967/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10383 -> Patchwork_20700
Summary
---
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc2 next-20210723]
[If your patch is applied to the wrong git tree
drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c:67:6: warning: symbol
'intel_eval_slpc_support' was not declared. Should it be static?
Reported-by: kernel test robot
Signed-off-by: kernel test robot
---
intel_guc_debugfs.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Cleanup remaining cases that we find CNL in the codebase.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 1 -
Remove registers that are not used anymore due to CNL removal and rename
those that are.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 192 ++-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
2 files changed, 48 insertions(+), 146
With the removal of CNL, let's consider ICL as the first platform using
those constants.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 24 +++
drivers/gpu/drm/i915/intel_dram.c | 32 +++
2 files changed, 28 insertions(+),
Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with
{==,>=} 11. With the removal of CNL, there is no platform with graphics
version equals 10.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 1 -
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10
Only one reference to CNL that is not needed, but code is the same for
GEN9_BC, so leave the code around and just remove the special
case for CNL.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
With the removal of CNL, let's consider GLK as the first platform using
those constants since GLK has DISPLAY_VER == 10.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/skl_scaler.c | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
2 files changed, 7
With the removal of CNL, let's consider ICL as the first platform using
that index.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +-
drivers/gpu/drm/i915/i915_drv.h| 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
The numbers of scalers and sprites depend on the display version, so use
it instead of GRAPHICS_VER. We were mixing both, which let me confused
while removing CNL and GRAPHICS_VER == 10.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_device_info.c | 8
1 file changed, 4
Remove references for CNL from pch detection.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_pch.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index cc44164e242b..d1d4b97b86f5 100644
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_ddi.c.
A lot of special code for CNL can be removed. There were some
__cnl.*() functions that were created to share the implementation
between ICL and CNL. Those are now embedded in the only
With all the users removed, finish removing the CNL platform definitions.
We will leave the PCI IDs around as those are exposed to userspace.
Even if mesa doesn't support CNL anymore, let's avoid build breakages
due to changing the headers.
Signed-off-by: Lucas De Marchi
---
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_dp.c.
Remove code and rename functions/macros accordingly to use ICL prefix.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dp.c | 35 -
1 file
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in skl_universal_plane.c.
Remove code and rename functions/macros accordingly to use ICL prefix.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 14
Remove special handling of PORT_F in i915_irq.c and only do it for
DISPLAY_VER == 11.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_display_power.c.
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 289 --
.../drm/i915/display/intel_display_power.h| 2 -
The only real platform with DISPLAY_VER == 10 is GLK, that doesn't have
combo phys. We don't need to handle CNL explicitly in
intel_combo_phy.c.
Remove code and rename functions/macros accordingly to use ICL prefix.
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/display/intel_combo_phy.c
Consider the new WOPCM size as starting in ICL rather than CNL since the
latter is being removed from the driver.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_wopcm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 +-
.../drm/i915/display/intel_ddi_buf_trans.c| 616 +-
The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
any checks and supporting code for CNL. For DISPLAY_VER >= 11,
ilk_load_csc_matrix() is not used, so make it handle GLK only.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_color.c | 5 ++---
1 file
CNL is the only platform with GRAPHICS_VER == 10. With its removal we
don't need to handle that version anymore.
Also we can now reduce the max number of slices: the call to
intel_sseu_set_info() with the highest number of slices comes from SKL
and BDW with 3 slices. Recent platforms actually
Remove support for CNL as it's highly untested, probably broken, and
there is no real platform that requires this code. This is part of CNL
removal from i915.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 41
The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_ddi.c.
Remove code and rename functions/macros accordingly to use ICL prefix.
There's one leftover reference to cnl that comes from the struct
intel_ddi_buf_trans. This will be renamed later when
No need for special CNL handling as there is no real platform with that
configuration.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
Only one reference to CNL that is not needed, but code is the same for
DISPLAY_VER >= 11, so leave the code around and just remove the special
case for CNL.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
Remove DMC firmware for CNL.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 9895fd957df9..3c3c6cb5c0df 100644
---
The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
any checks and supporting code for CNL. Remove code and rename
functions/macros accordingly.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +-
Only one reference to CNL that is not needed, but code is the same for
DISPLAY_VER >= 11, so leave the code around and just remove the special
case for CNL.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1
Explicit support for CNL is being removed from the driver as it's not
expected to work. Remove the workaround for PORT_F from
display/intel_bios.c so we can also remove the generic DISPLAY_VER == 10
calls to intel_ddi_init(): the only platform with that display version
is already handled
Commit 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt
in intel_bios.c") moved the workaround for broken or missing VBT to
intel_bios.c. However is_port_valid() only protects the handling of
different skus of the same display version. Since in
intel_setup_outputs() we share the
We were using GRAPHICS_VER() to handle SKL_DFSM register, which means we
were not handling GLK correctly since that has GRAPHICS_VER == 9, but
DISPLAY_VER == 10. Switch the entire branch to check DISPLAY_VER
which makes it more in line with Bspec.
Even though the Bspec has an exception for RKL in
Patches 1 and 2 are already being reviewed elsewhere. Discussion on 2nd
patch made me revive something I started after comment from Ville
at
https://patchwork.freedesktop.org/patch/428168/?series=88988=1#comment_768918
This removes CNL completely from the driver, while trying to rename
functions
On Fri, Jul 23, 2021 at 04:43:52PM -0700, Lucas De Marchi wrote:
> We were using GRAPHICS_VER() to handle SKL_DFSM register, which means we
> were not handling GLK correctly since that has GRAPHICS_VER == 9, but
> DISPLAY_VER == 10. Switch the entire branch to check DISPLAY_VER
> which makes it
== Series Details ==
Series: series starting with [v4,1/2] drm/i915: document caching related bits
URL : https://patchwork.freedesktop.org/series/92942/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10378_full -> Patchwork_20693_full
We were using GRAPHICS_VER() to handle SKL_DFSM register, which means we
were not handling GLK correctly since that has GRAPHICS_VER == 9, but
DISPLAY_VER == 10. Switch the entire branch to check DISPLAY_VER
which makes it more in line with Bspec.
Even though the Bspec has an exception for RKL in
On Wed, Jul 21, 2021 at 02:52:37PM -0700, Anusha Srivatsa wrote:
> Add support to the latest DMC firmware.
>
> Cc: Madhunitha Pradeep
> Signed-off-by: Anusha Srivatsa
> Reviewed-by: Madhumitha Pradeep <
You seem to have lost Madhumitha's email address on a couple of these
patches.
Matt
>
On 7/21/2021 11:21 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
This feature hands over the control of HW RC6 to the GuC.
GuC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GUCRC needs GuC submission to be enabled, and only
supported
== Series Details ==
Series: series starting with [01/10] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/92963/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10382 -> Patchwork_20699
On 7/21/2021 11:13 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Update the get/set min/max freq hooks to work for
SLPC case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on
On 7/21/2021 11:09 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland.
== Series Details ==
Series: drm/i915/bios: Fix ports mask (rev4)
URL : https://patchwork.freedesktop.org/series/92850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10378_full -> Patchwork_20692_full
Summary
---
== Series Details ==
Series: series starting with [01/10] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/92963/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [01/10] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/92963/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
51abed9a1d96 drm/i915: Check for nomodeset in i915_init() first
== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms (rev6)
URL : https://patchwork.freedesktop.org/series/92135/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10382 -> Patchwork_20698
Summary
---
== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms (rev6)
URL : https://patchwork.freedesktop.org/series/92135/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
== Series Details ==
Series: Begin enabling Xe_HP SDV and DG2 platforms (rev6)
URL : https://patchwork.freedesktop.org/series/92135/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f90c0193e566 drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP()
-:24:
== Series Details ==
Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev4)
URL : https://patchwork.freedesktop.org/series/92617/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10382 -> Patchwork_20697
== Series Details ==
Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev4)
URL : https://patchwork.freedesktop.org/series/92617/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev4)
URL : https://patchwork.freedesktop.org/series/92617/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d3522f0b05a8 drm/i915/gem: Check object_can_migrate from object_migrate
On 7/21/2021 11:05 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
This prints out relevant SLPC info from the SLPC shared structure.
We will send a h2g message which forces SLPC to update the
shared data structure with latest information before reading it.
v2:
On 7/21/2021 11:00 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a H2G command which forces
SLPC to update the shared data struct which can then be
read.
add note that functions
On 7/21/2021 10:42 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Add param set h2g helpers to set the min and max frequencies
for use by SLPC.
v2: Address review comments (Michal W)
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Vinay Belgaumkar
---
On 7/21/2021 10:26 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Allocate data structures for SLPC and functions for
initializing on host side.
v2: Address review comments (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_vmas to just a
slab_vmas.
We have to keep i915_drv.h include in
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_dependencies|priorities to just a
slab_dependencies|priorities.
Cc: Jason
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_objects to just a
slab_objects.
Cc: Jason Ekstrand
Signed-off-by: Daniel
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_requests|execute_cbs to just a
slab_requests|execute_cbs.
Cc: Jason
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_ce to just a
slab_ce.
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
No longer used.
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
drivers/gpu/drm/i915/i915_globals.c | 53 ---
drivers/gpu/drm/i915/i915_globals.h | 25 -
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_luts to just a
slab_luts.
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_blocks to just a
slab_blocks.
Cc: Jason Ekstrand
Signed-off-by: Daniel
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_cache to just a slab_cache.
Cc: Jason Ekstrand
Signed-off-by: Daniel
When modesetting (aka the full pci driver, which has nothing to do
with disable_display option, which just gives you the full pci driver
without the display driver) is disabled, we load nothing and do
nothing.
So move that check first, for a bit of orderliness. With Jason's
module init/exit table
On 7/21/2021 10:38 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper
On 7/21/2021 10:25 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Add constants and params that are needed to configure SLPC.
v2: Add a new abi header for SLPC. Replace bitfields with
genmasks. Address other comments from Michal W.
Signed-off-by: Vinay Belgaumkar
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
v2:
- Re-order intel_gt_info and intel_device_info slightly to avoid
unnecessary padding now that we've increased the size of
intel_engine_mask_t. (Tvrtko)
v3:
- Drop the
Hi
Am 13.07.21 um 22:51 schrieb Daniel Vetter:
tldr; DMA buffers aren't normal memory, expecting that you can use
them like that (like calling get_user_pages works, or that they're
accounting like any other normal memory) cannot be guaranteed.
Since some userspace only runs on integrated
On Fri, Jul 23, 2021 at 09:39:14AM +0200, Christoph Hellwig wrote:
> This looks unessecarily complicated. We can just try to load first
> and then store it under the same lock, e.g.:
Yes indeed, I went with this:
int vfio_assign_device_set(struct vfio_device *device, void *set_id)
{
On Fri, Jul 23, 2021 at 10:54:07AM -0700, Lucas De Marchi wrote:
> On Fri, Jul 23, 2021 at 10:42:11AM -0700, Matt Roper wrote:
> > From: John Harrison
> >
> > Xe_HP can have a lot of extra media engines. This patch adds the basic
> > definitions for them.
> >
> > v2:
> > - Re-order
== Series Details ==
Series: drm/i915: Program chicken bit during DP MST sequence on TGL+
URL : https://patchwork.freedesktop.org/series/92958/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10379 -> Patchwork_20696
Summary
On Fri, Jul 23, 2021 at 10:42:11AM -0700, Matt Roper wrote:
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
v2:
- Re-order intel_gt_info and intel_device_info slightly to avoid
unnecessary padding now that we've increased the
Are there IGTs for this anywhere?
On Fri, Jul 23, 2021 at 12:47 PM Jason Ekstrand wrote:
>
> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12044
>
> On Fri, Jul 23, 2021 at 6:35 AM Matthew Auld wrote:
> >
> > From: Chris Wilson
> >
> > Jason Ekstrand requested a more efficient
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12044
On Fri, Jul 23, 2021 at 6:35 AM Matthew Auld wrote:
>
> From: Chris Wilson
>
> Jason Ekstrand requested a more efficient method than userptr+set-domain
> to determine if the userptr object was backed by a complete set of pages
>
From: Ankit Nautiyal
Add the functions to configure HDMI2.1 pcon for DG2, before DP link
training.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
At the moment we don't have a proper algorithm that can be used to
calculate PHY settings for arbitrary HDMI link rates. The PHY tables
here should support the regular modes of real-world HDMI monitors.
Bspec: 54032
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-off-by: Vandita Kulkarni
Initialization of the PHY is handled by the hardware/firmware, but the
driver should wait up to 25ms for the PHY to report that its calibration
has completed.
Bspec: 49189
Bspec: 50107
Cc: Matt Atwood
Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
---
From: Gwan-gyeong Mun
The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.
Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Anusha Srivatsa
---
Although DG2_G10 platforms will always have all SQIDI's present and
don't need steering for registers in a SQIDI MMIO range, this isn't true
for DG2_G11 platforms; only SQIDI's 2 and 3 can be used on those.
We handle SQIDI ranges a bit differently from other types of explicit
steering. The SQIDI
DG2 has some changes to the expected modesetting sequences when compared
to gen12. Adjust our driver logic accordingly. Although the DP
sequence is pretty similar to TGL's, there are some steps that change,
so let's split the handling for that out into a separate function.
v2:
- Switch
Due to the removal of legacy slices and the transition to a
gslice/cslice/mslice/etc. design, we'll internally store all DSS under
"slice0."
Signed-off-by: Matt Roper
Reviewed-by: Caz Yokoyama
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 -
drivers/gpu/drm/i915/gt/intel_sseu.h
From: Daniele Ceraolo Spurio
Xe_HP is more modular then its predecessors and as a consequence it has
more types of replicated registers. As with l3bank regions on previous
platforms, we may need to explicitly re-steer accesses to these new
types of ranges at runtime if we can't find a single
DG2 supports compute DSS and has the same maximum number of DSS and EU
as XeHP SDV.
Signed-off-by: Matt Roper
Reviewed-by: Caz Yokoyama
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Xe_HPG adds some additional INSTDONE_GEOM debug registers; the Mesa team
has indicated that having these reported in the error state would be
useful for debugging GPU hangs. These registers are replicated per-DSS
with gslice steering.
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
Acked-by:
For tgl+, the per-context setting of MI_MODE[12] determines whether
the bits of a nested MI_BATCH_BUFFER_START instruction should be
interpreted in the traditional manner or whether they should
instead use a new tgl+ meaning that breaks backward compatibility, but
allows nesting into 3rd-level
From: Animesh Manna
In verify_mpllb_state() encoder is retrieved from best_encoder
of connector_state. As there will be only one connector_state
for bigjoiner and checking encoder may not be needed for
bigjoiner-slave. This code path related to mpll is done on dg2
and need this fix to avoid null
The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this
register is now a per-tile register at GTTMMADDR offset 0x250014.
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++-
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