On Tue, 27 Jul 2021 19:01:24 -0700, Dixit, Ashutosh wrote:
>
> On Mon, 26 Jul 2021 05:03:04 -0700, Matthew Auld wrote:
> >
> > diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> > index 4b4f2114..e2514f0c 100644
> > --- a/lib/i915/gem_mman.c
> > +++ b/lib/i915/gem_mman.c
> > @@ -497,6
== Series Details ==
Series: series starting with [1/1] drm/i915: dgfx cards need to wait on pcode's
uncore init done
URL : https://patchwork.freedesktop.org/series/93075/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10405_full -> Patchwork_20720_full
On Wed, Jul 28, 2021 at 02:29:18AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/adl_p: Allow underrun recovery when possible (rev2)
> URL : https://patchwork.freedesktop.org/series/93054/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
On 7/27/2021 8:24 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add param set h2g helpers to set the min and max frequencies
s/h2g/H2G
for use by SLPC.
v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
Signed-off-by:
== Series Details ==
Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F
workaround for CNL (rev2)
URL : https://patchwork.freedesktop.org/series/93056/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10405_full -> Patchwork_20719_full
== Series Details ==
Series: drm/i915/adl_p: Allow underrun recovery when possible (rev2)
URL : https://patchwork.freedesktop.org/series/93054/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10405_full -> Patchwork_20717_full
On Mon, 26 Jul 2021 05:03:04 -0700, Matthew Auld wrote:
>
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index 4b4f2114..e2514f0c 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -497,6 +497,43 @@ void *gem_mmap_offset__cpu(int fd, uint32_t handle,
> uint64_t
On 7/27/2021 9:00 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland.
On Tue, Jul 27, 2021 at 06:01:18PM -0700, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 5:20 PM, Matthew Brost wrote:
> > On Mon, Jul 26, 2021 at 12:07:52PM -0700, Vinay Belgaumkar wrote:
> > > The assumption when it was added was there would be no wakerefs
> > > held. However, if we fail to
On 7/27/2021 5:20 PM, Matthew Brost wrote:
On Mon, Jul 26, 2021 at 12:07:52PM -0700, Vinay Belgaumkar wrote:
The assumption when it was added was there would be no wakerefs
held. However, if we fail to enable SLPC, we will still be
holding a wakeref.
So this is if intel_guc_slpc_enable()
On Mon, Jul 26, 2021 at 12:07:52PM -0700, Vinay Belgaumkar wrote:
> The assumption when it was added was there would be no wakerefs
> held. However, if we fail to enable SLPC, we will still be
> holding a wakeref.
>
So this is if intel_guc_slpc_enable() fails, right? Not seeing where the
wakeref
On 7/27/2021 8:40 AM, Matthew Brost wrote:
On Mon, Jul 26, 2021 at 12:07:56PM -0700, Vinay Belgaumkar wrote:
This interrupt is enabled during RPS initialization, and
now needs to be done by SLPC code. It allows ARAT timer
expiry interrupts to get forwarded to GuC.
Signed-off-by: Vinay
On 7/27/2021 8:37 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
This prints out relevant SLPC info from the SLPC shared structure.
We will send a h2g message which forces SLPC to update the
s/h2g/H2G
ok.
shared data structure with latest information
On 7/27/2021 8:32 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a H2G command which forces
SLPC to update the shared data struct which can then be
read. These helpers will be used
On Wed, Jul 21, 2021 at 10:43:34PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling PSR data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> ---
>
== Series Details ==
Series: drm/i915/adlp: Add workaround to disable CMTG clock gating
URL : https://patchwork.freedesktop.org/series/93067/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10404_full -> Patchwork_20716_full
On Tue, Jul 27, 2021 at 03:48:23PM -0700, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 3:44 PM, Matthew Brost wrote:
> > On Mon, Jul 26, 2021 at 12:07:48PM -0700, Vinay Belgaumkar wrote:
> > > Also ensure uc_init is called before we initialize RPS so that we
> > > can check for SLPC support. We
On 7/27/2021 3:44 PM, Matthew Brost wrote:
On Mon, Jul 26, 2021 at 12:07:48PM -0700, Vinay Belgaumkar wrote:
Also ensure uc_init is called before we initialize RPS so that we
can check for SLPC support. We do not need to enable up/down
interrupts when SLPC is enabled. However, we still need
On Mon, Jul 26, 2021 at 12:07:48PM -0700, Vinay Belgaumkar wrote:
> Also ensure uc_init is called before we initialize RPS so that we
> can check for SLPC support. We do not need to enable up/down
> interrupts when SLPC is enabled. However, we still need the ARAT
> interrupt, which will be enabled
On 7/27/2021 8:24 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add param set h2g helpers to set the min and max frequencies
s/h2g/H2G
for use by SLPC.
v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
Signed-off-by:
On 7/27/2021 12:16 PM, Matthew Brost wrote:
On Mon, Jul 26, 2021 at 12:07:59PM -0700, Vinay Belgaumkar wrote:
Tests that exercise the SLPC get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that SLPC requests frequency lower than or equal to it.
On Tue, 2021-07-27 at 11:55 -0700, Anusha Srivatsa wrote:
> Release notes mention that this verion has:
> - Fixes for DC6v issue.
> - Flip queue enabled on pipe C and pipe D.
Reviewed-by: José Roberto de Souza
>
> Cc: Imre Deak
> Signed-off-by: Anusha Srivatsa
> ---
>
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/93066/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10404_full -> Patchwork_20715_full
On Mon, 26 Jul 2021 05:03:08 -0700, Matthew Auld wrote:
>
> We can no longer just call get_caching or set_domain, and the mmap mode
> must be FIXED. This should bring back gem_exec_basic and a few others in
> CI on DG1.
We should probably also similarly update mmap_{read, write} in
On Wed, Jul 21, 2021 at 10:43:33PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling eDP data.
>
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Atwood
> ---
>
== Series Details ==
Series: Bump DMC version on ADLP to v2.11
URL : https://patchwork.freedesktop.org/series/93081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10406 -> Patchwork_20721
Summary
---
**SUCCESS**
On 7/27/2021 1:19 PM, Michal Wajdeczko wrote:
On 27.07.2021 22:00, Belgaumkar, Vinay wrote:
On 7/27/2021 8:12 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been
On 27.07.2021 22:00, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 8:12 AM, Michal Wajdeczko wrote:
>>
>>
>> On 26.07.2021 21:07, Vinay Belgaumkar wrote:
>>> Add methods for interacting with GuC for enabling SLPC. Enable
>>> SLPC after GuC submission has been established. GuC load will
>>> fail
== Series Details ==
Series: drm/i915: Fix the 12 BPC bits for PIPE_MISC reg (rev2)
URL : https://patchwork.freedesktop.org/series/92690/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10403_full -> Patchwork_20714_full
On 7/27/2021 8:12 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper
On Tue, Jul 27, 2021 at 09:18:08AM -0700, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 8:37 AM, Matt Roper wrote:
> > On Mon, Jul 26, 2021 at 12:08:00PM -0700, Vinay Belgaumkar wrote:
> > > This feature hands over the control of HW RC6 to the GuC.
> > > GuC decides when to put HW into RC6 based
== Series Details ==
Series: series starting with [1/1] drm/i915: dgfx cards need to wait on pcode's
uncore init done
URL : https://patchwork.freedesktop.org/series/93075/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10405 -> Patchwork_20720
On 7/26/2021 17:23, Matthew Brost wrote:
Requests may take slightly longer with GuC submission, let's increase
the timeouts in live_requests.
Signed-off-by: Matthew Brost
Was already reviewed in previous series. Repeating here for patchwork:
Reviewed-by: John Harrison
---
On Mon, Jul 26, 2021 at 12:07:59PM -0700, Vinay Belgaumkar wrote:
> Tests that exercise the SLPC get/set frequency interfaces.
>
> Clamp_max will set max frequency to multiple levels and check
> that SLPC requests frequency lower than or equal to it.
>
> Clamp_min will set min frequency to
On 7/26/2021 5:23 PM, Matthew Brost wrote:
This adds GuC backend support for i915_request_cancel(), which in turn
makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
This implementation makes use of fence while there are likely simplier
options. A fence was chosen because of another feature coming
On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> Xe_HP is more modular then its predecessors and as a consequence it
then -> than
> has
> more types of replicated registers. As with l3bank regions on
> previous
> platforms, we may need to explicitly
On 7/27/2021 6:59 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add constants and params that are needed to configure SLPC.
v2: Add a new abi header for SLPC. Replace bitfields with
genmasks. Address other comments from Michal W.
v3: Add slpc H2G format in abi,
On Tue, 2021-07-27 at 11:38 -0700, Matt Roper wrote:
> On Tue, Jul 27, 2021 at 11:34:28AM -0700, Yokoyama, Caz wrote:
> > On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> > > During a rebase the parameters were partially renamed, but not
> > > completely. Since the subsequent patches that
Adding PR for CI to pickthe firmware:
The following changes since commit 168452ee695b5edb9deb641059bc110b9c5e8fc7:
Merge tag 'iwlwifi-fw-2021-07-19' of
git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/linux-firmware into main
(2021-07-19 14:35:47 -0400)
are available in the Git
Release notes mention that this verion has:
- Fixes for DC6v issue.
- Flip queue enabled on pipe C and pipe D.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 7/27/2021 6:43 AM, Michal Wajdeczko wrote:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
Add macros to check for SLPC support. This feature is currently supported
for Gen12+ and enabled whenever GuC submission is enabled/selected.
Include templates for SLPC init/fini and enable.
v2:
On 7/27/2021 02:49, Daniel Vetter wrote:
On Mon, Jul 26, 2021 at 07:21:43PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
Various UMDs require hardware configuration information about the
current platform. A bunch of static information is available in a
fixed table that can be
On Tue, Jul 27, 2021 at 11:34:28AM -0700, Yokoyama, Caz wrote:
> On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> > During a rebase the parameters were partially renamed, but not
> > completely. Since the subsequent patches that start using this macro
> > haven't landed on an upstream tree
On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> During a rebase the parameters were partially renamed, but not
> completely. Since the subsequent patches that start using this macro
> haven't landed on an upstream tree yet this didn't cause a build
> failure.
>
> Fixes: 086df54e20be
On Tue, Jul 27, 2021 at 09:56:06AM +0100, Tvrtko Ursulin wrote:
>
> On 26/07/2021 23:48, Matthew Brost wrote:
> > On Thu, Jul 15, 2021 at 10:36:51AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 24/06/2021 08:05, Matthew Brost wrote:
> > > > Reset implementation for new GuC interface. This is the
On Tue, Jul 27, 2021 at 9:44 AM Tvrtko Ursulin
wrote:
>
>
> On 27/07/2021 13:10, Daniel Vetter wrote:
> > The module init code is somewhat misplaced in i915_pci.c, since it
> > needs to pull in init/exit functions from every part of the driver and
> > pollutes the include list a lot.
> >
> >
== Series Details ==
Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F
workaround for CNL (rev2)
URL : https://patchwork.freedesktop.org/series/93056/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10405 -> Patchwork_20719
Patch should explain it all. Will include in [1] when that series is
respun.
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/93071/
Matthew Brost (1):
i915/gem_scheduler: Ensure submission order in manycontexts
tests/i915/gem_exec_schedule.c | 16 +++-
With GuC submission contexts can get reordered (compared to submission
order), if contexts get reordered the sequential nature of the batches
releasing the next batch's semaphore in function timesliceN() get broken
resulting in the test taking much longer than if should. e.g. Every
contexts needs
== Series Details ==
Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F
workaround for CNL (rev2)
URL : https://patchwork.freedesktop.org/series/93056/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit
== Series Details ==
Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F
workaround for CNL (rev2)
URL : https://patchwork.freedesktop.org/series/93056/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a5e4bffd6d6f drm/i915/display: remove PORT_F workaround
== Series Details ==
Series: drm/i915/adl_p: Allow underrun recovery when possible (rev2)
URL : https://patchwork.freedesktop.org/series/93054/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10405 -> Patchwork_20717
Summary
== Series Details ==
Series: drm, drm/vmwgfx: fixes and updates related to drm_master (rev2)
URL : https://patchwork.freedesktop.org/series/92894/
State : failure
== Summary ==
CC arch/x86/kernel/asm-offsets.s
In file included from ./arch/x86/include/asm/bug.h:84,
from
From: Badal Nilawar
In discrete cards, the graphics driver shouldn't proceed with the probe
or resume unless PCODE indicated everything is done, including memory
training and gt bring up.
For this reason, the driver probe and resume paths needs to be blocked
until PCODE indicates it is done.
On Tue, 2021-07-27 at 16:44 +0300, Imre Deak wrote:
> The driver doesn't depend atm on the common mode timing generator
> functionality (it would be used for some power saving feature and panel
> timing synchronization), however DMC will corrupt the CMTG registers
> across DC5 entry/exit sequences
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Update the get/set min/max freq hooks to work for
> SLPC case as well. Consolidate helpers for requested/min/max
> frequency get/set to intel_rps where the proper action can
> be taken depending on whether SLPC is enabled.
>
> v2: Add wrappers for
The numbers of scalers and sprites depend on the display version, so use
it instead of GRAPHICS_VER. We were mixing both, which let me confused
while removing CNL and GRAPHICS_VER == 10.
v2 (Rodrigo): Switch IS_GEMINILAKE to DISPLAY_VER == 10
v3 (Lucas): Change check to DISPLAY_VER >= 9, to cover
On 7/27/2021 8:37 AM, Matt Roper wrote:
On Mon, Jul 26, 2021 at 12:08:00PM -0700, Vinay Belgaumkar wrote:
This feature hands over the control of HW RC6 to the GuC.
GuC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GUCRC needs GuC submission to be enabled, and
On Thu, Jul 22, 2021 at 01:26:36PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> > https://github.com/intel/gvt-linux/blob/topic/gvt-xengt/drivers/gpu/drm/i915/gvt/xengt.c
>
> > But it's hard for some customers to contribute their own "hypervisor"
> > module to the upstream Linux kernel. I am thinking
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Cache rp0, rp1 and rpn platform limits into SLPC structure
> for range checking while setting min/max frequencies.
>
> Also add "soft" limits which keep track of frequency changes
> made from userland. These are initially set to platform min
> and
On Mon, Jul 26, 2021 at 12:07:56PM -0700, Vinay Belgaumkar wrote:
> This interrupt is enabled during RPS initialization, and
> now needs to be done by SLPC code. It allows ARAT timer
> expiry interrupts to get forwarded to GuC.
>
> Signed-off-by: Vinay Belgaumkar
> ---
>
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> This prints out relevant SLPC info from the SLPC shared structure.
>
> We will send a h2g message which forces SLPC to update the
s/h2g/H2G
> shared data structure with latest information before reading it.
>
> v2: Address review comments
On Mon, Jul 26, 2021 at 12:08:00PM -0700, Vinay Belgaumkar wrote:
> This feature hands over the control of HW RC6 to the GuC.
> GuC decides when to put HW into RC6 based on it's internal
> busyness algorithms.
>
> GUCRC needs GuC submission to be enabled, and only
> supported on Gen12+ for now.
>
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add helpers to read the min/max frequency being used
> by SLPC. This is done by send a H2G command which forces
> SLPC to update the shared data struct which can then be
> read. These helpers will be used in a sysfs patch later
> on.
>
> v2:
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add param set h2g helpers to set the min and max frequencies
s/h2g/H2G
> for use by SLPC.
>
> v2: Address review comments (Michal W)
> v3: Check for positive error code (Michal W)
>
> Signed-off-by: Sundaresan Sujaritha
> Signed-off-by: Vinay
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add methods for interacting with GuC for enabling SLPC. Enable
> SLPC after GuC submission has been established. GuC load will
> fail if SLPC cannot be successfully initialized. Add various
> helper methods to set/unset the parameters for SLPC.
== Series Details ==
Series: drm/i915/adlp: Add workaround to disable CMTG clock gating
URL : https://patchwork.freedesktop.org/series/93067/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10404 -> Patchwork_20716
Summary
IGT updates for GuC submission [1] and parallel submission (aka multi-bb
execbuf) [2]. This entails adding tests for parallel submission and
teaching IGTs to know of static priority mapping.
More IGTs likely need to be updated gem_ctx_persistence and i915_hangman
come to mind. Expect following
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 332c07e3d..0c023a52d 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -572,6
The i915 currently has 2k visible priority levels which are currently
unique. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_scheduler to understand this. This entails updating promotion
test to use 3 levels that will map into different
Add basic parallel execbuf submission test which more or less just
submits the same BB in loop a which does an atomic increment to a memory
location. The memory location is checked at the end for the correct
value. Different sections use various IOCTL options (e.g. fences,
location of BBs,
Signed-off-by: Matthew Brost
---
lib/intel_ctx.c | 28 +++-
lib/intel_ctx.h | 2 ++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
index f28c15544..11ec6fca4 100644
--- a/lib/intel_ctx.c
+++ b/lib/intel_ctx.c
@@ -83,6
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 128
1 file changed, 128 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index a1c0030c3..3c1aac348 100644
--- a/include/drm-uapi/i915_drm.h
+++
The i915 currently has 2k visible priority levels which are currently
unique. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_scheduler to understand this. This entails updating promotion
test to use 3 levels that will map into different
v2:
(CI)
- Fix off by 1 error in size of reserved fields
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 3c1aac348..332c07e3d 100644
---
On Thu, Jul 22, 2021 at 12:38:10PM +0200, Daniel Vetter wrote:
> On Thu, Jul 22, 2021 at 05:29:27PM +0800, Desmond Cheong Zhi Xi wrote:
> > Inside drm_is_current_master, using the outer drm_device.master_mutex
> > to protect reads of drm_file.master makes the function prone to creating
> > lock
ADL_P requires that we disable underrun recovery when downscaling (or
using the scaler for YUV420 pipe output), using DSC, or using PSR2.
Otherwise we should be able to enable the underrun recovery.
On DG2 we need to keep underrun recovery disabled at all times, but the
chicken bit in
On 07/12, Daniel Vetter wrote:
> Hi all,
>
> Quick new version since the previous one was a bit too broken:
> - dropped the bug-on patch to avoid breaking amdgpu's gpu reset failure
> games
> - another attempt at splitting job_init/arm, hopefully we're getting
> there.
>
> Note that
On 27/07/2021 13:10, Daniel Vetter wrote:
The module init code is somewhat misplaced in i915_pci.c, since it
needs to pull in init/exit functions from every part of the driver and
pollutes the include list a lot.
Extract an i915_module.c file which pulls all the bits together, and
allows us to
== Series Details ==
Series: drm/i915/adlp: Add workaround to disable CMTG clock gating
URL : https://patchwork.freedesktop.org/series/93067/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9cf8974d9e83 drm/i915/adlp: Add workaround to disable CMTG clock gating
-:34:
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/93066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10404 -> Patchwork_20715
Looks good to me.
Reviewed-by: Gwan-gyeong Mun
On 7/26/21 9:15 PM, José Roberto de Souza wrote:
HDMI and DisplayPort sequences states that audio and PSR should be
disabled before planes are disabled.
Not following it did not caused any problems up to Alderlake-P but
for this platform it
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/93066/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [v2,01/11] drm/i915: Check for nomodeset in
i915_init() first
URL : https://patchwork.freedesktop.org/series/93066/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
526b1246de6a drm/i915: Check for nomodeset in i915_init() first
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Allocate data structures for SLPC and functions for
> initializing on host side.
>
> v2: Address review comments (Michal W)
> v3: Remove unnecessary header includes (Michal W)
>
> Signed-off-by: Vinay Belgaumkar
> Signed-off-by: Sundaresan
On Thu, Jul 22, 2021 at 11:20 AM Sean Paul wrote:
>
Reply-all fail. Adding everyone else back to my response.
> On Tue, Jul 20, 2021 at 03:29:34PM +0200, Daniel Vetter wrote:
> > On Wed, Jul 14, 2021 at 11:51:36AM -0600, Jim Cromie wrote:
> > > drm's debug system uses distinct categories of
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add constants and params that are needed to configure SLPC.
>
> v2: Add a new abi header for SLPC. Replace bitfields with
> genmasks. Address other comments from Michal W.
>
> v3: Add slpc H2G format in abi, other review commments (Michal W)
>
>
On Tue, Jul 20, 2021 at 03:29:34PM +0200, Daniel Vetter wrote:
> On Wed, Jul 14, 2021 at 11:51:36AM -0600, Jim Cromie wrote:
> > drm's debug system uses distinct categories of debug messages, encoded
> > in an enum (DRM_UT_), which are mapped to bits in drm.debug.
> > drm_debug_enabled() does a
== Series Details ==
Series: series starting with [CI,01/28] drm/i915/display: remove PORT_F
workaround for CNL
URL : https://patchwork.freedesktop.org/series/93056/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10399_full -> Patchwork_20713_full
The driver doesn't depend atm on the common mode timing generator
functionality (it would be used for some power saving feature and panel
timing synchronization), however DMC will corrupt the CMTG registers
across DC5 entry/exit sequences unless the CMTG clock gating is
disabled. This in turn can
On 26.07.2021 21:07, Vinay Belgaumkar wrote:
> Add macros to check for SLPC support. This feature is currently supported
> for Gen12+ and enabled whenever GuC submission is enabled/selected.
>
> Include templates for SLPC init/fini and enable.
>
> v2: Move SLPC helper functions to
== Series Details ==
Series: drm/i915: Fix the 12 BPC bits for PIPE_MISC reg (rev2)
URL : https://patchwork.freedesktop.org/series/92690/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10403 -> Patchwork_20714
Summary
On Sat, Jul 24, 2021 at 07:18:22PM +0800, Desmond Cheong Zhi Xi wrote:
> Inside drm_is_current_master, using the outer drm_device.master_mutex
> to protect reads of drm_file.master makes the function prone to creating
> lock hierarchy inversions. Instead, we can use the
>
On Sat, Jul 24, 2021 at 07:18:23PM +0800, Desmond Cheong Zhi Xi wrote:
> We make the following changes to the documentation of drm leases to
> make it easier to reason about their usage. In particular, we clarify
> the lifetime and locking rules of lease fields in drm_master:
>
> 1. Make it clear
The module init code is somewhat misplaced in i915_pci.c, since it
needs to pull in init/exit functions from every part of the driver and
pollutes the include list a lot.
Extract an i915_module.c file which pulls all the bits together, and
allows us to massively trim the include list of
No longer used.
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
drivers/gpu/drm/i915/i915_globals.c | 53 ---
drivers/gpu/drm/i915/i915_globals.h | 25 -
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_vmas to just a
slab_vmas.
We have to keep i915_drv.h include in
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_requests|execute_cbs to just a
slab_requests|execute_cbs.
v2: Make slab
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_objects to just a
slab_objects.
v2: Make slab static (Jason, 0day)
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_dependencies|priorities to just a
slab_dependencies|priorities.
v2: Make
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