onfig-a006-20210822 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/d75ce0657c5bed32b206ab0461ea42eea7514436
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags li
== Series Details ==
Series: Fix in max source calculation for dp/edp (rev2)
URL : https://patchwork.freedesktop.org/series/93622/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10506 -> Patchwork_20870
Summary
---
**
== Series Details ==
Series: Enable mipi dsi on XELPD (rev2)
URL : https://patchwork.freedesktop.org/series/93917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10506_full -> Patchwork_20869_full
Summary
---
**SUCCES
On Mon, Aug 23, 2021 at 1:21 AM Jim Cromie wrote:
>
> DEFINE_DYNAMIC_DEBUG_CATEGORIES(name, var, bitmap_desc, @bit_descs)
> allows users to define a drm.debug style (bitmap) sysfs interface, and
> to specify the desired mapping from bits[0-N] to the format-prefix'd
> pr_debug()s to be controlled.
== Series Details ==
Series: Fix in max source calculation for dp/edp (rev2)
URL : https://patchwork.freedesktop.org/series/93622/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b4ce1a67c5b8 drm/i915/dp: Fix eDP max rate for display 11+
-:20: ERROR:GIT_COMMIT_ID: Please use git
Now, this change and changes from patch 51 of this series is taken care as part
of the below series
https://patchwork.freedesktop.org/series/92750/
and merged.
Thanks,
Vandita
> -Original Message-
> From: Jani Nikula
> Sent: Friday, July 2, 2021 1:50 PM
> To: Roper, Matthew D ; intel-
>
== Series Details ==
Series: Enable mipi dsi on XELPD (rev2)
URL : https://patchwork.freedesktop.org/series/93917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10506 -> Patchwork_20869
Summary
---
**SUCCESS**
No
== Series Details ==
Series: Enable mipi dsi on XELPD (rev2)
URL : https://patchwork.freedesktop.org/series/93917/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gem/i915_gem
Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband"
field to account for the repeaters on the HS Request/Ready PPI signaling
between the Display engine and the DPHY.
v2: Fix build issue.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 25 +
== Series Details ==
Series: Enable mipi dsi on XELPD
URL : https://patchwork.freedesktop.org/series/93917/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm
Enable MIPI DSI support on ADL-P platform.
The esc clock changes, WA changes are taken care
in the previous patches.
As per the Bspec the seq remains to be same as TGL.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --
Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband"
field to account for the repeaters on the HS Request/Ready PPI signaling
between the Display engine and the DPHY.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 24
drive
The delta from TGL is wrt the ESC clock, and an additional
WA needed. With that support in place, extend the support
for mipi dsi.
Vandita Kulkarni (2):
drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband
drm/i915/dsi/xelpd: Enable mipi dsi support.
drivers/gpu/drm/i915/display/i
== Series Details ==
Series: drm/i915: switch from 'pci_' to 'dma_' API
URL : https://patchwork.freedesktop.org/series/93911/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10505_full -> Patchwork_20866_full
Summary
---
== Series Details ==
Series: drm/amdgpu: switch from 'pci_' to 'dma_' API
URL : https://patchwork.freedesktop.org/series/93906/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10505_full -> Patchwork_20865_full
Summary
--
== Series Details ==
Series: use DYNAMIC_DEBUG to implement DRM.debug
URL : https://patchwork.freedesktop.org/series/93914/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR
== Series Details ==
Series: drm/i915: switch from 'pci_' to 'dma_' API
URL : https://patchwork.freedesktop.org/series/93911/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10505 -> Patchwork_20866
Summary
---
**SUCCE
== Series Details ==
Series: drm/amdgpu: switch from 'pci_' to 'dma_' API
URL : https://patchwork.freedesktop.org/series/93906/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10505 -> Patchwork_20865
Summary
---
**SUC
drm's debug system writes 10 distinct categories of messages to syslog
using a small API[1]: drm_dbg*(10 names), DRM_DEBUG*(8 names),
DRM_DEV_DEBUG*(3 names). There are thousands of these callsites, each
categorized by their authors.
These callsites can be enabled at runtime by their category, ea
Its tautological that having pr_debug()s with optional print-once and
rate-limiting features could be useful. Build it, they will come.
The advantages:
- dynamically configured with flags
- can use them on existing callsites
- printonce is easy, (almost) just new flags
no additional resources
There are blocks of DRM_DEBUG calls, consolidate their args into
single calls. With dynamic-debug in use, each callsite consumes 56
bytes of ro callsite data, and this patch removes about 65 calls, so
it saves ~3.5kb.
no functional changes.
RFC: this creates multi-line log messages, does that br
logger_types.h defines many DC_LOG_*() categorized debug wrappers.
Most of these use DRM debug API, so are controllable using drm.debug,
but others use bare pr_debug("$prefix: .."), each with a different
class-prefix matching "^\[\w+\]:"
Use DEFINE_DYNAMIC_DEBUG_CATEGORIES to create a /sys debug_d
Sean Paul seanp...@chromium.org proposed, in
https://patchwork.freedesktop.org/series/78133/
drm/trace: Mirror DRM debug logs to tracefs
That patchset's objective is to be able to independently steer some of
the debug stream to an alternate tracing destination, by splitting
drm_debug_enabled() int
With DRM_USE_DYNAMIC_DEBUG, each callsite record requires 56 bytes.
We can combine 12 into one here and save ~620 bytes.
Signed-off-by: Jim Cromie
---
---
drivers/gpu/drm/nouveau/nouveau_drm.c | 36 +--
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/drive
Duplicate drm_debug_enabled() code into both "basic" and "dyndbg"
ifdef branches. Then add a pr_debug("todo: ...") into the "dyndbg"
branch.
Then convert the "dyndbg" branch's code to a macro, so that its
pr_debug() get its callsite info from the invoking function, instead
of from drm_debug_enabl
Taking embedded spaces out of existing prefixes makes them better
class-prefixes; simplifying the nested quoting needed otherwise:
$> echo "format '^gvt: core:' +p" >control
Dropping the internal spaces means any trailing space in a query will
more clearly terminate the prefix being searched fo
The gvt component of this driver has ~120 pr_debugs, in 9 categories
quite similar to those in DRM. Following the interface model of
drm.debug, add a parameter to map bits to these categorizations.
DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,
"dyndbg bitmap desc",
{ "gv
DEFINE_DYNAMIC_DEBUG_CATEGORIES(name, var, bitmap_desc, @bit_descs)
allows users to define a drm.debug style (bitmap) sysfs interface, and
to specify the desired mapping from bits[0-N] to the format-prefix'd
pr_debug()s to be controlled.
DEFINE_DYNAMIC_DEBUG_CATEGORIES(debug_gvt, __gvt_debug,
Add a const void* data member to the struct, to allow attaching
private data that will be used soon by a setter method (via kp->data)
to perform more elaborate actions.
To attach the data at compile time, add new macros:
module_param_cb_data() derives from module_param_cb(), adding data
param, an
This patchset does 3 main things.
Adds DEFINE_DYNAMIC_DEBUG_CATEGORIES to define bitmap => category
control of pr_debugs, and to create their sysfs entries.
Uses it in amdgpu, i915 to control existing pr_debugs according to
their ad-hoc categorizations.
Plugs dyndbg into drm-debug framework, in
The wrappers in include/linux/pci-dma-compat.h should go away.
The patch has been generated with the coccinelle script below.
It has been compile tested.
@@
@@
-PCI_DMA_BIDIRECTIONAL
+DMA_BIDIRECTIONAL
@@
@@
-PCI_DMA_TODEVICE
+DMA_TO_DEVICE
@@
@@
-PCI_DMA_FROMDEVICE
+DM
The wrappers in include/linux/pci-dma-compat.h should go away.
The patch has been generated with the coccinelle script below.
It has been compile tested.
@@
@@
-PCI_DMA_BIDIRECTIONAL
+DMA_BIDIRECTIONAL
@@
@@
-PCI_DMA_TODEVICE
+DMA_TO_DEVICE
@@
@@
-PCI_DMA_FROMDEVICE
+DM
== Series Details ==
Series: drm/i915/lmem: Enable device memory support for DG2
URL : https://patchwork.freedesktop.org/series/93904/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10505_full -> Patchwork_20864_full
Summary
== Series Details ==
Series: drm/i915/lmem: Enable device memory support for DG2
URL : https://patchwork.freedesktop.org/series/93904/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10505 -> Patchwork_20864
Summary
---
== Series Details ==
Series: drm/i915/lmem: Enable device memory support for DG2
URL : https://patchwork.freedesktop.org/series/93904/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/d
== Series Details ==
Series: drm/i915/lmem: Enable device memory support for DG2
URL : https://patchwork.freedesktop.org/series/93904/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d96ba2006a6a drm/i915: Add has_64k_pages flag
6ba41b6b2c87 drm/i915/xehpsdv: set min page-size to
From: Matthew Auld
The basic idea is that each 2M block(page-table) has a color, depending
on if the page-table is occupied by LMEM objects(64K) or SMEM
objects(4K), where our goal is to prevent mixing 64K and 4K GTT pages in
the page-table, which is not supported by the HW.
Signed-off-by: Matth
Gen12.5 >= devices support Flat CCS which reserved a portion of the device
memory to store compression metadata, during the clearing of device memory
buffer object we also need to clear the associated CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Address of CCS buffer associated
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
Cc: Matthew Auld
Signe
From: CQ Tang
Gen12>= devices support 3D surface (buffer) compression and various
compression formats. This is accomplished by an additional compression
control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of memory. It is
From: Matthew Auld
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.
Signed-off-by: Matthew Auld
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/selftests
From: Bommu Krishnaiah
Replace the hard coded 4K alignment value with vm->min_alignment.
Cc: Wilson Chris P
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Ayaz A Siddiqui
---
.../i915/gem/selftests/i915_gem_client_blt.c | 23 ---
drivers/gpu/drm/i915/gt/intel_gtt.c
From: Matthew Auld
XEHPSDV optimises 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no longer sup
From: Matthew Auld
On some platforms the hw has dropped support for 4K GTT pages when
dealing with LMEM, and due to the design of 64K GTT pages in the hw, we
can only mark the *entire* page-table as operating in 64K GTT mode,
since the enable bit is still on the pde, and not the pte. And since we
Removing extern declaration of i915_gem_lmem_obj_ops
from i915_gem_lmem.h.
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index 4
From: Matthew Auld
If the device needs 64K minimum GTT pages for device local-memory,
like on XEHPSDV, then we need to fail the allocation if we can't
meet it, instead of falling back to 4K pages, otherwise we can't
safely support the insertion of device local-memory pages for
this vm, since the
From: Matthew Auld
For local-memory objects we need to align the GTT addresses to 64K, both
for the ppgtt and ggtt.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_vma.c | 9 +++--
1 file changed, 7 insertions(
From: Matthew Auld
LMEM should be allocated at 64K granularity, since 4K page support will
eventually be dropped for LMEM when using the PPGTT.
Signed-off-by: Matthew Auld
Signed-off-by: Stuart Summers
Signed-off-by: Ayaz A Siddiqui
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/
From: Stuart Summers
Add a new platform flag, has_64k_pages, for platforms supporting
base page sizes of 64k.
Signed-off-by: Stuart Summers
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915
There are few changes for device memory in Gen12.5+ platforms.
1. Minimum page size has been changed to 64KB.
2. Compression control state (CCS) moved from user-space manages
AUX page tables to flat indexed region of memory. This Flat index
memory is referred as Flat CCS.
3. Due to different page
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