== Series Details ==
Series: drm/i915/ttm: Async migration (rev10)
URL : https://patchwork.freedesktop.org/series/96798/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10917 -> Patchwork_21666
Summary
---
**SUCCESS**
On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> Hi Stanislav,
>
> Are there IGT tests for this modifier?
Hi Nanley
Yes, there should be plenty of those, not sure they
are all sent to upstream though.
We have a separate team doing this.
That modifier should be added to kms_plane_m
On Mon, 22 Nov 2021 15:42:38 -0700
jim.cro...@gmail.com wrote:
> On Mon, Nov 22, 2021 at 2:02 AM Pekka Paalanen wrote:
> >
> > On Fri, 19 Nov 2021 11:21:36 -0500
> > Jason Baron wrote:
> >
> > > On 11/18/21 10:24 AM, Pekka Paalanen wrote:
> > > > On Thu, 18 Nov 2021 09:29:27 -0500
> > > > Ja
On Fri, Nov 19, 2021 at 03:13:44PM +0200, Mika Kahola wrote:
> For CD clock squashing method, we need to define corresponding CD clock table
> for
> reference clocks, dividers and ratios for all CD clock options.
>
> BSpec: 54034
>
> v2: Add CD squashing waveforms as part of CD clock table (Vill
On Fri, Nov 19, 2021 at 03:13:45PM +0200, Mika Kahola wrote:
> In case of CD clock squashing the divider is always 1. We don't
> need to calculate the divider in use so let's skip that for DG2.
>
> v2: Drop unnecessary local variable (Ville)
> v3: Avoid if-else structure (Ville)
> [v4: vsyrjala: F
On Fri, Nov 19, 2021 at 03:13:46PM +0200, Mika Kahola wrote:
> Set CD clock squashing registers based on selected CD clock.
>
> v2: use slk_cdclk_decimal() to compute decimal values instead of a
> specific table (Ville)
> Set waveform based on CD clock table (Ville)
> Drop unnecessary
On Fri, Nov 19, 2021 at 03:13:47PM +0200, Mika Kahola wrote:
> To calculate CD clock with squasher unit, we set CD clock ratio to fixed
> value of 34.
> The CD clock value is read from CD clock squasher table.
>
> BSpec: 54034
>
> v2: Read ratio from register (Ville)
> Drop unnecessary local
On 22/11/2021 23:39, Umesh Nerlige Ramappa wrote:
On Mon, Nov 22, 2021 at 03:44:29PM +, Tvrtko Ursulin wrote:
On 11/11/2021 16:48, Umesh Nerlige Ramappa wrote:
On Thu, Nov 11, 2021 at 02:37:43PM +, Tvrtko Ursulin wrote:
On 04/11/2021 22:04, Umesh Nerlige Ramappa wrote:
On Thu, Nov
On 22/11/2021 18:44, Rodrigo Vivi wrote:
On Wed, Nov 17, 2021 at 02:49:55PM -0800, Vinay Belgaumkar wrote:
From: Chris Wilson
While the power consumption is proportional to the frequency, there is
also a static draw for active gates. The longer we are able to powergate
(rc6), the lower the s
On 23/11/2021 05:09, Randy Dunlap wrote:
Correct kernel-doc warnings in i915_drm_object.c:
i915_gem_object.c:103: warning: expecting prototype for i915_gem_object_fini().
Prototype was for __i915_gem_object_fini() instead
i915_gem_object.c:110: warning: This comment starts with '/**', but isn't
First off, let me reiterate that this feature would be invaluable as user-space
developers. It's often pretty difficult to figure out the cause of an EINVAL,
we have to ask users to follow complicated instructions [1] to grab DRM logs.
Then have to skim through several megabytes of logs to find the
On 17/11/2021 22:49, Vinay Belgaumkar wrote:
From: Chris Wilson
Everytime we come to the end of a virtual engine's context, re-randomise
it's siblings[]. As we schedule the siblings' tasklets in the order they
are in the array, earlier entries are executed first (when idle) and so
will be pre
== Series Details ==
Series: drm/i915/ttm: Async migration (rev10)
URL : https://patchwork.freedesktop.org/series/96798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10917_full -> Patchwork_21666_full
Summary
---
**
On Tue, 23 Nov 2021 at 05:56, Patchwork
wrote:
> *Patch Details*
> *Series:* drm/i915/gem: placate scripts/kernel-doc
> *URL:* https://patchwork.freedesktop.org/series/97190/
> *State:* failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21664/index.html CI
> Bug Log - chang
On 22/11/2021 19:13, Zbigniew Kempczyński wrote:
In short - we want to enforce alignment == 0 for gen4+ GEM object
settings.
Before we merge this we need to inspect all UMD we expect can use
this. My investigation was narrowed to UMD code:
1. IGT
2. Mesa
3. Media-Driver
4. NEO
5. libdrm
6. xf
== Series Details ==
Series: drm/i915/pxp: Trybot - run CI with PXP and MEI_PXP enabled (rev2)
URL : https://patchwork.freedesktop.org/series/97145/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10917 -> Patchwork_21667
Sum
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Tuesday, November 23, 2021 3:14 AM
> To: Nanley Chery
> Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G
>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
>
> On Mon, Nov 22, 2021 at 05:08:31PM
== Series Details ==
Series: drm/i915/pxp: Trybot - run CI with PXP and MEI_PXP enabled (rev2)
URL : https://patchwork.freedesktop.org/series/97145/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10917_full -> Patchwork_21667_full
===
drm-intel-gt-next fails to build with:
drivers/gpu/drm/i915/gem/i915_gem_ttm.c: In function ‘vm_fault_ttm’:
drivers/gpu/drm/i915/gem/i915_gem_ttm.c:862:23: error: too many arguments to
function ‘ttm_bo_vm_fault_reserved’
862 | ret = ttm_bo_vm_fault_reserved(vmf,
vmf->vma->vm_pa
== Series Details ==
Series: drm/i915/ttm: fixup build failure
URL : https://patchwork.freedesktop.org/series/97205/
State : failure
== Summary ==
Applying: drm/i915/ttm: fixup build failure
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gem/i915_gem_ttm.c
Falling
On Tue, Nov 23, 2021 at 02:41:20PM +0200, Chery, Nanley G wrote:
>
>
> > -Original Message-
> > From: Lisovskiy, Stanislav
> > Sent: Tuesday, November 23, 2021 3:14 AM
> > To: Nanley Chery
> > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G
> >
> > Subject: Re: [Intel-gfx] [PATCH]
On 21-11-20 07:26:02, Jakub Kicinski wrote:
> On Sat, 20 Nov 2021 15:30:11 +0800 Peter Chen wrote:
> > > diff --git a/drivers/usb/cdns3/host.c b/drivers/usb/cdns3/host.c
> > > index 84dadfa726aa..9643b905e2d8 100644
> > > --- a/drivers/usb/cdns3/host.c
> > > +++ b/drivers/usb/cdns3/host.c
> > > @@
Hi Daniele,
I'll give it a whirl on my laptop. Thanks.
Jason
From: raviteja goud talla
Bspec page says "Reset: BUS", Accordingly moving w/a's:
Wa_1407352427,Wa_1406680159 to proper function icl_gt_workarounds_init()
Which will resolve guc enabling error
Cc: John Harrison
Signed-off-by: raviteja goud talla
---
drivers/gpu/drm/i915/gt/intel_workarounds.c
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Tuesday, November 23, 2021 8:37 AM
> To: Chery, Nanley G
> Cc: Nanley Chery ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
>
> On Tue, Nov 23, 2021 at 02:41:20PM +
== Series Details ==
Series: drm/i915/gen11: Moving WAs to icl_gt_workarounds_init()
URL : https://patchwork.freedesktop.org/series/97208/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8a0b3247925b drm/i915/gen11: Moving WAs to icl_gt_workarounds_init()
-:23: CHECK:PARENTHESIS_
On Tue, Nov 23, 2021 at 05:06:22PM +0200, Chery, Nanley G wrote:
>
>
> > -Original Message-
> > From: Lisovskiy, Stanislav
> > Sent: Tuesday, November 23, 2021 8:37 AM
> > To: Chery, Nanley G
> > Cc: Nanley Chery ; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm
== Series Details ==
Series: drm/i915/gen11: Moving WAs to icl_gt_workarounds_init()
URL : https://patchwork.freedesktop.org/series/97208/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10917 -> Patchwork_21669
Summary
-
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Tuesday, November 23, 2021 10:23 AM
> To: Chery, Nanley G
> Cc: intel-gfx@lists.freedesktop.org; Deak, Imre
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
>
> On Tue, Nov 23, 2021 at 05:06:22PM +0
On Mon, Nov 22, 2021 at 05:08:31PM -0500, Nanley Chery wrote:
> Hi Stanislav,
>
> Are there IGT tests for this modifier?
>
> On Mon, Nov 22, 2021 at 4:14 PM Stanislav Lisovskiy
> wrote:
> >
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for l
On Tue, 2021-11-23 at 09:17 +, Tvrtko Ursulin wrote:
>
> On 22/11/2021 18:44, Rodrigo Vivi wrote:
> > On Wed, Nov 17, 2021 at 02:49:55PM -0800, Vinay Belgaumkar wrote:
> > > From: Chris Wilson
> > >
> > > While the power consumption is proportional to the frequency,
> > > there is
> > > also
== Series Details ==
Series: drm/i915/gen11: Moving WAs to icl_gt_workarounds_init()
URL : https://patchwork.freedesktop.org/series/97208/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10917_full -> Patchwork_21669_full
Sum
== Series Details ==
Series: drm/i915/gem: placate scripts/kernel-doc
URL : https://patchwork.freedesktop.org/series/97190/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10917 -> Patchwork_21664
Summary
---
**SUCCESS
This failure is related to
https://gitlab.freedesktop.org/drm/intel/-/issues/4547
Few tests - fail - This test was killed due to a kernel taint, INFO: task
kworker/.* blocked for more than 30 seconds.
Re-reproted.
Thanks,
Lakshmi.
From: Matthew Auld
Sent: Tuesday, November 23, 2021 1:45 AM
To:
On 11/17/2021 2:49 PM, Vinay Belgaumkar wrote:
From: Chris Wilson
Currently, we inspect each engine individually and measure the occupancy
of that engine over the last evaluation interval. If that exceeds our
busyness thresholds, we decide to increase the GPU frequency. However,
under a load
On 11/17/2021 2:49 PM, Vinay Belgaumkar wrote:
From: Chris Wilson
While the power consumption is proportional to the frequency, there is
also a static draw for active gates. The longer we are able to powergate
(rc6), the lower the static draw. Thus there is a sweetspot in the
frequency/power
On Fri, Nov 19, 2021 at 12:37 PM Alejandro Colomar
wrote:
>
> Signed-off-by: Alejandro Colomar
> Cc: Ajit Khaparde
> Cc: Andrew Morton
> Cc: Andy Shevchenko
> Cc: Arnd Bergmann
> Cc: Bjorn Andersson
> Cc: Borislav Petkov
> Cc: Corey Minyard
> Cc: Chris Mason
> Cc: Christian Brauner
> Cc:
On 23/11/2021 12:58, Matthew Auld wrote:
drm-intel-gt-next fails to build with:
drivers/gpu/drm/i915/gem/i915_gem_ttm.c: In function ‘vm_fault_ttm’:
drivers/gpu/drm/i915/gem/i915_gem_ttm.c:862:23: error: too many arguments to
function ‘ttm_bo_vm_fault_reserved’
862 | ret =
== Series Details ==
Series: drm/i915/gem: placate scripts/kernel-doc
URL : https://patchwork.freedesktop.org/series/97190/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10917_full -> Patchwork_21664_full
Summary
---
Enable pipe color support for Display 13 platform. This series
enables just the 10bit gamma mode. More advanced logarithmic
gamma mode will be enable with the new enhanced UAPI. It will
be extended once the UAPI is agreed in community. This series
just adds the basic support in the interim.
Uma Sh
Enable pipe color support for Display 13 platforms. Currently
limit to just 10bit gamma and later extend it for logarithmic
gamma, once the new UAPI is agreed by community and implemented
by a userspace consumer.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 9 +
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> DPCD register definition added to check and enable panel replay
> capability of the sink.
>
> Signed-off-by: Animesh Manna
> ---
> include/drm/drm_dp_helper.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/drm/drm
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
to incorparate the extended lut size for XE_LPD.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/displa
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driv
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> v1: RFC version.
> v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> v3:
> - code comments
On Tue, Nov 23, 2021 at 09:39:25AM +, Tvrtko Ursulin wrote:
>
> On 17/11/2021 22:49, Vinay Belgaumkar wrote:
> > From: Chris Wilson
> >
> > Everytime we come to the end of a virtual engine's context, re-randomise
> > it's siblings[]. As we schedule the siblings' tasklets in the order they
>
This is the 2nd set of kernel/sysctl.c cleanups. The diff stat should
reflect how this is a much better way to deal with theses. Fortunately
coccinelle can be used to ensure correctness for most of these and/or
future merge conflicts.
Note that since this is part of a larger effort to cleanup
kern
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci PATH
@c1@
expression E1;
identifier subd
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci lib/test_sysctl.c
@c1@
expression E1;
id
From: Xiaoming Ni
The kernel/sysctl.c is a kitchen sink where everyone leaves
their dirty dishes, this makes it very difficult to maintain.
To help with this maintenance let's start by moving sysctls to
places where they actually belong. The proc sysctl maintainers
do not want to know what sysct
From: Xiaoming Ni
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
Move inotify_user sysctl to inotify_user.c while at it to remove clutter
from
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci drivers/char/hpet.c
@c1@
expression E1;
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci PATH
@c1@
expression E1;
identifier subd
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci PATH
@c1@
expression E1;
identifier subd
There is no need to user boiler plate code to specify a set of base
directories we're going to stuff sysctls under. Simplify this by using
register_sysctl() and specifying the directory path directly.
// pycocci sysctl-subdir-register-sysctl-simplify.cocci PATH
@c1@
expression E1;
identifier subd
On 23.11.2021 00:03, Alan Previn wrote:
> From: John Harrison
...
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 77fbcd8730ee..0bfc92b1b982 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/
== Series Details ==
Series: Enable pipe color support on D13 platform
URL : https://patchwork.freedesktop.org/series/97219/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10919 -> Patchwork_21670
Summary
---
**SUCCES
On 11/22/2021 8:56 AM, Daniele Ceraolo Spurio wrote:
On 11/18/2021 11:35 AM, Daniele Ceraolo Spurio wrote:
On 11/16/2021 10:03 PM, Tejas Upadhyay wrote:
selftest --r live shows failure in suspend tests when
RPM wakelock is not acquired during suspend.
This changes addresses below error
Hi,
just few random nits below
-Michal
On 23.11.2021 00:03, Alan Previn wrote:
> Update GuC ADS size allocation to include space for
> the lists of error state capture register descriptors.
>
> Also, populate the lists of registers we want GuC to report back to
> Host on engine reset events. T
On 23.11.2021 00:03, Alan Previn wrote:
> Add device specific tables and register lists to cover different engines
> class types for GuC error state capture.
>
> Also, add runtime allocation and freeing of extended register lists
> for registers that need steering identifiers that depend on
> th
== Series Details ==
Series: sysctl: second set of kernel/sysctl cleanups
URL : https://patchwork.freedesktop.org/series/97221/
State : failure
== Summary ==
Applying: hpet: simplify subdirectory registration with register_sysctl()
Applying: i915: simplify subdirectory registration with regist
Hi all,
Today's linux-next merge of the drm-intel-gt tree got a conflict in:
drivers/gpu/drm/i915/i915_pci.c
between commit:
3c542cfa8266 ("drm/i915/dg2: Tile 4 plane format support")
from the drm-intel tree and commit:
a5b7ef27da60 ("drm/i915: Add struct to hold IP version")
from the
== Series Details ==
Series: Enable pipe color support on D13 platform
URL : https://patchwork.freedesktop.org/series/97219/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10919_full -> Patchwork_21670_full
Summary
---
== Series Details ==
Series: drm/i915/ttm: Async migration (rev11)
URL : https://patchwork.freedesktop.org/series/96798/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
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