On Thu, Mar 03, 2022 at 02:34:34PM -0800, Matt Roper wrote:
In the past we've always assumed that an RCS engine is present on every
platform. However now that we have compute engines there may be
platforms that have CCS engines but no RCS, or platforms that are
designed to have both, but have th
== Series Details ==
Series: drm/i915: Use the memcpy_from_wc function from drm (rev3)
URL : https://patchwork.freedesktop.org/series/100581/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320_full -> Patchwork_22475_full
== Series Details ==
Series: drm/i915/gtt: reduce overzealous alignment constraints for GGTT (rev2)
URL : https://patchwork.freedesktop.org/series/100991/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11320_full -> Patchwork_22474_full
=
On Thu, Mar 03, 2022 at 08:47:08PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/adl-n: Add stepping info
> URL : https://patchwork.freedesktop.org/series/100995/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11318_full -> Patchwork_22472_full
>
Please help to merge.
Thanks,
Tejas
> -Original Message-
> From: Roper, Matthew D
> Sent: 04 March 2022 10:09
> To: Surendrakumar Upadhyay, TejaskumarX
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/adl-n: Add stepping info
>
> On Thu, Mar 03, 2022 at 05:02:52P
On Thu, Mar 03, 2022 at 05:02:52PM +0530, Tejas Upadhyay wrote:
> Add ADL-N stepping-substepping info in
> accordance to BSpec.
>
> Bspec: 68397
>
> Cc: Matt Roper
> Signed-off-by: Tejas Upadhyay
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_step.c | 7 +++
> 1 file changed
Hi Tvrtko
Can we need extend this patch by adding selftest?
Thanks,
Mastan
-Original Message-
From: Auld, Matthew
Sent: 03 March 2022 16:14
To: Tvrtko Ursulin ; Katragadda, MastanX
; intel-gfx@lists.freedesktop.org
Cc: Surendrakumar Upadhyay, TejaskumarX
Subject: Re: [Intel-gf
== Series Details ==
Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev5)
URL : https://patchwork.freedesktop.org/series/98801/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11322 -> Patchwork_22484
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709
URL : https://patchwork.freedesktop.org/series/101023/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11322 -> Patchwork_22483
Summary
== Series Details ==
Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev5)
URL : https://patchwork.freedesktop.org/series/98801/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b7eb4985f027 drm/i915/display/vrr: Reset VRR capable property on a long hpd
-:1
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709
URL : https://patchwork.freedesktop.org/series/101023/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709
URL : https://patchwork.freedesktop.org/series/101023/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1deb35fff8c4 drm/i915/dg2: Add preemption changes for Wa_14015141709
-:127: CHECK:MACRO_ARG_
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads (rev4)
URL : https://patchwork.freedesktop.org/series/100428/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11322 -> Patchwork_22482
Summary
--
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads (rev4)
URL : https://patchwork.freedesktop.org/series/100428/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads (rev4)
URL : https://patchwork.freedesktop.org/series/100428/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5ef6e2a52bd2 drm/i915/guc: Limit scheduling properties to avoid overflow
-:42: CHECK:MACRO
On Wed, Mar 02, 2022 at 09:03:18AM +, Tvrtko Ursulin wrote:
On 01/03/2022 19:34, Umesh Nerlige Ramappa wrote:
On Tue, Feb 22, 2022 at 02:04:21PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
This will be useful to have at hand in a following patch.
Signed-off-by: Tvrtko Ursulin
---
== Series Details ==
Series: series starting with [1/2] drm/i915/xehp: Support platforms with CCS
engines but no RCS
URL : https://patchwork.freedesktop.org/series/101019/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11321 -> Patchwork_22481
=
With some VRR panels, user can turn VRR ON/OFF on the fly from the panel
settings.
When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore MSA
bit
in the DPCD. Currently the driver parses that onevery HPD but fails to reset
the corresponding VRR Capable Connector property.
Henc
On Thu, Mar 03, 2022 at 02:37:35PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> An earlier patch added support for compute engines. However, it missed
> enabling the anti-pre-emption w/a for the new engine class. So move
> the 'compute capable' flag earlier and use it for the
== Series Details ==
Series: series starting with [1/2] drm/i915/xehp: Support platforms with CCS
engines but no RCS
URL : https://patchwork.freedesktop.org/series/101019/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't
On 3/2/2022 01:27, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Prep work for next GuC release (rev4)
*URL:* https://patchwork.freedesktop.org/series/99805/
*State:*failure
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22457/index.html
C
On 3/3/2022 14:34, Matt Roper wrote:
From: Stuart Summers
If RCS is not enumerated, GuC will return invalid parameters.
Make sure we do not send RCS supported when we have not enumerated
it.
Cc: Vinay Belgaumkar
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
Reviewed-by: John Harr
From: Akeem G Abodunrin
Starting with DG2, preemption can no longer be controlled using userspace
on a per-context basis. Instead, the hardware only allows us to enable or
disable preemption in a global, system-wide basis. Also, we lose the
ability to specify the preemption granularity (such as b
On Wed, Feb 23, 2022 at 03:13:15PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> When using bigjoiner it's useful to know the offset of each
> individual pipe in the whole set of joined pipes. Let's include
> that information in our PIPESRC rectangle. With this we can make
> the plane cli
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
It is not totally unbound as the heartbeat will kick in eventually
and cause a reset of the hung engine.
However, this does not work well in G
From: John Harrison
Compute workloads are inherently not pre-emptible for long periods on
current hardware. As a workaround for this, the pre-emption timeout
for compute capable engines was disabled. This is undesirable with GuC
submission as it prevents per engine reset of hung contexts. Hence t
From: John Harrison
GuC converts the pre-emption timeout and timeslice quantum values into
clock ticks internally. That significantly reduces the point of 32bit
overflow. On current platforms, worst case scenario is approximately
110 seconds. Rather than allowing the user to set higher values and
From: John Harrison
An earlier patch added support for compute engines. However, it missed
enabling the anti-pre-emption w/a for the new engine class. So move
the 'compute capable' flag earlier and use it for the pre-emption w/a
test.
Fixes: c674c5b9342e ("drm/i915/xehp: CCS should use RCS setup
From: John Harrison
Compute workloads are inherently not pre-emptible on current hardware.
Thus the pre-emption timeout was disabled as a workaround to prevent
unwanted resets. Instead, the hang detection was left to the heartbeat
and its (longer) timeout. This is undesirable with GuC submission
From: Stuart Summers
If RCS is not enumerated, GuC will return invalid parameters.
Make sure we do not send RCS supported when we have not enumerated
it.
Cc: Vinay Belgaumkar
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
1 file
In the past we've always assumed that an RCS engine is present on every
platform. However now that we have compute engines there may be
platforms that have CCS engines but no RCS, or platforms that are
designed to have both, but have the RCS engine fused off.
Various engine-centric initialization
On Thu, Feb 24, 2022 at 12:35:59PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 23, 2022 at 12:00:28PM -0800, Navare, Manasi wrote:
> > On Wed, Feb 23, 2022 at 03:13:14PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Replace the hardcoded 2 pipe assumptions when we're massaging
>
On Wed, Feb 23, 2022 at 03:13:12PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Instead of just having the pipe_src_{w,h} let's use a full
> drm_rect for it. This will be particularly useful to astract
> away some bigjoiner details.
>
> v2: No hweight() stuff yet
>
> Signed-off-by: Vil
== Series Details ==
Series: Bump DMC to v2.16 on ADL-P (rev2)
URL : https://patchwork.freedesktop.org/series/100666/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320 -> Patchwork_22480
Summary
---
**SUCCESS**
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/fbdev: fixup setting screen_size
URL : https://patchwork.freedesktop.org/series/101016/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320 -> Patchwork_22479
==
We are seeking nominations for candidates for election to the X.org Foundation
Board of Directors. However, as we presently do not have enough nominations to
start the election - the decision has been made to extend the timeline by 2
weeks. Note this is a fairly regular part of the elections proces
== Series Details ==
Series: drm/selftests: fix a shift-out-of-bounds bug
URL : https://patchwork.freedesktop.org/series/101012/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320 -> Patchwork_22478
Summary
---
**SU
== Series Details ==
Series: drm/i915/adl-n: Add stepping info
URL : https://patchwork.freedesktop.org/series/100995/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11318_full -> Patchwork_22472_full
Summary
---
**SUC
We currently blow up in i915_vm_lock_objects when binding the dpt, due
to what looks like NULL scratch[0]. Likely the moving fence has not been
unset yet(even though it should have signalled), due to some previous
move. For now let's just create something which more closely resembles a
proper vm.
Since we are actually mapping the object and not the vma, when dealing
with LMEM, we should be careful and use the obj->base.size here, since
the vma could have all kinds of funny padding constraints.
Signed-off-by: Matthew Auld
Cc: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_fbd
== Series Details ==
Series: drm/selftests: fix a shift-out-of-bounds bug
URL : https://patchwork.freedesktop.org/series/101012/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
233edfd3e6e2 drm/selftests: fix a shift-out-of-bounds bug
-:47: WARNING:COMMIT_LOG_LONG_LINE: Possible
== Series Details ==
Series: drm/i915: Fix bandwith related cdclk calculations (rev2)
URL : https://patchwork.freedesktop.org/series/98975/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320 -> Patchwork_22477
Summary
On Thu, Mar 03, 2022 at 08:19:30PM +0200, Jani Nikula wrote:
> Allocate the individual intel_gmbus structs dynamically. This lets us
> hide struct intel_gmbus inside intel_gmbus.c completely. Also use the
> cleanup function on the error path to avoid duplication.
>
> Leave #include in i915_drv.h
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, March 3, 2022 1:59 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Add cdclk check to atomic
> check
>
> On Wed, 02 Mar 2022, Anusha Srivatsa wrote:
> > Checki
== Series Details ==
Series: drm/i915: Fix bandwith related cdclk calculations (rev2)
URL : https://patchwork.freedesktop.org/series/98975/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Fix bandwith related cdclk calculations (rev2)
URL : https://patchwork.freedesktop.org/series/98975/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c60dc5b8150b drm/i915: Tweak plane ddb allocation tracking
f73e140093bf drm/i915: Split plan
== Series Details ==
Series: series starting with [1/5] drm/i915/gmbus: combine gmbus pin lookups to
one function
URL : https://patchwork.freedesktop.org/series/101007/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320 -> Patchwork_22476
== Series Details ==
Series: drm/i915: Use the memcpy_from_wc function from drm (rev3)
URL : https://patchwork.freedesktop.org/series/100581/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320 -> Patchwork_22475
Summary
--
== Series Details ==
Series: series starting with [1/5] drm/i915/gmbus: combine gmbus pin lookups to
one function
URL : https://patchwork.freedesktop.org/series/101007/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
From: Ville Syrjälä
Make sure the CDCLK is high enough to support the so called
"maximum pipe read bandwidth" limitation. Specified as
51.2 x CDCLK.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 36 +
drivers/gpu/drm/i915/display/intel_bw.h
From: Ville Syrjälä
The current code also forgets to call intel_atomic_lock_global_state()
when other stuff besides the final min_cdlck changes in the state.
That means we may throw away data which actually has changed, and
thus we can't be at all sure what the code ends up doing during
subsequen
From: Ville Syrjälä
Make the dbuf bandwidth min cdclk calculations match the spec
more closely. Supposedly the arbiter can only guarantee an equal
share of the total bandwidth of the slice to each active plane
on that slice. So we take the max bandwidth of any of the planes
on each slice and mult
From: Ville Syrjälä
We should round up when doing bandwidth calculations to make sure
our estimates don't fall short of the actual number.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gp
From: Ville Syrjälä
intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
(at least documented) dbuf min cdclk limit on pre-skl so let's just get
rid of all this confusion.
Reviewed-by: Stanislav Lisovski
From: Ville Syrjälä
Handle the plane relative data rate in exactly the same
way as we already handle the real data rate. Ie. pre-calculate
it during intel_plane_atomic_check_with_state(), and assign/clear
it for the Y plane as needed. This should guarantee that the
tracking is 100% consistent, an
From: Ville Syrjälä
There's really no need to maintain these total[] arrays to
track the size of each plane's ddb allocation. We just stick
the results straight into the crtc_state ddb tracking structures.
The main annoyance with all this is the mismatch between
wm_uv vs. ddb_y on pre-icl. If on
From: Ville Syrjälä
Split the currently combined plane data_rate into the proper
Y vs. CbCr components. This matches how we now track the
plane dbuf allocations, and thus will make the dbuf bandwidth
calculations actually produce the correct numbers for each
dbuf slice.
Reviewed-by: Stanislav Li
From: Ville Syrjälä
Let's store the plane allocation in a manner which more closely
matches how the hw operates. That is, we store the packed/CbCr
ddb in one struct, and the Y ddb in another. Currently we're
storing packed/Y in one struct, CbCr in the other.
This also works pretty well for icl+
From: Ville Syrjälä
Fix up the dbuf bandwidth cdclk calculations to match the spec,
and also implement the cdclk based pipe max bandwidth limit.
TODO: intel_bw contains two orthogonal things (qgv vs. cdclk).
We should probably just split it into two parts to life
less confusing. But
On 3/3/2022 01:55, Tvrtko Ursulin wrote:
On 02/03/2022 17:55, John Harrison wrote:
I was assuming 2.5s tP is enough and basing all calculation on that.
Heartbeat or timeslicing regardless. I thought we established
neither of us knows how long is enough.
Are you now saying 2.5s is definitely
== Series Details ==
Series: drm/i915: Use the memcpy_from_wc function from drm (rev3)
URL : https://patchwork.freedesktop.org/series/100581/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/gtt: reduce overzealous alignment constraints for GGTT (rev2)
URL : https://patchwork.freedesktop.org/series/100991/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11320 -> Patchwork_22474
===
Combine the platform specific if ladders for array lookup and size
checks into one. This is cleaner and avoids duplication, but hopefully
also helps any static analyzers that seem to have trouble with the
bounds checks.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_gmbus.c |
Include linux/highmem.h and linux/swap.h explicitly where needed so we
can drop the linux/i2c.h include from i915_drv.h where it pulled in the
dependencies implicitly.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gem/i915_gem_context.c| 1 +
drivers/gpu/drm/i915/gem/i915_gem_execb
Avoid the additional gmbus lookup on the pin.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_gmbus.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 9dc664
Allocate the individual intel_gmbus structs dynamically. This lets us
hide struct intel_gmbus inside intel_gmbus.c completely. Also use the
cleanup function on the error path to avoid duplication.
Leave #include in i915_drv.h for now, as it pulls in a
bunch of implicit dependencies.
Signed-off-b
Avoid separate pin lookups for validity and name.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_gmbus.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 9
Fast copy using non-temporal instructions for x86 currently exists at two
locations. One is implemented in i915 driver at i915/i915_memcpy.c and
another copy at drm_cache.c. The plan is to remove the duplicate
implementation in i915 driver and use the functions from drm_cache.c.
A variant of drm_m
drm_memcpy_from_wc() performs fast copy from WC memory type using
non-temporal instructions. Now there are two similar implementations of
this function. One exists in drm_cache.c as drm_memcpy_from_wc() and
another implementation in i915/i915_memcpy.c as i915_memcpy_from_wc().
drm_memcpy_from_wc()
There is no need for the destination address to be aligned to 16 byte
boundary to be able to use the non-temporal instructions while copying.
Non-temporal instructions are used only for loading from the source
address which has alignment constraints.
We only need to take care of using the right ins
Pointer passed to zlib_deflate() for compression could point to io
mapped memory and might end up in direct derefencing.
io mapped memory is copied to a temporary buffer, which is then shared
to zlib_deflate(), only for the case where platform supports fast copy
using non-temporal instructions. If
io mapped memory should not be directly dereferenced to ensure
portability. io memory should be read/written/copied using helper
functions.
i915_memcpy_from_wc() function was used to copy the data from io memory to
a temporary buffer and pointer to the temporary buffer was passed to CRC
calculation
memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
by the implementation in drm_cache.c.
Updated to use the functions provided by drm_cache.c.
Signed-off-by: Balasubramani Vivekanandan
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 --
1
memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
by the implementation in drm_cache.c.
Updated to use the functions provided by drm_cache.c.
v2: Check if the log object allocated from local memory or system memory
and according setup the iosys_map (Lucas)
Cc: Lucas De Ma
memcpy_from_wc functions in i915_memcpy.c will be removed and replaced
by the implementation in drm_cache.c.
Updated to use the functions provided by drm_cache.c.
v2: check if the source and destination memory address is from local
memory or system memory and initialize the iosys_map according
Matthew Auld wrote:
> Scratch that. it looks like the for() already accounts for this, as
> pointed out by Chris.
Yes, you are right.
I rechecked and found this one is indeed an ordinary code smell.
Thank you for taking the time.
Xiaoke Wang
On 2022-03-02 15:55, Michael Cheng wrote:
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to
understand how ARM flushes a range of dcache for device drivers, and not
an equal to x86 clflush.
I believe the concern is if the CPU writes an update,
> On 3. Mar 2022, at 05:58, David Laight wrote:
>
> From: Xiaomeng Tong
>> Sent: 03 March 2022 02:27
>>
>> On Wed, 2 Mar 2022 14:04:06 +, David Laight
>> wrote:
>>> I think that it would be better to make any alternate loop macro
>>> just set the variable to NULL on the loop exit.
>>> Th
> I think this would make sense, it would mean you only assign the containing
> element on valid elements.
>
> I was thinking something along the lines of:
>
> #define list_for_each_entry(pos, head, member)
> \
> for (struct list_head *list = head->next
> From: Xiaomeng Tong
> > Sent: 03 March 2022 07:27
> >
> > On Thu, 3 Mar 2022 04:58:23 +, David Laight wrote:
> > > on 3 Mar 2022 10:27:29 +0800, Xiaomeng Tong wrote:
> > > > The problem is the mis-use of iterator outside the loop on exit, and
> > > > the iterator will be the HEAD's container
correct for typo:
-for (struct list_head *list = head->next, cond = (struct list_head *)-1; cond
== (struct list_head *)-1; cond = NULL) \
+for (struct list_head *list = head->next, *cond = (struct list_head *)-1; cond
== (struct list_head *)-1; cond = NULL) \
--
Xiaomeng Tong
On Thu, 3 Mar 2022 04:58:23 +, David Laight wrote:
> on 3 Mar 2022 10:27:29 +0800, Xiaomeng Tong wrote:
> > The problem is the mis-use of iterator outside the loop on exit, and
> > the iterator will be the HEAD's container_of pointer which pointers
> > to a type-confused struct. Sidenote: The *
On Wed, 2 Mar 2022 14:04:06 +, David Laight
wrote:
> I think that it would be better to make any alternate loop macro
> just set the variable to NULL on the loop exit.
> That is easier to code for and the compiler might be persuaded to
> not redo the test.
No, that would lead to a NULL derefe
Am 01.03.22 um 21:38 schrieb Arunpravin:
- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy
v2(Matthew Auld):
- replace spinlock with mutex as we call kmem_cache_zalloc
(..., GFP_KERNEL) in drm_buddy_alloc() function
- lock
On Wed, 2 Mar 2022 at 10:22, Thomas Hellström
wrote:
>
> vms are not getting properly closed. Rather than fixing that,
> Remove the vm open count and instead rely on the vm refcount.
>
> The vm open count existed solely to break the strong references the
> vmas had on the vms. Now instead make tho
On 3/2/2022 10:31 AM, Laurent Pinchart wrote:
Hi Abhinav,
On Wed, Mar 02, 2022 at 10:28:03AM -0800, Abhinav Kumar wrote:
On 2/28/2022 5:42 AM, Laurent Pinchart wrote:
On Mon, Feb 28, 2022 at 02:28:27PM +0200, Laurent Pinchart wrote:
On Mon, Feb 28, 2022 at 02:09:15PM +0200, Jani Nikula wro
== Series Details ==
Series: Remove usage of list iterator past the loop body (rev5)
URL : https://patchwork.freedesktop.org/series/100822/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11317_full -> Patchwork_22471_full
Su
== Series Details ==
Series: drm/i915/dg2: Use I915_BO_ALLOC_CONTIGUOUS flag for DPT (rev2)
URL : https://patchwork.freedesktop.org/series/97806/
State : failure
== Summary ==
Applying: drm/i915/dg2: Use I915_BO_ALLOC_CONTIGUOUS flag for DPT
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: drm/i915/gtt: reduce overzealous alignment constraints for GGTT
URL : https://patchwork.freedesktop.org/series/100991/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11317_full -> Patchwork_22470_full
On Mon, Feb 14, 2022 at 12:55:32PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Print the offending plane/crtc id+name in the async flip debugs.
Reviewed-by: Stanislav Lisovskiy
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_d
On Mon, Feb 14, 2022 at 12:55:31PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The current implementation of the async flip wm0/ddb optimization
> does not work at all. The biggest problem is that we skip the
> whole intel_pipe_update_{start,end}() dance and thus never actually
> comple
On Mon, Feb 14, 2022 at 12:55:30PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Since the async flip state check is done very late and
> thus it can see potentially all the planes in the state
> (due to the wm/ddb optimization) we need to move the
> "can the requested plane do async flip
On Mon, Feb 14, 2022 at 12:55:29PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> data_rate==0 no longer means a plane is disabled, it could
> also mean we want to use the minimum ddb allocation for it.
> Hence we can't bail out early during ddb allocation or
> else we'll simply forget to
== Series Details ==
Series: drm/i915/adl-n: Add stepping info
URL : https://patchwork.freedesktop.org/series/100995/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11318 -> Patchwork_22472
Summary
---
**SUCCESS**
On Sun, 2022-02-27 at 05:27 +, Patchwork wrote:
Patch Details
Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev5)
URL:https://patchwork.freedesktop.org/series/100633/
State: success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/index.h
== Series Details ==
Series: drm/i915: add more TMDS clock rate supported by HDMI driver (rev2)
URL : https://patchwork.freedesktop.org/series/100866/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11317_full -> Patchwork_22469_full
=
On Thu, 9 Dec 2021 at 17:00, Stanislav Lisovskiy
wrote:
>
> Do mapping using CONTIGUOUS flag - otherwise
> i915_gem_object_is_contiguous warn is triggered.
>
> Signed-off-by: Stanislav Lisovskiy
As a temporary fix,
Reviewed-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/display/intel_dpt.c | 2
On Thu, Mar 03, 2022 at 03:26:57PM +0800, Xiaomeng Tong wrote:
> On Thu, 3 Mar 2022 04:58:23 +, David Laight wrote:
> > on 3 Mar 2022 10:27:29 +0800, Xiaomeng Tong wrote:
> > > The problem is the mis-use of iterator outside the loop on exit, and
> > > the iterator will be the HEAD's container_o
== Series Details ==
Series: Remove usage of list iterator past the loop body (rev5)
URL : https://patchwork.freedesktop.org/series/100822/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11317 -> Patchwork_22471
Summary
Add ADL-N stepping-substepping info in
accordance to BSpec.
Bspec: 68397
Cc: Matt Roper
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/intel_step.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 4f
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