== Series Details ==
Series: i915: General multicast steering updates
URL : https://patchwork.freedesktop.org/series/101367/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11363_full -> Patchwork_22565_full
Summary
---
== Series Details ==
Series: drm: Fix a infinite loop condition when order becomes 0
URL : https://patchwork.freedesktop.org/series/101360/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11363_full -> Patchwork_22563_full
Su
== Series Details ==
Series: drm/i915: Reduce stack usage in debugfs due to SSEU (rev2)
URL : https://patchwork.freedesktop.org/series/101369/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11363 -> Patchwork_22567
Summary
-
Hi Matt,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on drm-exynos/exynos-drm-next drm/drm-next
next-20220310]
[cannot apply to drm-intel/for-linux-next tegra-drm/drm/tegra/for-next
airlied/drm-next v5.17-rc8]
[If
== Series Details ==
Series: drm/i915: round_up the size to the alignment value
URL : https://patchwork.freedesktop.org/series/101357/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11363_full -> Patchwork_22562_full
Summary
On 18/02/2022 12:03, Ville Syrjala wrote:
From: Ville Syrjälä
struct drm_display_mode embeds a list head, so overwriting
the full struct with another one will corrupt the list
(if the destination mode is on a list). Use drm_mode_copy()
instead which explicitly preserves the list head of
the des
On Tue, Mar 15, 2022 at 03:01:44AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Reduce stack usage in debugfs due to SSEU
> URL : https://patchwork.freedesktop.org/series/101369/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11363 -> Patchwork
== Series Details ==
Series: drm/i915: Reduce stack usage in debugfs due to SSEU
URL : https://patchwork.freedesktop.org/series/101369/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11363 -> Patchwork_22566
Summary
---
Hi Alan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next v5.17-rc8 next-20220310]
[If your patch is applied to the wrong git tree, kindly d
From: John Harrison
sseu_dev_info is already a pretty large structure which will likely
continue to grow when future platforms increase potential DSS and EU
counts. Let's switch the stack placement of this structure in debugfs
with a dynamic allocation.
Signed-off-by: John Harrison
Signed-off-
== Series Details ==
Series: i915: General multicast steering updates
URL : https://patchwork.freedesktop.org/series/101367/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11363 -> Patchwork_22565
Summary
---
**SUCCES
== Series Details ==
Series: i915: General multicast steering updates
URL : https://patchwork.freedesktop.org/series/101367/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm: Fix a infinite loop condition when order becomes 0
URL : https://patchwork.freedesktop.org/series/101360/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11363 -> Patchwork_22563
Summary
== Series Details ==
Series: suppress the wrong long hotplug events
URL : https://patchwork.freedesktop.org/series/101366/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M]
== Series Details ==
Series: drm/i915: round_up the size to the alignment value
URL : https://patchwork.freedesktop.org/series/101357/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11363 -> Patchwork_22562
Summary
---
== Series Details ==
Series: drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6() (rev2)
URL : https://patchwork.freedesktop.org/series/101301/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11360_full -> Patchwork_22559_full
=
ip drm-tip
config: i386-randconfig-a002-20220314
(https://download.01.org/0day-ci/archive/20220315/202203150713.nsmdifry-...@intel.com/config)
compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04) 9.4.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/li
From: Daniele Ceraolo Spurio
GuC has its own steering mechanism and can't use the default set by i915,
so we need to provide the steering information that the FW will need to
save/restore registers while processing an engine reset. The GUC
interface allows us to do so as part of the register save
Add a new 'steering' node in each gt's debugfs directory that tells
whether we're using explicit steering for various types of MCR ranges
and, if so, what MMIO ranges it applies to.
We're going to be transitioning away from implicit steering, even for
slice/dss steering soon, so the information re
A few minor steering updates, mostly to prepare for other upcoming work.
We'll soon be doing most of our steering explicitly, rather than relying
on implicit steering as we do now, so reporting the steering assignments
in debugfs will be helpful for debugging. We also have some features
coming up
Upcoming patches will need to steer writes to multicast registers as
well as reading them.
Although the setting of the 'multicast' bit should only really matter
for write operations (reads always operate in a unicast manner and give
us the result from one specific instance), Wa_22013088509 suggest
On 2022-03-08 10:58 a.m., Lucas De Marchi wrote:
On Tue, Feb 22, 2022 at 08:24:31PM +0100, Thomas Hellström (Intel) wrote:
Hi, Michael,
On 2/22/22 18:26, Michael Cheng wrote:
This patch removes logic for wbinvd_on_all_cpus and brings in
drm_cache.h. This header has the logic that outputs a wa
From: Mohammed Khajapasha
Add 2sec sleep for power state connector when a monitor
is in power sleep state before atomic commit enable.
Monitors like LG 27UL650-W, 27UK850 goes into power
sleep state and generates long duration hotplug events
even the monitor connected for display, sleep for 2sec
From: Mohammed Khajapasha
Add connector disable wait time for a power state connector
for monitor power sleep state.
Monitors like LG 27UL650-W, 27UK850 goes into power sleep state
and generates long duration hotplug events even the monitor
connected for display, create a debugfs entry to enable
Monitors like LG 27UL650-W, 27UK850 goes into power sleep state
and generates long duration hotplug events even when the monitor
is connected for display. Here is a proposal to detect and
suppress such hotplug events by "sleep" for 2 secs for power
state monitor become available before enable atomi
On Fri, Feb 18, 2022 at 12:03:41PM +0200, Ville Syrjala wrote:
> drm: Add drm_mode_init()
> drm/bridge: Use drm_mode_copy()
> drm/imx: Use drm_mode_duplicate()
> drm/panel: Use drm_mode_duplicate()
> drm/vc4: Use drm_mode_copy()
These have been pushed to drm-misc-next.
> drm/amdgpu: Re
== Series Details ==
Series: lrc selftest fixes (rev2)
URL : https://patchwork.freedesktop.org/series/101353/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11360 -> Patchwork_22561
Summary
---
**FAILURE**
Serious
On Mon, Mar 14, 2022 at 10:40:47AM +0200, Jani Nikula wrote:
> On Sun, 13 Mar 2022, Lee Shawn C wrote:
> > drm_find_cea_extension() always look for a top level CEA block. Pass
> > ext_index from caller then this function to search next available
> > CEA ext block from a specific EDID block pointer
== Series Details ==
Series: lrc selftest fixes (rev2)
URL : https://patchwork.freedesktop.org/series/101353/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine
== Series Details ==
Series: lrc selftest fixes (rev2)
URL : https://patchwork.freedesktop.org/series/101353/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d63eda7a7b01 drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
bd18807e4830 drm/i915/selftests: Check for incomplet
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101348/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11360 -> Patchwork_22560
Summary
---
**FAILURE**
Seri
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101348/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101348/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d88514e8a355 drm/i915/guc: Update GuC ADS size for error capture lists
-:39: WARNING:FILE_PATH_CHANGES: added, moved o
== Series Details ==
Series: drm/i915/pmu: Drop redundant IS_VALLEYVIEW check in __get_rc6() (rev2)
URL : https://patchwork.freedesktop.org/series/101301/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11360 -> Patchwork_22559
===
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev4)
URL : https://patchwork.freedesktop.org/series/101222/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11358_full -> Patchwork_22558_full
==
== Series Details ==
Series: drm/i915/display/adlp: Update eDP voltage swing table
URL : https://patchwork.freedesktop.org/series/101343/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11358_full -> Patchwork_22557_full
Summ
From: Chris Wilson
Ensure that we always signal the semaphore when timing out, so that if it
happens to be stuck waiting for the semaphore we will quickly recover
without having to wait for a reset.
Reported-by: CQ Tang
Signed-off-by: Chris Wilson
Cc: CQ Tang
cc: Joonas Lahtinen
Signed-off-b
From: Chris Wilson
When testing whether we can get the GPU to leak information about
non-privileged state, we first need to ensure that the output buffer is
set to a known value as the HW may opt to skip the write into memory for
a non-privileged read of a sensitive register. We chose POISON_INUS
From: Chris Wilson
In order to keep the context image parser simple, we assume that all
commands follow a similar format. A few, especially not MI commands on
the render engines, have fixed lengths not encoded in a length field.
This caused us to incorrectly skip over 3D state commands, and start
From: Chris Wilson
Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.
Testcase: igt/i915_selftests/gt_lrc
Signed-off-by: Chris Wilson
Cc: Mik
Few bug fixes for lrc selftest.
Chris Wilson (4):
drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
drm/i915/selftests: Check for incomplete LRI from the context image
drm/i915/selftest: Clear the output buffers before GPU writes
drm/i915/selftest: Always cancel semaphore on error
Few bug fixes for lrc selftest.
Chris Wilson (4):
drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
drm/i915/selftests: Check for incomplete LRI from the context image
drm/i915/selftest: Clear the output buffers before GPU writes
drm/i915/selftest: Always cancel semaphore on error
On Mon, 14 Mar 2022 08:35:17 -0700, Tvrtko Ursulin wrote:
>
> >> Alternatively, all other uapi uses struct i915_engine_class_instance to
> >> address engines which uses u16:u16.
> >>
> >> How ugly it is to stuff a struct into u32 flags is the question... But you
> >> could at least use u16:u16 for
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Fix HPD short pulse
handling for eDP (rev2)
URL : https://patchwork.freedesktop.org/series/101299/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11358_full -> Patchwork_22556_full
===
Print the GuC captured error state register list (string names
and values) when gpu_coredump_state printout is invoked via
the i915 debugfs for flushing the gpu error-state that was
captured prior.
Since GuC could have reported multiple engine register dumps
in a single notification event, parse t
GuC log buffer regions for debug-log-events, crash-dumps and
error-state-capture are all part of a single bo allocation that
also includes the guc_log_buffer_state structures. Now that we
support it, increase the size allocation for error-capture.
Since the error-capture region is accessed at non-
In the rare but possible scenario where we are in the midst of
multiple GuC error-capture (and engine reset) events and the
user also triggers a forced full GT reset or the internal watchdog
triggers the same, intel_guc_submission_reset_prepare's call
to flush_work(&guc->ct.requests.worker) can cau
Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +++
.../gpu/drm/i91
Add a flags parameter through all of the coredump creation
functions. Add a bitmask flag to indicate if the top
level gpu_coredump event is triggered in response to
a GuC context reset notification.
Using that flag, ensure all coredump functions that
read or print mmio-register values related to w
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
1 file changed, 59 insertions(+), 2
- Upon the G2H Notify-Err-Capture event, parse through the
GuC Log Buffer (error-capture-subregion) and generate one or
more capture-nodes. A single node represents a single "engine-
instance-capture-dump" and contains at least 3 register lists:
global, engine-class and engine-instance. An
For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c
Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 47 ++
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 116 ++
drivers/gpu/drm/i915/gt/
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Then, populate GuC ADS with the lists of registers we want
GuC to report back to host on engine reset events. This list
should include global, engine-class and engine-instance
registers for e
This series:
1. Enables support of GuC to report error-state-capture
using a list of MMIO registers the driver registers
and GuC will dump, log and notify right before a GuC
triggered engine-reset event.
2. Updates the ADS blob creation to register said lists
of global, engi
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev4)
URL : https://patchwork.freedesktop.org/series/101222/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11358 -> Patchwork_22558
Summar
On Mon, Mar 14, 2022 at 08:27:53AM -0700, José Roberto de Souza wrote:
> Up to now alderlake-p was using the same eDP voltage swing table for
> frequencies up to HBR2 as icelake but now it has its own table.
>
> BSpec: 49291
> Cc: Clinton A Taylor
> Signed-off-by: José Roberto de Souza
Matches
== Series Details ==
Series: Some more bits for small BAR enabling (rev4)
URL : https://patchwork.freedesktop.org/series/101052/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11358_full -> Patchwork_22555_full
Summary
-
On Sat, Mar 12, 2022 at 01:58:28AM +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/2] drm/i915/sseu: Don't overallocate
> subslice storage
> URL : https://patchwork.freedesktop.org/series/101305/
> State : success
>
> == Summary ==
>
> CI Bug Log - change
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev4)
URL : https://patchwork.freedesktop.org/series/101222/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: DRRS fixes/cleanups and start of static DRRS (rev4)
URL : https://patchwork.freedesktop.org/series/101222/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d81ae837b734 drm/i915/dsi: Pass fixed_mode to *_dsi_add_properties()
f3f40125db96 drm/
== Series Details ==
Series: drm/i915/display/adlp: Update eDP voltage swing table
URL : https://patchwork.freedesktop.org/series/101343/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11358 -> Patchwork_22557
Summary
--
Because VLV_GT_RENDER_RC6 == GEN6_GT_GFX_RC6, the IS_VALLEYVIEW() check is
not needed. Neither is the check present in other code paths which call
intel_rc6_residency_ns() (in functions gen6_drpc(), rc6_residency() and
rc6_residency_ms_show()).
v2: Elimintate VLV_GT_RENDER_RC6 #define (Jani)
Cc:
On 12/03/2022 04:16, Matt Atwood wrote:
On Thu, Mar 10, 2022 at 12:26:12PM +, Tvrtko Ursulin wrote:
On 10/03/2022 05:18, Matt Atwood wrote:
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the first,
From: Ville Syrjälä
Store the fixed_mode and downclock_mode as a real list,
in preparation for exposing other supported modes as well.
v2: Init the list in intel_sdvo_connector_alloc() too
v3: Use list_first_entry_or_null() (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
...
Up to now alderlake-p was using the same eDP voltage swing table for
frequencies up to HBR2 as icelake but now it has its own table.
BSpec: 49291
Cc: Clinton A Taylor
Signed-off-by: José Roberto de Souza
---
.../gpu/drm/i915/display/intel_ddi_buf_trans.c | 18 --
1 file changed,
On Mon, Mar 14, 2022 at 12:31:13PM +0200, Jani Nikula wrote:
> On Fri, 11 Mar 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Ger rid of one more ugly crtc->config usage by storing the DRRS
> > state under intel_crtc. intel_drrs_enable() copies what it needs
> > from the crtc state, af
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Fix HPD short pulse
handling for eDP (rev2)
URL : https://patchwork.freedesktop.org/series/101299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11358 -> Patchwork_22556
=
== Series Details ==
Series: drm/i915: Avoid explicit IRQ-off sections. (rev2)
URL : https://patchwork.freedesktop.org/series/101288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11357_full -> Patchwork_22554_full
Summary
On 11.03.2022 10:40, Lucas De Marchi wrote:
> On Tue, Mar 08, 2022 at 10:17:42PM +0530, Balasubramani Vivekanandan wrote:
> > This patch is continuation of the effort to move all pointers in i915,
> > which at any point may be pointing to device memory or system memory, to
> > iosys_map interface.
== Series Details ==
Series: Some more bits for small BAR enabling (rev4)
URL : https://patchwork.freedesktop.org/series/101052/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11358 -> Patchwork_22555
Summary
---
**SU
== Series Details ==
Series: Some more bits for small BAR enabling (rev4)
URL : https://patchwork.freedesktop.org/series/101052/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Avoid explicit IRQ-off sections. (rev2)
URL : https://patchwork.freedesktop.org/series/101288/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11357 -> Patchwork_22554
Summary
---
On 13.03.2022 20:45, Andi Shyti wrote:
Hi Andrzej,
I'm sorry, but I'm not fully understanding,
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+ const char *name)
+{
+ struct kobject *kobj = &dev->kobj;
+
+ /*
+*
Add a generic interface for allocating an object at some specific
offset, and convert stolen over. Later we will want to hook this up to
different backends.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Acked-by: Nirmoy Das
---
.../drm/i915/display/intel_plane_initial.c| 4 +-
drivers/
Just pass along the probed io_size. The backend should be able to
utilize the entire range here, even if some of it is non-mappable.
It does leave open with what to do with stolen local-memory.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
Acked-by: Nirmoy Das
For the ttm backend we can use existing placements fpfn and lpfn to
force the allocator to place the object at the requested offset,
potentially evicting stuff if the spot is currently occupied.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Acked-by: Nirmoy Das
---
.../gpu/drm/i915/gem/i915
Keep the behaviour consistent with normal lmem, where we assume CPU
access if by default required.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Acked-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i9
From: Akeem G Abodunrin
On client platforms with reduced LMEM BAR, we should be able to continue
with driver load with reduced io_size. Instead of using the BAR size to
determine the how large stolen should be, we should instead use the
ADDR_RANGE register to figure this out(at least on platforms
On integrated it looks like the GGTT base should always 1:1 maps to
somewhere within DSM. On discrete the base seems to be pre-programmed with
a normal lmem address, and is not 1:1 mapped with the base address. On
such devices probe the lmem address directly from the PTE.
v2(Ville):
- The base i
From: CQ Tang
When system does not have mappable aperture, ggtt->mappable_end=0. In
this case if we pass PIN_MAPPABLE when pinning vma, the pinning code
will return -ENOSPC. So conditionally set PIN_MAPPABLE if HAS_GMCH().
Suggested-by: Chris P Wilson
Signed-off-by: CQ Tang
Cc: Radhakrishna Sr
The leftover bits around dealing with stolen-local memory + small BAR, plus
some related fixes.
v2: some tweaks based on feedback from Ville
v3: directly probe the PTE to derive the physical offset within lmem
--
2.34.1
On 11/03/2022 09:39, Daniel Vetter wrote:
On Mon, 7 Mar 2022 at 21:38, Vivek Kasireddy wrote:
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between these 2 FBs w
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Store the fixed_mode and downclock_mode as a real list,
> in preparation for exposing other supported modes as well.
>
> v2: Init the list in intel_sdvo_connector_alloc() too
>
> Signed-off-by: Ville Syrjälä
Even for the two mo
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Ger rid of one more ugly crtc->config usage by storing the DRRS
> state under intel_crtc. intel_drrs_enable() copies what it needs
> from the crtc state, after which DRRS can be blissfully ignorant
> of anything going on around i
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The DRRS code has no use for the intel_dp, replace it with
> just a crtc pointer. This is just an intermediate step towards
> making DRRS truly per-crtc.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> driv
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The DRRS code has no use for the intel_dp, replace it with
> just a crtc pointer. This is just an intermediate step towards
> making DRRS truly per-crtc.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> driv
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> There are a couple of cases where we essentially just want to
> get/check the preferred fixed mode of the panel. Add a small
> helper for that to abstract away the direct pointer lookup.
>
> Signed-off-by: Ville Syrjälä
Reviewe
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Abstract away the details on where we store the fixed/downclock
> modes, and also how we select them. Will be useful for static
> DRRS (aka. allowing the user to select the refresh rate for the
> panel).
>
> We pass in the user r
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add a helper to determine which type of DRRS the panel supports.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_drrs.c | 10 +++---
> drivers/gpu/drm/i915/display/i
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add helper to get the drrs type as a string, and use it
> in a couple of places. Also pimp the debugfs output a bit
> while at it.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> .../drm/i915/display/intel_
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Several connectors want to return the fixed_mode from .get_modes(),
> add a helper to do that (and hide the details inside intel_panel.c).
>
> Signed-off-by: Ville Syrjälä
Nice!
Reviewed-by: Jani Nikula
One note below.
> --
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> When we found a downclock mode dev_priv->drrs.type is just a
> straight copy of dev_priv->vbt.drrs_type. And in case we
> couldn't find a downclock mode can_enable_drrs() won't let
> us enable DRRS anyway so the minor distinction
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No need for all this connector type special casing. If the
> connector has a fixed mode just print it, otherwise don't.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_deb
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We want to eventually get rid of the connector->panel.fixed_mode
> pointer so avoid using it during LVDS setup. Since this all
> happens during the encoder init we already have the fixed_mode
> around, just pass that in.
>
> Sign
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We want to stop using connector->panel.fixed_mode directtly.
> In order to look it up in the future we'll need to have the
> requested mode around, so pass that in fully (instead of just
> passing bits of it).
>
> Signed-off-by:
On Fri, 11 Mar 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We want to eventually get rid of the connector->panel.fixed_mode
> pointer so avoid using it during DSI property setup. Since this
> all happens during the encoder init we already have the fixed_mode
> around, just pass that in.
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