Hi Dave & Daniel,
Two final -fixes for v5.18.
One is to reject DMC with out-of-spec MMIO (Cc: stable) and another
to correctly mark guilty contexts on GuC reset.
Regards, Joonas
***
drm-intel-fixes-2022-05-19:
- Reject DMC firmware with out-of-spec MMIO addresses.
- Correctly mark guilty
== Series Details ==
Series: drm/i915/dg2: Extend Wa_22010954014 to DG2-G11 and DG2-G12
URL : https://patchwork.freedesktop.org/series/104104/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11668_full -> Patchwork_104104v1_full
== Series Details ==
Series: drm/i915/dg2: Add workaround 22014600077 (rev2)
URL : https://patchwork.freedesktop.org/series/104097/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11668_full -> Patchwork_104097v2_full
On Wed, 2022-05-18 at 10:45 +0300, Jouni Högander wrote:
> Currently there is no mean to get understanding how psr is utilized.
> E.g. How much psr is actually enabled or how often driver falls back
> to full update.
But with this information what can you do?
I don't see much value on it.
We
== Series Details ==
Series: DG2 VRAM_SR Support (rev2)
URL : https://patchwork.freedesktop.org/series/104128/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11674 -> Patchwork_104128v2
Summary
---
**FAILURE**
Media driver never creates a BO with more than one backing regions.
Acked-by: Tony Ye
Thanks,
Tony
On 5/2/2022 7:15 AM, Ramalingam C wrote:
Capture the impact of memory region preference list of the objects, on
their memory residency and Flat-CCS capability.
v2:
Fix the Flat-CCS
== Series Details ==
Series: DG2 VRAM_SR Support (rev2)
URL : https://patchwork.freedesktop.org/series/104128/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: DG2 VRAM_SR Support (rev2)
URL : https://patchwork.freedesktop.org/series/104128/
State : warning
== Summary ==
Error: dim checkpatch failed
ee8880156960 drm/i915/dgfx: OpRegion VRAM Self Refresh Support
41f57c1513eb drm/i915/dg1: OpRegion PCON DG1 MBD config
== Series Details ==
Series: drm/i915: Individualize fences before adding to dma_resv obj (rev2)
URL : https://patchwork.freedesktop.org/series/104074/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11674 -> Patchwork_104074v2
On Tue, 2022-05-17 at 17:23 +0200, Hans de Goede wrote:
> Typically the acpi_video driver will initialize before nouveau, which
> used to cause /sys/class/backlight/acpi_video0 to get registered and then
> nouveau would register its own nv_backlight device later. After which
> the
On Wed, 2022-05-18 at 15:39 +, Sean Christopherson wrote:
> On Wed, May 18, 2022, Maxim Levitsky wrote:
> > On Wed, 2022-05-18 at 16:28 +0800, Chao Gao wrote:
> > > > struct kvm_arch {
> > > > @@ -1258,6 +1260,7 @@ struct kvm_arch {
> > > > hpa_t hv_root_tdp;
> > > >
On Wed, 2022-05-18 at 15:56 +, Sean Christopherson wrote:
> On Wed, Apr 27, 2022, Maxim Levitsky wrote:
> > These days there are too many AVIC/APICv inhibit
> > reasons, and it doesn't hurt to have some documentation
> > for them.
>
> Please wrap at ~75 chars.
>
> > Signed-off-by: Maxim
== Series Details ==
Series: series starting with [1/2] drm/i915/reg: fix undefined behavior due to
shift overflowing the constant
URL : https://patchwork.freedesktop.org/series/104122/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11673_full -> Patchwork_104122v1_full
Reviewed-by: Lyude Paul
Also, ack on this being pushed to drm-misc, along with any other patches I r-b
On Tue, 2022-05-17 at 17:23 +0200, Hans de Goede wrote:
> Before this commit when we want userspace to use the acpi_video backlight
> device we register both the GPU's native backlight device
Filed a new issue https://gitlab.freedesktop.org/drm/intel/-/issues/6038
igt@kms_flip@flip-vs-panning-interruptible@c-edp1 - dmesg-warn - rcu: INFO:
rcu_preempt detected stalls on CPUs/tasks
Thanks,
Lakshmi.
-Original Message-
From: Roper, Matthew D
Sent: Tuesday, May 17, 2022 8:24 PM
On 13/05/2022 02:36, Ashutosh Dixit wrote:
Extend pcode initialization to pcode on different gt's.
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_driver.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff
> Subject: [PATCH v2 00/14] GSC support for XeHP SDV and DG2 platforms
>
> Add GSC support for XeHP SDV and DG2 platforms.
>
> The series includes changes for the mei driver:
> - add ability to use polling instead of interrupts
> - add ability to use extended timeouts
> - setup extended
== Series Details ==
Series: i915: SSEU handling updates (rev4)
URL : https://patchwork.freedesktop.org/series/103244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11666_full -> Patchwork_103244v4_full
Summary
---
On Tue, May 17, 2022 at 02:29:05PM -0700, Swathi Dhanavanthri wrote:
> Signed-off-by: Swathi Dhanavanthri
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++
> 2 files changed, 11 insertions(+)
>
> diff --git
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, May 18, 2022 7:46 PM
> To: Gupta, Anshuman
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> Wilson, Chris P ; Vivi, Rodrigo
>
> Subject: Re: [Intel-gfx] [PATCH 7/7] drm/i915/rpm: Enable D3Cold VRAM SR
> Support
>
>
On Tue, 17 May 2022 at 21:45, Adrian Larumbe
wrote:
>
> This patch is a second attempt at eliminating the old shmem memory region
> and GEM object backend, in favour of a TTM-based one that is able to manage
> objects placed on both system and local memory.
>
> Questions addressed since previous
== Series Details ==
Series: series starting with [1/2] drm/i915/reg: fix undefined behavior due to
shift overflowing the constant
URL : https://patchwork.freedesktop.org/series/104122/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11673 -> Patchwork_104122v1
On Wed, May 18, 2022 at 06:37:16PM +0530, Anshuman Gupta wrote:
> Intel Client DGFX card supports D3Cold with two option.
> D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
>
> i915 requires to evict the lmem objects to smem in order to
> support D3Cold-Off, which increases i915 the suspend/resume
On Wed, 18 May 2022, Michal Wajdeczko wrote:
> On 18.05.2022 13:33, Jani Nikula wrote:
>> From: Borislav Petkov
>>
>> Fix:
>>
>> In file included from :0:0:
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function ‘intel_guc_send_mmio’:
>> ././include/linux/compiler_types.h:352:38: error:
On 18.05.2022 13:33, Jani Nikula wrote:
> From: Borislav Petkov
>
> Fix:
>
> In file included from :0:0:
> drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function ‘intel_guc_send_mmio’:
> ././include/linux/compiler_types.h:352:38: error: call to
> ‘__compiletime_assert_1047’ \
>
On 5/18/22 00:46, Arnd Bergmann wrote:
On Mon, May 16, 2022 at 3:19 PM Guenter Roeck wrote:
On 5/16/22 06:31, Greg KH wrote:
On Mon, May 16, 2022 at 06:10:23AM -0700, Guenter Roeck wrote:
On Mon, Feb 28, 2022 at 11:27:43AM +0100, Arnd Bergmann wrote:
From: Arnd Bergmann
During a patch
== Series Details ==
Series: series starting with [1/2] drm/i915/reg: fix undefined behavior due to
shift overflowing the constant
URL : https://patchwork.freedesktop.org/series/104122/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit
On Wed, 18 May 2022, Ville Syrjälä wrote:
> On Wed, May 18, 2022 at 02:33:14PM +0300, Jani Nikula wrote:
>> Use REG_GENMASK() and REG_FIELD_PREP() to avoid errors due to
>> -fsanitize=shift.
>
> I presume it's just unhappy about shifting into the sign bit?
Yeah, and apparently it also only
On Tue, May 03, 2022 at 03:22:07PM +0200, Juergen Gross wrote:
> Some drivers are using pat_enabled() in order to test availability of
> special caching modes (WC and UC-). This will lead to false negatives
> in case the system was booted e.g. with the "nopat" variant and the
> BIOS did setup the
Intel Client DGFX card supports D3Cold with two option.
D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support D3Cold-Off, which increases i915 the suspend/resume
latency. Enabling VRAM Self Refresh feature optimize the
latency with
DGFX uses similar PCODE MBOX interface as IGFX but
uses distinct COMMAND and PARAM set of bit fields.
Adding those headers Accordingly.
Cc: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
Add DG2 Motherboard Down Config check support.
BSpec: 44477
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 9 +
2 files changed, 11 insertions(+)
diff --git
DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable VRAM SR using ACPI OpRegion.
i915 requires to check OpRegion PCON MBD Config bits to
discover whether Gfx Card is MBD config before enabling
Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
opportunistic S0ix system wide suspend flow as well.
Without VRSR enablement i915 has to evict the lmem objects to
system memory. Depending on some heuristics driver
This series add DG2 D3Cold VRAM_SR support.
TODO: GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (7):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: DG2 MBD config
drm/i915/dgfx: Add has_lmem_sr
This series add DG2 D3Cold VRAM_SR support.
TODO: GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (7):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: DG2 MBD config
drm/i915/dgfx: Add has_lmem_sr
On Wed, May 18, 2022 at 03:05:44PM +0300, Lisovskiy, Stanislav wrote:
> On Wed, May 18, 2022 at 02:44:30PM +0300, Jani Nikula wrote:
> > On Wed, 18 May 2022, Stanislav Lisovskiy
> > wrote:
> > > Otherwise we seem to get FIFO underruns. It is being disabled
> > > anyway, so kind of logical to
On Wed, May 18, 2022 at 02:33:14PM +0300, Jani Nikula wrote:
> Use REG_GENMASK() and REG_FIELD_PREP() to avoid errors due to
> -fsanitize=shift.
I presume it's just unhappy about shifting into the sign bit?
Changes look correct:
Reviewed-by: Ville Syrjälä
>
> References:
_i915_vma_move_to_active() can receive > 1 fences for
multiple batch buffers submission. Because dma_resv_add_fence()
can only accept one fence at a time, change _i915_vma_move_to_active()
to be aware of multiple fences so that it can add individual
fences to the dma resv object.
v3:
On Wed, 2022-05-18 at 19:51 +0800, Chao Gao wrote:
> On Wed, May 18, 2022 at 12:50:27PM +0300, Maxim Levitsky wrote:
> > > > struct kvm_arch {
> > > > @@ -1258,6 +1260,7 @@ struct kvm_arch {
> > > > hpa_t hv_root_tdp;
> > > > spinlock_t hv_root_tdp_lock;
> > > > #endif
> > > > +
On Wed, May 18, 2022 at 02:44:30PM +0300, Jani Nikula wrote:
> On Wed, 18 May 2022, Stanislav Lisovskiy
> wrote:
> > Otherwise we seem to get FIFO underruns. It is being disabled
> > anyway, so kind of logical to write those as zeroes, even if
> > disabling is temporary.
> >
> > Signed-off-by:
== Series Details ==
Series: drm/i915: Write zero wms if we disable planes for icl+
URL : https://patchwork.freedesktop.org/series/104120/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11672 -> Patchwork_104120v1
Summary
On Wed, May 18, 2022 at 12:50:27PM +0300, Maxim Levitsky wrote:
>> > struct kvm_arch {
>> > @@ -1258,6 +1260,7 @@ struct kvm_arch {
>> >hpa_t hv_root_tdp;
>> >spinlock_t hv_root_tdp_lock;
>> > #endif
>> > + bool apic_id_changed;
>>
>> What's the value of this boolean? No one reads it.
On Wed, 18 May 2022, Jouni Högander wrote:
> Currently there is no mean to get understanding how psr is utilized.
> E.g. How much psr is actually enabled or how often driver falls back
> to full update.
>
> This patch addresses this by adding new debugfs interface
> i915_edp_psr_stats. Statistics
On Wed, 18 May 2022, Stanislav Lisovskiy wrote:
> Otherwise we seem to get FIFO underruns. It is being disabled
> anyway, so kind of logical to write those as zeroes, even if
> disabling is temporary.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../drm/i915/display/skl_universal_plane.c|
On Tue, 17 May 2022, "GONG, Ruiqi" wrote:
> Fix the compilation errors produced by building recent mainline on x86
> with allmodconfig:
>
> (1st type of errors)
> drivers/gpu/drm/i915/display/intel_ddi.c:1916:2: error: case label does not
> reduce to an integer constant
> case
On Wed, 18 May 2022, Borislav Petkov wrote:
> On Tue, May 17, 2022 at 04:05:46PM -0700, Randy Dunlap wrote:
>>
>>
>> On 4/5/22 08:15, Borislav Petkov wrote:
>> > From: Borislav Petkov
>> >
>> > Fix:
>> >
>> > In file included from :0:0:
>> > drivers/gpu/drm/i915/gt/uc/intel_guc.c: In
From: Borislav Petkov
Fix:
In file included from :0:0:
drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function ‘intel_guc_send_mmio’:
././include/linux/compiler_types.h:352:38: error: call to
‘__compiletime_assert_1047’ \
declared with attribute error: FIELD_PREP: mask is not constant
Use REG_GENMASK() and REG_FIELD_PREP() to avoid errors due to
-fsanitize=shift.
References: https://lore.kernel.org/r/20220405151517.29753-12...@alien8.de
Reported-by: Borislav Petkov
Reported-by: Ruiqi GONG
Cc: Randy Dunlap
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 32
== Series Details ==
Series: drm/i915: Write zero wms if we disable planes for icl+
URL : https://patchwork.freedesktop.org/series/104120/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+ ^
+ }
== Series Details ==
Series: drm/i915: Write zero wms if we disable planes for icl+
URL : https://patchwork.freedesktop.org/series/104120/
State : warning
== Summary ==
Error: dim checkpatch failed
ad72e46079ae drm/i915: Write zero wms if we disable planes for icl+
-:78: CHECK:LINE_SPACING:
== Series Details ==
Series: drm/i915: Debugfs statistics interface for psr
URL : https://patchwork.freedesktop.org/series/104115/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11671_full -> Patchwork_104115v1_full
Summary
Otherwise we seem to get FIFO underruns. It is being disabled
anyway, so kind of logical to write those as zeroes, even if
disabling is temporary.
Signed-off-by: Stanislav Lisovskiy
---
.../drm/i915/display/skl_universal_plane.c| 2 +-
drivers/gpu/drm/i915/intel_pm.c | 46
On Wed, 18 May 2022, Hans de Goede wrote:
> Hi,
>
> On 5/18/22 10:44, Jani Nikula wrote:
>> On Tue, 17 May 2022, Hans de Goede wrote:
>>> Hi All,
>>>
>>> As mentioned in my RFC titled "drm/kms: control display brightness through
>>> drm_connector properties":
>>>
Hi,
On 5/18/22 10:55, Jani Nikula wrote:
> On Tue, 17 May 2022, Hans de Goede wrote:
>> ATM on x86 laptops where we want userspace to use the acpi_video backlight
>> device we often register both the GPU's native backlight device and
>> acpi_video's firmware acpi_video# backlight device. This
Hi,
On 5/18/22 10:44, Jani Nikula wrote:
> On Tue, 17 May 2022, Hans de Goede wrote:
>> Hi All,
>>
>> As mentioned in my RFC titled "drm/kms: control display brightness through
>> drm_connector properties":
>> https://lore.kernel.org/dri-devel/0d188965-d809-81b5-74ce-7d30c49fe...@redhat.com/
>>
On Wed, 2022-05-18 at 16:28 +0800, Chao Gao wrote:
> On Wed, Apr 27, 2022 at 11:02:57PM +0300, Maxim Levitsky wrote:
> > Neither of these settings should be changed by the guest and it is
> > a burden to support it in the acceleration code, so just inhibit
> > it instead.
> >
> > Also add a
Hi,
On 17/05/2022 17:56, Yongzhi Liu wrote:
if drm_syncobj_fence_get return null, we will get a
null pointer. Fix this by adding the null pointer check
on fence.
Signed-off-by: Yongzhi Liu
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4
1 file changed, 4 insertions(+)
diff
On Tue, 17 May 2022, Hans de Goede wrote:
> ATM on x86 laptops where we want userspace to use the acpi_video backlight
> device we often register both the GPU's native backlight device and
> acpi_video's firmware acpi_video# backlight device. This relies on
> userspace preferring firmware type
On Tue, 17 May 2022, Hans de Goede wrote:
> Hi All,
>
> As mentioned in my RFC titled "drm/kms: control display brightness through
> drm_connector properties":
> https://lore.kernel.org/dri-devel/0d188965-d809-81b5-74ce-7d30c49fe...@redhat.com/
>
> The first step towards this is to deal with some
== Series Details ==
Series: drm/i915: Debugfs statistics interface for psr
URL : https://patchwork.freedesktop.org/series/104115/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11671 -> Patchwork_104115v1
Summary
---
On Wed, Apr 27, 2022 at 11:02:57PM +0300, Maxim Levitsky wrote:
>Neither of these settings should be changed by the guest and it is
>a burden to support it in the acceleration code, so just inhibit
>it instead.
>
>Also add a boolean 'apic_id_changed' to indicate if apic id ever changed.
>
With this the release_work in gvt can go away as well:
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 633acfcf76bf2..aee1a45da74bc 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -227,7 +227,6 @@ struct intel_vgpu {
Currently there is no mean to get understanding how psr is utilized.
E.g. How much psr is actually enabled or how often driver falls back
to full update.
This patch addresses this by adding new debugfs interface
i915_edp_psr_stats. Statistics gathering is started by writing 1/y/Y and
stopped by
> if (device->ops->flags & VFIO_DEVICE_NEEDS_KVM)
> {
Nit: this is not the normal brace placement.
But what is you diff against anyway? The one Matthew sent did away
with the VFIO_DEVICE_NEEDS_KVM flags, which does the wrong thing for
zpci, so it can't be that..
Also if we want to
Hi Imre,
> On Mon, May 16, 2022 at 01:54:02AM -0700, Vivek Kasireddy wrote:
> > Although, doing a modeset on any disconnected connector might be futile,
> > it can be particularly problematic if the connector is a Type-C port
> > without a sink. And, the spec only says "Display software must not
On 2022-05-13 at 14:06:11 -0700, Jordan Justen wrote:
> On 2022-05-13 05:31:00, Lionel Landwerlin wrote:
> > On 02/05/2022 17:15, Ramalingam C wrote:
> > > Capture the impact of memory region preference list of the objects, on
> > > their memory residency and Flat-CCS capability.
> > >
> > > v2:
>
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