On Thu, May 26, 2022 at 12:00:42PM -0700, Ashutosh Dixit wrote:
> Create a gt/gtN/.defaults directory (similar to
> engine//.defaults) to expose default parameter values for each
> gt in sysfs. This allows userspace to restore default parameter values
> after they may have changed.
Drive-by commen
From: Ville Syrjälä
Some machines declare DRRS type = seamless, DRRS = no, DMRRS = yes.
I *think* DMRRS stands for "dynamcic media refresh rate", and
I suspect the way it's meant to work is that it lets the driver
switch refresh rates to match the frame rate for media playback.
Obviously for us a
From: Ville Syrjälä
Add a bunch of new struff we're missing in various BDB blocks.
TODO: Bunch of these might actually need to be taken
into use...
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 50 ---
1 file changed, 43 insertions(+), 7 dele
From: Ville Syrjälä
Fix various typos around "aggressiveness". Note that
the VBT spec also sometimes missspells it as
"agressiveness" so I guess that's where some of the typos
came from.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8
1 file changed
From: Ville Syrjälä
It seem that when dealing with VRR capable eDP panels we need
to accept fixed modes with variable vblank length (which is what
VRR varies dynamically). Typically the preferred mode seems to be
a non-VRR more (lowish dotclock/refresh rate + short vblank).
We also have examples
From: Ville Syrjälä
VBT seems to have an extra flag for VRR vs. not. Let's consult
that for eDP panels.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bios.c | 5 +
.../drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display/intel_vrr.c
From: Ville Syrjälä
To help with debugging DRRS/VRR panel init let's dump out all
the fixed modes we rejected for whatever reason.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_panel.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/in
From: Ville Syrjälä
VRR panels generally declare modes with different timings instead
of just modes with different clocks that we get with DRRS panels.
Let's accept more fixed modes for VRR panels.
There are also funny machines that declare DMRRS support but not
DRRS support. Treating those as s
On Thu, May 26, 2022 at 11:18:17AM +0100, Tvrtko Ursulin wrote:
>
> On 25/05/2022 19:05, Matt Roper wrote:
> > On Wed, May 25, 2022 at 05:03:13PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 24/05/2022 18:51, Matt Roper wrote:
> > > > On Tue, May 24, 2022 at 10:43:39AM +0100, Tvrtko Ursulin wrote:
On Fri, May 27, 2022 at 01:10:46AM -0700, Lucas De Marchi wrote:
> This reverts commit bcefacd359f07dee18795dd80f834acb47fd21eb.
>
> IGT conversion is ready, so these execptions can already be removed.
> Once CI is clean, this commit will actually be removed from
> topic/core-for-CI.
>
> Signed-o
On Thu, May 26, 2022 at 03:22:13PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display/adl_p: Updates to HDMI combo PHY voltage swing table
> URL : https://patchwork.freedesktop.org/series/104393/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_
From: Stuart Summers
Bspec: 64027
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 61 ++---
drivers/gpu/drm/i915/i
For PVC, the base die and compute tile have separate stepping values
that we need to track; we'll use the existing graphics_step field to
represent the compute tile stepping and add a new 'basedie_step' field.
Unlike past platforms, steppings for these components are represented by
specific bitfie
Matt Roper (1):
drm/i915/pvc: Extract stepping information from PCI revid
Stuart Summers (1):
drm/i915/pvc: Add initial PVC workarounds
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 5 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 61 +
On 17.05.2022 21:39, Ruhl, Michael J wrote:
> >-Original Message-
> >From: Intel-gfx On Behalf Of
> >Adrian Larumbe
> >Sent: Tuesday, May 17, 2022 4:45 PM
> >To: dan...@ffwll.ch; intel-gfx@lists.freedesktop.org
> >Cc: adrian.laru...@collabora.com
> >Subject: [Intel-gfx] [RFC PATCH v2 1/1]
On 18.05.2022 16:00, Matthew Auld wrote:
> On Tue, 17 May 2022 at 21:45, Adrian Larumbe
> wrote:
> >
> > This patch is a second attempt at eliminating the old shmem memory region
> > and GEM object backend, in favour of a TTM-based one that is able to manage
> > objects placed on both system and l
== Series Details ==
Series: drm/i915: don't flush TLB on GEN8 (rev2)
URL : https://patchwork.freedesktop.org/series/104451/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11705_full -> Patchwork_104451v2_full
Summary
--
== Series Details ==
Series: Revert "drm/i915: Add relocation exceptions for two other platforms"
URL : https://patchwork.freedesktop.org/series/104449/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11705_full -> Patchwork_104449v1_full
== Series Details ==
Series: drm/i915: don't flush TLB on GEN8 (rev2)
URL : https://patchwork.freedesktop.org/series/104451/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11705 -> Patchwork_104451v2
Summary
---
**SUC
On 27.05.2022 09:24, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We have long standing customer complaints that pressing Ctrl-C (or to the
effect of) causes engine resets with otherwise well behaving programs.
Not only is logging engine resets during normal operation not desirable
since it crea
On Fri, 27 May 2022 11:55:42 +0100
Tvrtko Ursulin wrote:
> On 27/05/2022 10:09, Mauro Carvalho Chehab wrote:
> > i915 selftest hangcheck is causing the i915 driver timeouts, as
> > reported by Intel CI:
> >
> >
> > http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a9
On 5/27/2022 1:37 PM, Matthew Auld wrote:
On 27/05/2022 11:24, Das, Nirmoy wrote:
On 5/27/2022 11:55 AM, Matthew Auld wrote:
On 27/05/2022 10:46, Das, Nirmoy wrote:
On 5/26/2022 11:27 AM, Matthew Auld wrote:
On 25/05/2022 10:59, Nirmoy Das wrote:
_i915_vma_move_to_active() can receive >
On 27/05/2022 11:24, Das, Nirmoy wrote:
On 5/27/2022 11:55 AM, Matthew Auld wrote:
On 27/05/2022 10:46, Das, Nirmoy wrote:
On 5/26/2022 11:27 AM, Matthew Auld wrote:
On 25/05/2022 10:59, Nirmoy Das wrote:
_i915_vma_move_to_active() can receive > 1 fences for
multiple batch buffers submissio
== Series Details ==
Series: Revert "drm/i915: Add relocation exceptions for two other platforms"
URL : https://patchwork.freedesktop.org/series/104449/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11705 -> Patchwork_104449v1
==
On 27/05/2022 10:09, Mauro Carvalho Chehab wrote:
i915 selftest hangcheck is causing the i915 driver timeouts, as
reported by Intel CI:
http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4
When such test runs, the only outpu
From: Tvrtko Ursulin
Be nice and explicitly free all memory on exit.
Also fix a Valgrind reported unitilised conditional jump.
Signed-off-by: Tvrtko Ursulin
Cc: Petri Latvala
---
tools/intel_gpu_top.c | 51 +++
1 file changed, 42 insertions(+), 9 delet
From: Tvrtko Ursulin
Ensure buffer is null terminated at the point where the read ended and not
at the end of the whole buffer. Otherwise string parsing can stray into
un-initialised memory.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 8
lib/igt_drm_fdinfo.h | 4 ++--
2 f
From: Tvrtko Ursulin
Fix a possible oversight.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_device_scan.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/lib/igt_device_scan.c b/lib/igt_device_scan.c
index 3c23fe0eb520..a30433ae2cff 100644
--- a/lib/igt_device_scan.c
+++ b/lib/igt_device
On 5/27/2022 11:55 AM, Matthew Auld wrote:
On 27/05/2022 10:46, Das, Nirmoy wrote:
On 5/26/2022 11:27 AM, Matthew Auld wrote:
On 25/05/2022 10:59, Nirmoy Das wrote:
_i915_vma_move_to_active() can receive > 1 fences for
multiple batch buffers submission. Because dma_resv_add_fence()
can only
On 27/05/2022 10:46, Das, Nirmoy wrote:
On 5/26/2022 11:27 AM, Matthew Auld wrote:
On 25/05/2022 10:59, Nirmoy Das wrote:
_i915_vma_move_to_active() can receive > 1 fences for
multiple batch buffers submission. Because dma_resv_add_fence()
can only accept one fence at a time, change _i915_vma_
== Series Details ==
Series: drm/i915: don't flush TLB on GEN8 (rev2)
URL : https://patchwork.freedesktop.org/series/104451/
State : warning
== Summary ==
Error: dim checkpatch failed
5a0ff8197012 drm/i915: don't flush TLB on GEN8
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit de
GFX-CI will be quieting down today for hardware migration.
New builds will be stopped soon to drain the shard queue.
Existing results on https://intel-gfx-ci.01.org/ will be available
during migration.
CI data migration is estimated to take two days. After syncing,
functional testing will proceed.
On 5/26/2022 11:27 AM, Matthew Auld wrote:
On 25/05/2022 10:59, Nirmoy Das wrote:
_i915_vma_move_to_active() can receive > 1 fences for
multiple batch buffers submission. Because dma_resv_add_fence()
can only accept one fence at a time, change _i915_vma_move_to_active()
to be aware of multiple
On 27/05/2022 09:52, Petri Latvala wrote:
On Fri, May 27, 2022 at 08:53:04AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
On kernels without support for the feature we should skip showing the
clients header to avoid confusing users.
Simply briefly open a render node to the selected dev
== Series Details ==
Series: drm/i915: Improve user experience and driver robustness under SIGINT or
similar
URL : https://patchwork.freedesktop.org/series/10/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11705 -> Patchwork_10v1
==
i915 selftest hangcheck is causing the i915 driver timeouts, as
reported by Intel CI:
http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4
When such test runs, the only output is:
[ 68.811639] i915: Performing live se
From: Mauro Carvalho Chehab
i915 selftest hangcheck is causing the i915 driver timeouts, as
reported by Intel CI:
http://gfx-ci.fi.intel.com/cibuglog-ng/issuefilterassoc/24297?query_key=42a999f48fa6ecce068bc8126c069be7c31153b4
When such test runs, the only output is:
[ 68.81
On Fri, May 27, 2022 at 08:53:04AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> On kernels without support for the feature we should skip showing the
> clients header to avoid confusing users.
>
> Simply briefly open a render node to the selected device during init and
> look if the r
This reverts commit bcefacd359f07dee18795dd80f834acb47fd21eb.
IGT conversion is ready, so these execptions can already be removed.
Once CI is clean, this commit will actually be removed from
topic/core-for-CI.
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21
From: Tvrtko Ursulin
On kernels without support for the feature we should skip showing the
clients header to avoid confusing users.
Simply briefly open a render node to the selected device during init and
look if the relevant fields are present in the fdinfo data.
Signed-off-by: Tvrtko Ursulin
== Series Details ==
Series: drm/i915: Improve user experience and driver robustness under SIGINT or
similar
URL : https://patchwork.freedesktop.org/series/10/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separa
From: Tvrtko Ursulin
We have long standing customer complaints that pressing Ctrl-C (or to the
effect of) causes engine resets with otherwise well behaving programs.
Not only is logging engine resets during normal operation not desirable
since it creates support incidents, but more fundamentally
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