On 08/06/2022 22:32, Niranjana Vishwanathapura wrote:
On Wed, Jun 08, 2022 at 10:12:05AM +0100, Matthew Auld wrote:
On 08/06/2022 08:17, Tvrtko Ursulin wrote:
On 07/06/2022 20:37, Niranjana Vishwanathapura wrote:
On Tue, Jun 07, 2022 at 11:27:14AM +0100, Tvrtko Ursulin wrote:
On 17/05/2022
FWIW, I found that reverting the two drm merges (with `git revert -m`)
from 5.19-rc1 "fixed" the issue.
Hi,
Please file issue at:
https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs
Br,
Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
> -Original Message-
> From: Intel-gfx On Behalf Of Jason
> A.
> Donenfeld
> Sent: torstai 9. kesäkuut
Done. https://gitlab.freedesktop.org/drm/intel/-/issues/6205
Hi Daniel, Dave,
Here's this week drm-misc-fixes PR
Maxime
drm-misc-fixes-2022-06-09:
One fix to handle DT errors in ti-sn65dsi83, a fix for a use-after-free in
panfrost, two fixes for panel self-refresh handling, and one to fix
multiple output support on AST.
The following changes since commit
== Series Details ==
Series: drm/i915/pvc: Add register steering (rev2)
URL : https://patchwork.freedesktop.org/series/104691/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11740_full -> Patchwork_104691v2_full
Summary
On Thu, Jun 09, 2022 at 02:17:54PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Add register steering (rev2)
> URL : https://patchwork.freedesktop.org/series/104691/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11740_full -> Patchwork_104
On 09/06/2022 00:55, Jason Ekstrand wrote:
On Wed, Jun 8, 2022 at 4:44 PM Niranjana Vishwanathapura
wrote:
On Wed, Jun 08, 2022 at 08:33:25AM +0100, Tvrtko Ursulin wrote:
>
>
>On 07/06/2022 22:32, Niranjana Vishwanathapura wrote:
>>On Tue, Jun 07, 2022 at 11:18:11AM -0700,
This series refactors i915's internal buffer backend to use ttm.
It uses ttm's pool allocator to allocate volatile pages in place of the
old code which rolled its own via alloc_pages.
This is continuing progress to align all backends on using ttm.
v2: - commit message improvements to add detai
Various places within the driver override the default chosen cache_level.
Before ttm, these overrides were permanent until explicitly changed again
or for the lifetime of the buffer.
TTM movement code came along and decided that it could make that
decision at that time, which is usually well after
Internal gem objects will soon just be volatile system memory region
objects.
To enable this, create a separate dummy object creation function
for gen6 ppgtt. The object only exists as a fake object pointing to ggtt
and gains no benefit in going via the internal backend.
Instead, create a dummy gem
Internal/volatile buffers should not be shmem backed.
If a volatile buffer is requested, allow ttm to use the pool allocator
to provide volatile pages as backing.
Fix i915_ttm_shrink to handle !is_shmem volatile buffers by purging.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/gem/i915_
By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
This is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable and bsw via
ggtt mappings, so limit DGFX for now and maintain previous behaviour.
Signed-of
i965G[M] cannot relocate objects above 4GiB.
Ensure ttm uses dma32 on these systems.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/intel_region_ttm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c
b/drivers/gpu/drm/i915
Reorder scratch page allocation so that memory regions are available
to allocate the buffers
Signed-off-by: Robert Beckett
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 20 ++--
drivers/gpu/drm/i915/gt/intel_gt_gmch.h | 6 ++
drivers/gpu/drm/i9
In commit 450cede7f380 ("drm/i915/gem: Fix the mman selftest") we fixed up
the mman selftest to allocate user buffers via smem only if we have lmem,
otherwise it uses internal buffers.
As the commit message asserts, we should only be using buffers that
userland should be able to create.
Internal b
Create a kernel only internal memory region that uses ttm pool allocator to
allocate volatile system pages.
Refactor internal buffer backend to simply allocate from this new
region.
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 187 +-
drivers/
== Series Details ==
Series: drm/i915/display: Fix handling of enable_psr parameter
URL : https://patchwork.freedesktop.org/series/104907/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11740_full -> Patchwork_104907v1_full
== Series Details ==
Series: drm/i915: ttm for internal (rev2)
URL : https://patchwork.freedesktop.org/series/104909/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Each LFP may have different panel type which is stored in LFP data
data block. Based on the child device index respective panel-type/
panel-type2 field will be used.
v1: Initial rfc verion.
v2: Based on review comments from Jani,
- Used panel-type instead addition panel-index variable.
- DEVICE_HA
On Thu, Jun 09, 2022 at 09:36:48AM +0100, Matthew Auld wrote:
On 08/06/2022 22:32, Niranjana Vishwanathapura wrote:
On Wed, Jun 08, 2022 at 10:12:05AM +0100, Matthew Auld wrote:
On 08/06/2022 08:17, Tvrtko Ursulin wrote:
On 07/06/2022 20:37, Niranjana Vishwanathapura wrote:
On Tue, Jun 07, 2
On Thu, 2022-06-09 at 17:01 +, Patchwork wrote:
Patch Details
Series: drm/i915/display: Fix handling of enable_psr parameter
URL:https://patchwork.freedesktop.org/series/104907/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104907v1/index.html
CI Bug Lo
On Thu, Jun 09, 2022 at 05:49:09PM +0300, Lionel Landwerlin wrote:
On 09/06/2022 00:55, Jason Ekstrand wrote:
On Wed, Jun 8, 2022 at 4:44 PM Niranjana Vishwanathapura
wrote:
On Wed, Jun 08, 2022 at 08:33:25AM +0100, Tvrtko Ursulin wrote:
>
>
>On 07/06/2022 22:
== Series Details ==
Series: drm/i915: ttm for internal (rev2)
URL : https://patchwork.freedesktop.org/series/104909/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11749 -> Patchwork_104909v2
Summary
---
**SUCCESS**
The following changes since commit 02c69863c885db963f8c0121b533f2816ef5be3b:
rtl_bt: Update RTL8852A BT USB firmware to 0xDFB8_0634 (2022-06-07 08:32:39
-0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dg2_huc_7.10.0
for you to fetch changes up
Instead of always falling back to memcpy_fromio() for any size, prefer
using read{b,w,l}(). When reading struct members it's common to read
individual integer variables individually. Going through memcpy_fromio()
for each of them poses a high penalty.
Employ a similar trick as __seqprop() by using
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
operation itself is relatively simple (just send a message to the GSC
with the physical address of the HuC in LMEM), but there are timing
changes that requires special attention. In particular, to send a PXP
command we need to
This is a squash of the GSC support for XeHP SDV and DG2 series, which
is being reviewed separately at:
https://patchwork.freedesktop.org/series/102339/
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 119 +---
drivers/gpu/drm/i915/gt/intel
From: Vitaly Lubart
Add gsc command to the mei client bus API.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Cc: Daniele Ceraolo Spurio
---
drivers/misc/mei/bus.c | 125 +
include/linux/mei_cl_bus.h | 6 ++
2 files changed, 131 insertions
From: Vitaly Lubart
Adding command streamer API to the PXP driver
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Cc: Daniele Ceraolo Spurio
---
drivers/misc/mei/pxp/mei_pxp.c | 27 +++
include/drm/i915_pxp_tee_interface.h | 5 +
2 files changed,
From: Tomas Winkler
Support matching with a discrete graphics card.
Signed-off-by: Tomas Winkler
Cc: Vitaly Lubart
---
drivers/misc/mei/pxp/mei_pxp.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_px
From: Vitaly Lubart
Command to be sent via the stream interface are written to a local
memory page, whose address is then provided to the GSC.
The interface supports providing a full sg with multiple pages for both
input and output messages, but since for now we only aim to support short
and sync
From: Tomas Winkler
Add support for loading HuC via a pxp stream command.
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
---
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 6 ++
drivers/gpu/drm/i915/i915_request.c| 24
2 files changed, 30 insertions(+
The media driver uses this only as an indication that HuC is enabled and
they have a secondary check within their batches to verify if the HuC
is indeed loaded or not. They have therefore requested us to report this
as true if HuC loading is in progress.
Signed-off-by: Daniele Ceraolo Spurio
Cc:
The GSC will perform both the load and teh authentication, so we just
need to check the auth bit after the GSC has replied.
Since we require the PXP module to load the HuC, the earliest we can
trigger the load is during the pxp_bind operation.
Note that GSC-loaded HuC survives GT reset, so we need
The mei_pxp module is required to send the command to load authenticate
the HuC to the GSC even if pxp is not in use for protected content
management.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 10 +++---
drivers/gpu/drm/i915/pxp/int
From: Tomas Winkler
GSC extend header is of variable size and data
is provided in a sgl list inside the header
and not in the data buffers, need to enable the path.
Signed-off-by: Tomas Winkler
Cc: Vitaly Lubart
---
drivers/misc/mei/client.c| 55 --
drivers
From: Tomas Winkler
GSC command is and extended header containing a scatter gather
list and without a data buffer. Using MEI_CL_IO_SGL flag,
the caller send the GSC command as a data and the function internally
moves it to the extended header.
Signed-off-by: Tomas Winkler
Cc: Vitaly Lubart
---
The fw name is different and we need to record the fact that the blob is
gsc-loaded, so add a new macro to help.
Note: A-step DG2 G10 does not support HuC loading via GSC and would
require a separate firmware to be loaded the legacy way, but that's
not a production stepping so we're not going to b
Both are required for HuC loading.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Kconfig.debug | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..a6576ffbc4dc 100644
--- a/drivers/gpu
Given that HuC load is delayed on DG2, this patch adds support for a fence
that can be used to wait for load completion. No waiters are added in this
patch (they're coming up in the next one), to keep the focus of the
patch on the tracking logic.
The full HuC loading flow on boot DG2 is as follows
== Series Details ==
Series: iosys-map: Add word-sized reads
URL : https://patchwork.freedesktop.org/series/104947/
State : warning
== Summary ==
Error: dim checkpatch failed
9f93e9ff5930 iosys-map: Add word-sized reads
-:38: WARNING:TYPO_SPELLING: 'accidentaly' may be misspelled - perhaps
'a
== Series Details ==
Series: iosys-map: Add word-sized reads
URL : https://patchwork.freedesktop.org/series/104947/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 5/10/2022 3:14 PM, Nerlige Ramappa, Umesh wrote:
From: Umesh Nerlige Ramappa
For execlists backend, current implementation of Wa_22011802037 is to
stop the CS before doing a reset of the engine. This WA was further
extended to wait for any pending MI FORCE WAKEUPs before issuing a
reset.
== Series Details ==
Series: HuC loading for DG2
URL : https://patchwork.freedesktop.org/series/104949/
State : warning
== Summary ==
Error: dim checkpatch failed
458d50370348 HAX: mei: GSC support for XeHP SDV and DG2 platform
Traceback (most recent call last):
File "scripts/spdxcheck.py",
== Series Details ==
Series: HuC loading for DG2
URL : https://patchwork.freedesktop.org/series/104949/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Umesh Nerlige Ramappa
In addition, extend the WA to gen11.
v2: (Tvrtko)
- Clarify comments, commit message, fix typos
- Use IS_GRAPHICS_VER for gen 11/12 checks
v3: (Daneile)
- Drop changes to intel_ring_submission since WA does not apply to it
- Log an error if MSG IDLE is not defined fo
From: Umesh Nerlige Ramappa
For execlists backend, current implementation of Wa_22011802037 is to
stop the CS before doing a reset of the engine. This WA was further
extended to wait for any pending MI FORCE WAKEUPs before issuing a
reset. Add the extended steps in the execlist path of reset.
In
Commit title messed up, please ignore this one.
Umesh
On Thu, Jun 09, 2022 at 05:24:54PM -0700, Nerlige Ramappa, Umesh wrote:
From: Umesh Nerlige Ramappa
In addition, extend the WA to gen11.
v2: (Tvrtko)
- Clarify comments, commit message, fix typos
- Use IS_GRAPHICS_VER for gen 11/12 checks
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
include/uapi/linux/dma-buf.h
between commit:
7c3e9fcad9c7 ("dma-buf: fix use of DMA_BUF_SET_NAME_{A,B} in userspace")
from Linus' tree and commits:
20e10881a043 ("dma-buf: Add an API for exporting sync files (v14)"
== Series Details ==
Series: drm/i915/reset: Add additional steps for Wa_22011802037 for execlist
backend (rev2)
URL : https://patchwork.freedesktop.org/series/103837/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked se
On Wed, Jun 08, 2022 at 12:24:04PM +0100, Matthew Auld wrote:
On Tue, 17 May 2022 at 19:32, Niranjana Vishwanathapura
wrote:
Add some missing i915 upai documentation which the new
i915 VM_BIND feature documentation will be refer to.
Signed-off-by: Niranjana Vishwanathapura
---
include/uapi/
Hi Lucas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[also build test ERROR on linus/master v5.19-rc1 next-20220609]
[cannot apply to tegra-drm/drm/tegra/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when
== Series Details ==
Series: drm/i915/bios: calculate panel type as per child device index in VBT
URL : https://patchwork.freedesktop.org/series/104943/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11749 -> Patchwork_104943v1
==
Hi all,
After merging the drm-misc tree, today's linux-next build (powerpc
allyesconfig) failed like this:
drivers/firmware/efi/sysfb_efi.c:29:10: fatal error: asm/efi.h: No such file or
directory
29 | #include
| ^~~
Caused by commit
fa0e256450f2 ("fbdev: vesafb: A
The i915 KMD will use the first async flip to update the watermarks as
per the watermark optimization in DISPLAY13. Hence the actual async flip
will happen from the subsequent flips.
For alternate sync async test, a dummy async flip has to be done to
allow the KMD to perform the watermark related u
On 09/06/2022 22:31, Niranjana Vishwanathapura wrote:
On Thu, Jun 09, 2022 at 05:49:09PM +0300, Lionel Landwerlin wrote:
On 09/06/2022 00:55, Jason Ekstrand wrote:
On Wed, Jun 8, 2022 at 4:44 PM Niranjana Vishwanathapura
wrote:
On Wed, Jun 08, 2022 at 08:33:25AM +0100, Tvrtko
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