[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Try not to screw up the pps during panel probe

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915: Try not to screw up the pps during panel probe URL : https://patchwork.freedesktop.org/series/109392/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12214_full -> Patchwork_109392v1_full

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj URL : https://patchwork.freedesktop.org/series/109389/ State : success == Summary == CI Bug Log - changes from CI_DRM_12214_full -> Patchwork_109389v1_full

Re: [Intel-gfx] [PATCH 14/16] drm/i915/vm_bind: Handle persistent vmas in execbuf3

2022-10-04 Thread Niranjana Vishwanathapura
On Mon, Oct 03, 2022 at 09:36:38AM +0100, Matthew Auld wrote: On 02/10/2022 07:28, Niranjana Vishwanathapura wrote: On Fri, Sep 30, 2022 at 10:47:48AM +0100, Matthew Auld wrote: On 28/09/2022 07:19, Niranjana Vishwanathapura wrote: Handle persistent (VM_BIND) mappings during the request submis

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add MTP ddc pin configuration

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915/mtl: Add MTP ddc pin configuration URL : https://patchwork.freedesktop.org/series/109406/ State : success == Summary == CI Bug Log - changes from CI_DRM_12216 -> Patchwork_109406v1 Summary --- **

Re: [Intel-gfx] [PATCH v2 12/14] drm/i915: Define multicast registers as a new type

2022-10-04 Thread Matt Roper
On Tue, Oct 04, 2022 at 04:00:57PM +0300, Jani Nikula wrote: > On Tue, 04 Oct 2022, Jani Nikula wrote: > > On Fri, 30 Sep 2022, Matt Roper wrote: > >> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h > >> b/drivers/gpu/drm/i915/i915_reg_defs.h > >> index 8f486f77609f..e823869b9afd 100644 > >> -

[Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree

2022-10-04 Thread Stephen Rothwell
Hi all, Today's linux-next merge of the drm-misc tree got a conflict in: include/drm/drm_edid.h between commit: c7943bb324e5 ("drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets") from Linus' tree and commit: afd4429eba28 ("drm/edid: Define more flags") from the drm-misc tree.

[Intel-gfx] [PATCH] drm/i915/mtl: Add MTP ddc pin configuration

2022-10-04 Thread Radhakrishna Sripada
Meteorlake PCH reuses Alderlake ddc pin mapping. Extend ADL-P pin mapping for Meteorlake. Cc: Lucas De Marchi Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_

Re: [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/slpc: Update frequency debugfs for SLPC (rev3)

2022-10-04 Thread Belgaumkar, Vinay
On 10/4/2022 4:33 PM, Patchwork wrote: == Series Details == Series: drm/i915/slpc: Update frequency debugfs for SLPC (rev3) URL : https://patchwork.freedesktop.org/series/109328/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh CALLscripts/atomic/

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/slpc: Update frequency debugfs for SLPC (rev3)

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915/slpc: Update frequency debugfs for SLPC (rev3) URL : https://patchwork.freedesktop.org/series/109328/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK

[Intel-gfx] [PATCH v2 2/2] drm/i915/slpc: Update the frequency debugfs

2022-10-04 Thread Vinay Belgaumkar
Read the values stored in the SLPC structures. Remove the fields that are no longer valid (like RPS interrupts) as well. v2: Move all functionality changes to this patch (Jani) Signed-off-by: Vinay Belgaumkar --- drivers/gpu/drm/i915/gt/intel_rps.c | 46 - 1 file cha

[Intel-gfx] [PATCH v2 1/2] drm/i915: Add a wrapper for frequency debugfs

2022-10-04 Thread Vinay Belgaumkar
Move it to the RPS source file. v2: Separate out code movement and functional changes (Jani) Signed-off-by: Vinay Belgaumkar --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 157 + drivers/gpu/drm/i915/gt/intel_rps.c | 163 ++ drivers/gpu/drm/i915/gt

[Intel-gfx] [PATCH v2 0/2] drm/i915/slpc: Update frequency debugfs for SLPC

2022-10-04 Thread Vinay Belgaumkar
Remove the RPS related information that is not valid when SLPC is enabled. v2: Add version numbers and address other comments (Jani) Signed-off-by: Vinay Belgaumkar Vinay Belgaumkar (2): drm/i915: Add a wrapper for frequency debugfs drm/i915/slpc: Update the frequency debugfs drivers/gpu/

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add a wrapper for frequency debugfs

2022-10-04 Thread Belgaumkar, Vinay
On 10/4/2022 12:36 AM, Jani Nikula wrote: On Mon, 03 Oct 2022, Vinay Belgaumkar wrote: Move it to the RPS source file. The idea was that the 1st patch would be non-functional code movement. This is still a functional change. Or you can do the functional changes first, and then move code, as

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable SDP split for DP2.0

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915: Enable SDP split for DP2.0 URL : https://patchwork.freedesktop.org/series/109395/ State : success == Summary == CI Bug Log - changes from CI_DRM_12215 -> Patchwork_109395v1 Summary --- **SUCCESS

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Clean up some namespacing

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915: Clean up some namespacing URL : https://patchwork.freedesktop.org/series/109393/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12214 -> Patchwork_109393v1 Summary --- **FAILURE*

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Extend PSR support

2022-10-04 Thread Sripada, Radhakrishna
Merged the patch. Thank you for the patch and review. - Radhakrishna(RK) Sripada > -Original Message- > From: Intel-gfx On Behalf Of > Lisovskiy, Stanislav > Sent: Friday, September 23, 2022 1:09 AM > To: Kahola, Mika > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PAT

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Try not to screw up the pps during panel probe

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915: Try not to screw up the pps during panel probe URL : https://patchwork.freedesktop.org/series/109392/ State : success == Summary == CI Bug Log - changes from CI_DRM_12214 -> Patchwork_109392v1 Summary

Re: [Intel-gfx] [PATCH v2 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3

2022-10-04 Thread Niranjana Vishwanathapura
On Mon, Oct 03, 2022 at 01:18:27PM +0100, Matthew Auld wrote: On 03/10/2022 07:12, Niranjana Vishwanathapura wrote: Handle persistent (VM_BIND) mappings during the request submission in the execbuf3 path. v2: Ensure requests wait for bindings to complete. Signed-off-by: Niranjana Vishwanathapu

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj URL : https://patchwork.freedesktop.org/series/109389/ State : success == Summary == CI Bug Log - changes from CI_DRM_12214 -> Patchwork_109389v1 ==

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj URL : https://patchwork.freedesktop.org/series/109389/ State : warning == Summary == Error: dim checkpatch failed bc460e1488f8 drm/i915: remove the TODO in pin_and_fence_fb_obj 59ce306

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj URL : https://patchwork.freedesktop.org/series/109389/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separa

Re: [Intel-gfx] [PATCH] drm/i915/display/lspcon: Increase LSPCON mode settle timeout

2022-10-04 Thread Jani Nikula
On Thu, 15 Sep 2022, Pablo Ceballos wrote: > On some devices the Parade PS175 takes more than 400ms to settle in PCON > mode. Got any bug report with more info, or any other details to back this up? This is kind of thin. What's the 800 ms based on? BR, Jani. > > Signed-off-by: Pablo Ceballos

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 URL : https://patchwork.freedesktop.org/series/109384/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12210_full -> Patchwork_109384v1_full =

Re: [Intel-gfx] [PATCH v2 0/4] Fix HFVSDB parsing

2022-10-04 Thread Jani Nikula
On Fri, 16 Sep 2022, Ankit Nautiyal wrote: > Fix issues in HFVSDB parsing for DSC support. > Also minor refactoring in Logging. > > Split from original patch into a new series. > https://patchwork.freedesktop.org/patch/495193/ > > v2: Minor styling fixes. Thanks for the patches, pushed to drm-mis

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Document and future-proof preemption control policy

2022-10-04 Thread Matt Roper
On Thu, Sep 08, 2022 at 05:06:02AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Document and future-proof preemption control policy > URL : https://patchwork.freedesktop.org/series/108275/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_12090_fu

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj URL : https://patchwork.freedesktop.org/series/109382/ State : success == Summary == CI Bug Log - changes from CI_DRM_12210_full -> Patchwork_109382v1_full

[Intel-gfx] [PATCH] drm/i915: Enable SDP split for DP2.0

2022-10-04 Thread Vinod Govindapillai
Enable the SDP split configuration for DP2.0. v2: Move the register handling out of compute config function (JaniN) v3: Patch styling and register access based on platform support (JaniN) Bspec: 67768 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_audio.c| 12 +++

[Intel-gfx] [PATCH i-g-t v2 4/5] tests/i915/query: sanity check reported GTT alignment

2022-10-04 Thread Matthew Auld
Ensure the kernel is reporting "normal" values here, based on our current expectations. v2: - Split the rsvd0 check out, so we can in theory land that patch by itself (since that will fix the kernel failure vs old igt and could be merged early). - s/4096/PAGE_SIZE/ (Nirmoy) Signed-off-by:

[Intel-gfx] [PATCH i-g-t v2 5/5] tests/i915/gem_create: add some basic testing for GTT alignment

2022-10-04 Thread Matthew Auld
Make sure we can always place an object at some GTT address, so long as we adhere to the min GTT alignment for the given region. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- tests/i915/gem_create.c | 117 1 f

[Intel-gfx] [PATCH i-g-t v2 3/5] tests/i915/query: stop checking rsvd0 in region info

2022-10-04 Thread Matthew Auld
No longer reserved, in the near future this will be the GTT alignment. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- tests/i915/i915_query.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index

[Intel-gfx] [PATCH i-g-t v2 2/5] tests/i915/query: fix igt_assert_eq_u32

2022-10-04 Thread Matthew Auld
rsvd1 is u64 here. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- tests/i915/i915_query.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 2744421c..b92d7593 100644 --- a/tests

[Intel-gfx] [PATCH i-g-t v2 1/5] i915_drm.h sync

2022-10-04 Thread Matthew Auld
Get the small-bar related stuff at: 525e93f6317a ("drm/i915/uapi: add NEEDS_CPU_ACCESS hint"), and drop the local related bits. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- include/drm-uapi/i915_drm.h| 182 + lib/

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Fix revocation of non-persistent contexts

2022-10-04 Thread Ceraolo Spurio, Daniele
On 10/4/2022 4:14 AM, Tvrtko Ursulin wrote: On 03/10/2022 13:16, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Patch which added graceful exit for non-persistent contexts missed the fact it is not enough to set the exiting flag on a context and let the backend handle it from there. GuC backe

Re: [Intel-gfx] [PATCH] drm/i915: Clean up some namespacing

2022-10-04 Thread Jani Nikula
On Tue, 04 Oct 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > Rename a few functions from intel_crtc_foo_init() to > intel_foo_crtc_init() so that the namespaec clearly > indicates what feature/file we're talking about. > > If left out intel_crtc_crc_init() because the whole crc *I > stuf

Re: [Intel-gfx] [PATCH 0/2] drm/i915: Try not to screw up the pps during panel probe

2022-10-04 Thread Jani Nikula
On Tue, 04 Oct 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > I had to stare at the pps stuff again while dealing with the -stable > pps regression. While doing that I figured I'd try to make it so we > don't accidentally use the wrong pps during the panle probe when we > don't yet have the

[Intel-gfx] [PATCH] drm/i915: Clean up some namespacing

2022-10-04 Thread Ville Syrjala
From: Ville Syrjälä Rename a few functions from intel_crtc_foo_init() to intel_foo_crtc_init() so that the namespaec clearly indicates what feature/file we're talking about. If left out intel_crtc_crc_init() because the whole crc stuff uses intel_crtc_ as its namespace currently. Suggested-by:

[Intel-gfx] [PATCH 2/2] drm/i915: Try to use the correct power sequencer initially on bxt/glk

2022-10-04 Thread Ville Syrjala
From: Ville Syrjälä Currently on bxt/glk we just grab the power sequencer index from the VBT data even though it may not have been parsed yet. That could lead us to using the incorrect power sequencer during the initial panel probe. To avoid that let's try to read out the current state of the po

[Intel-gfx] [PATCH 1/2] drm/i915: Generalize the PPS vlv_pipe_check() stuff

2022-10-04 Thread Ville Syrjala
From: Ville Syrjälä Restate the vlv_pipe_check() stuff in terms of PPS index (rather than pipe, which it is on VLV/CHV) so that we can reuse this same mechanim on other platforms as well. Cc: Animesh Manna Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_pps.c | 27

[Intel-gfx] [PATCH 0/2] drm/i915: Try not to screw up the pps during panel probe

2022-10-04 Thread Ville Syrjala
From: Ville Syrjälä I had to stare at the pps stuff again while dealing with the -stable pps regression. While doing that I figured I'd try to make it so we don't accidentally use the wrong pps during the panle probe when we don't yet have the VBT parsed. So here's an attempt at deducing the corr

Re: [Intel-gfx] Regression on 5.19.12, display flickering on Framework laptop

2022-10-04 Thread Greg Kroah-Hartman
On Tue, Oct 04, 2022 at 04:44:35PM +0300, Ville Syrjälä wrote: > On Tue, Oct 04, 2022 at 03:40:55PM +0200, Greg Kroah-Hartman wrote: > > On Tue, Oct 04, 2022 at 06:46:10AM -0500, David Matthew Mattli wrote: > > > Thorsten Leemhuis writes: > > > > > > > On 03.10.22 19:48, Ville Syrjälä wrote: > > >

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment

2022-10-04 Thread Das, Nirmoy
On 10/4/2022 1:49 PM, Matthew Auld wrote: On some platforms we potentially have different alignment restrictions depending on the memory type. We also now have different alignment restrictions for the same region across different kernel versions. Extend the region query to return the minimum re

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Don't use port enum as register offset (rev8)

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915/display: Don't use port enum as register offset (rev8) URL : https://patchwork.freedesktop.org/series/108833/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12211 -> Patchwork_108833v8 S

Re: [Intel-gfx] Regression on 5.19.12, display flickering on Framework laptop

2022-10-04 Thread Ville Syrjälä
On Tue, Oct 04, 2022 at 03:40:55PM +0200, Greg Kroah-Hartman wrote: > On Tue, Oct 04, 2022 at 06:46:10AM -0500, David Matthew Mattli wrote: > > Thorsten Leemhuis writes: > > > > > On 03.10.22 19:48, Ville Syrjälä wrote: > > >> On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote: > > >>>

Re: [Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

2022-10-04 Thread Das, Nirmoy
On 10/4/2022 3:19 PM, Matthew Auld wrote: For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place in the mappable part of lmem, which becomes necessary on small-bar systems.

Re: [Intel-gfx] Regression on 5.19.12, display flickering on Framework laptop

2022-10-04 Thread Greg Kroah-Hartman
On Tue, Oct 04, 2022 at 06:46:10AM -0500, David Matthew Mattli wrote: > Thorsten Leemhuis writes: > > > On 03.10.22 19:48, Ville Syrjälä wrote: > >> On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote: > >>> On Sat, Oct 01, 2022 at 12:07:39PM +0200, Thorsten Leemhuis wrote: > On 30.

Re: [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset

2022-10-04 Thread Balasubramani Vivekanandan
On 04.10.2022 16:03, Jani Nikula wrote: > On Tue, 04 Oct 2022, Balasubramani Vivekanandan > wrote: > > Prior to display version 12, platforms had DDI ports A,B,C,D,E,F > > > > represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of > > > > the ports

Re: [Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

2022-10-04 Thread Ville Syrjälä
On Tue, Oct 04, 2022 at 02:19:15PM +0100, Matthew Auld wrote: > For these types of display buffers, we need to able to CPU access some > part of the backing memory in prepare_plane_clear_colors(). As a result > we need to ensure we always place in the mappable part of lmem, which > becomes necessar

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Don't use port enum as register offset (rev8)

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915/display: Don't use port enum as register offset (rev8) URL : https://patchwork.freedesktop.org/series/108833/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v5 2/5] drm/i915/display: handle migration for dpt

2022-10-04 Thread Ville Syrjälä
On Tue, Oct 04, 2022 at 02:19:13PM +0100, Matthew Auld wrote: > On platforms like DG2, it looks like the dpt path here is missing the > migrate-to-lmem step on discrete platforms. > > v2: > - Move the vma_pin() under the for_i915_gem_ww(), otherwise the > object can be moved after dropping t

[Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

2022-10-04 Thread Matthew Auld
For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place in the mappable part of lmem, which becomes necessary on small-bar systems. v2(Nirmoy & Ville): - Add some commentary fo

[Intel-gfx] [PATCH v5 2/5] drm/i915/display: handle migration for dpt

2022-10-04 Thread Matthew Auld
On platforms like DG2, it looks like the dpt path here is missing the migrate-to-lmem step on discrete platforms. v2: - Move the vma_pin() under the for_i915_gem_ww(), otherwise the object can be moved after dropping the lock and then doing the pin. Fixes: 33e7a975103c ("drm/i915/xelpd: Fir

[Intel-gfx] [PATCH v5 3/5] drm/i915: allow control over the flags when migrating

2022-10-04 Thread Matthew Auld
In the next patch we want to move the object (if the current resource is not compatible), to the mappable part of lmem for some display buffers. Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY hint. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy

[Intel-gfx] [PATCH v5 5/5] drm/i915: check memory is mappable in read_from_page

2022-10-04 Thread Matthew Auld
On small-bar systems we could be given something non-mappable here, which leads to nasty oops. Make this nicer by checking if the resource is mappable or not, and return an error otherwise. v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY) Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville

[Intel-gfx] [PATCH v5 1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Matthew Auld
The copy is async (if there even is one), but when later updating the GGTT we always sync against the binding, which will in turn sync against any moves. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- drivers/gpu/drm/i915/display/inte

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Match frequencies reported by PMU and sysfs

2022-10-04 Thread Tvrtko Ursulin
On 04/10/2022 14:00, Tvrtko Ursulin wrote: On 04/10/2022 10:29, Tvrtko Ursulin wrote: On 03/10/2022 20:24, Ashutosh Dixit wrote: PMU and sysfs use different wakeref's to "interpret" zero freq. Sysfs uses runtime PM wakeref (see intel_rps_read_punit_req and intel_rps_read_actual_frequency).

Re: [Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset

2022-10-04 Thread Jani Nikula
On Tue, 04 Oct 2022, Balasubramani Vivekanandan wrote: > Prior to display version 12, platforms had DDI ports A,B,C,D,E,F > > represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of > > the ports were in the same order as the ports. So the port enums

Re: [Intel-gfx] [PATCH v2 12/14] drm/i915: Define multicast registers as a new type

2022-10-04 Thread Jani Nikula
On Tue, 04 Oct 2022, Jani Nikula wrote: > On Fri, 30 Sep 2022, Matt Roper wrote: >> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h >> b/drivers/gpu/drm/i915/i915_reg_defs.h >> index 8f486f77609f..e823869b9afd 100644 >> --- a/drivers/gpu/drm/i915/i915_reg_defs.h >> +++ b/drivers/gpu/drm/i915/i

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Match frequencies reported by PMU and sysfs

2022-10-04 Thread Tvrtko Ursulin
On 04/10/2022 10:29, Tvrtko Ursulin wrote: On 03/10/2022 20:24, Ashutosh Dixit wrote: PMU and sysfs use different wakeref's to "interpret" zero freq. Sysfs uses runtime PM wakeref (see intel_rps_read_punit_req and intel_rps_read_actual_frequency). PMU uses the GT parked/unparked wakeref. In

Re: [Intel-gfx] Regression on 5.19.12, display flickering on Framework laptop

2022-10-04 Thread Greg Kroah-Hartman
On Tue, Oct 04, 2022 at 03:35:44PM +0300, Ville Syrjälä wrote: > On Mon, Oct 03, 2022 at 08:28:50PM +0200, Thorsten Leemhuis wrote: > > > > > > On 03.10.22 19:48, Ville Syrjälä wrote: > > > On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote: > > >> On Sat, Oct 01, 2022 at 12:07:39PM +0

Re: [Intel-gfx] [PATCH v2 12/14] drm/i915: Define multicast registers as a new type

2022-10-04 Thread Jani Nikula
On Fri, 30 Sep 2022, Matt Roper wrote: > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h > b/drivers/gpu/drm/i915/i915_reg_defs.h > index 8f486f77609f..e823869b9afd 100644 > --- a/drivers/gpu/drm/i915/i915_reg_defs.h > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h > @@ -104,22 +104,16 @@ typedef s

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 URL : https://patchwork.freedesktop.org/series/109384/ State : success == Summary == CI Bug Log - changes from CI_DRM_12210 -> Patchwork_109384v1 ===

[Intel-gfx] [PATCH v6 7/7] drm/i915/display: cleanup unused DDI port enums

2022-10-04 Thread Balasubramani Vivekanandan
DDI port enums PORT_G/H/I were added in the commit - "6c8337dafaa9 drm/i915/tgl: Add additional ports for Tiger Lake" to identify new ports added in the platform. In the subsequent commits those ports were identified by new enums PORT_TC1/TC2/TC3.. to differentiate TypeC ports from non-TypeC. Howev

[Intel-gfx] [PATCH v6 6/7] drm/i915/display: Fix port_identifier function

2022-10-04 Thread Balasubramani Vivekanandan
port_identifier function was broken when TypeC ports were using enum aliases. It would return wrong string for TypeC ports. With unique enums for DDI ports now, fix port_identifier to cover all ports. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display.h | 12

[Intel-gfx] [PATCH v6 5/7] drm/i915/display: Remove PORT_D_XELPD/PORT_E_XELPD platform specific defintions

2022-10-04 Thread Balasubramani Vivekanandan
Port enums are no more used in the DDI register offset caculcation. We can remove the platform specific port redefinitions. Along with it we also get rid of the code required for handling these special definitions. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_

[Intel-gfx] [PATCH v6 4/7] drm/i915/display: Free port enums from tied to register offset

2022-10-04 Thread Balasubramani Vivekanandan
With the index required for DDI register offset calculation available in the device info, the macros which used port enums to calculate the DDI register offsets i.e. DDI_BUF_CTL and DDI_CLK_SEL are updated to make use of the index rather than enum directly. Any new macros access that DDI registers

[Intel-gfx] [PATCH v6 3/7] drm/i915/display: Define the DDI port indices inside device info

2022-10-04 Thread Balasubramani Vivekanandan
Prior to display version 12, platforms had DDI ports A,B,C,D,E,F represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of the ports was in the same order as the ports. So the port enums were directly used as index to calculate the register offset of the ports. Starting in display ve

[Intel-gfx] [PATCH v6 2/7] drm/i915/display: Pass struct drm_i915_private to DDI_CLK_SEL macro

2022-10-04 Thread Balasubramani Vivekanandan
DDI_CLK_SEL is an another macro which returns the register offset based on DDI port enum. So DDI_CLK_SEL has to be prepared for the new method being developed for calculating the register offsets of DDI ports. Macro receives i915 private structure as new parameter for the upcoming changes. Signed-

[Intel-gfx] [PATCH v6 1/7] drm/i915/display: Pass struct drm_i915_private to DDI_BUF_CTL macro

2022-10-04 Thread Balasubramani Vivekanandan
This is a prep patch for a patch series in which register offset of the DDI ports are not calculated using the port enums but using a different datastructure part of the device info. So the device info is passed as a parameter to the macro DDI_BUF_CTL but unused yet. Signed-off-by: Balasubramani V

[Intel-gfx] [PATCH v6 0/7] drm/i915/display: Don't use port enum as register offset

2022-10-04 Thread Balasubramani Vivekanandan
Prior to display version 12, platforms had DDI ports A,B,C,D,E,F represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of the ports were in the same order as the ports. So the port enums were directly used as index to calculate the r

Re: [Intel-gfx] Regression on 5.19.12, display flickering on Framework laptop

2022-10-04 Thread Ville Syrjälä
On Mon, Oct 03, 2022 at 08:28:50PM +0200, Thorsten Leemhuis wrote: > > > On 03.10.22 19:48, Ville Syrjälä wrote: > > On Mon, Oct 03, 2022 at 08:45:18PM +0300, Ville Syrjälä wrote: > >> On Sat, Oct 01, 2022 at 12:07:39PM +0200, Thorsten Leemhuis wrote: > >>> On 30.09.22 14:26, Jerry Ling wrote: >

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/2] drm/i915: enable PS64 support for DG2

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v3,1/2] drm/i915: enable PS64 support for DG2 URL : https://patchwork.freedesktop.org/series/109384/ State : warning == Summary == Error: dim checkpatch failed 88944e5bbc43 drm/i915: enable PS64 support for DG2 -:15: ERROR:GIT_COMMIT_ID: Pleas

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj URL : https://patchwork.freedesktop.org/series/109382/ State : success == Summary == CI Bug Log - changes from CI_DRM_12210 -> Patchwork_109382v1 ==

Re: [Intel-gfx] [PATCH v4 2/5] drm/i915/display: handle migration for dpt

2022-10-04 Thread Ville Syrjälä
On Tue, Oct 04, 2022 at 12:54:33PM +0100, Matthew Auld wrote: > On 04/10/2022 12:22, Ville Syrjälä wrote: > > On Tue, Oct 04, 2022 at 11:33:08AM +0100, Matthew Auld wrote: > >> On platforms like DG2, it looks like the dpt path here is missing the > >> migrate-to-lmem step on discrete platforms. > >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Fix overwriting ggtt

2022-10-04 Thread Patchwork
== Series Details == Series: drm/i915/selftests: Fix overwriting ggtt URL : https://patchwork.freedesktop.org/series/109379/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12208_full -> Patchwork_109379v1_full Summary --

Re: [Intel-gfx] [PATCH v4 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

2022-10-04 Thread Ville Syrjälä
On Tue, Oct 04, 2022 at 12:51:11PM +0100, Matthew Auld wrote: > On 04/10/2022 12:28, Ville Syrjälä wrote: > > On Tue, Oct 04, 2022 at 11:33:10AM +0100, Matthew Auld wrote: > >> For these types of display buffers, we need to able to CPU access some > >> part of the backing memory in prepare_plane_cl

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj URL : https://patchwork.freedesktop.org/series/109382/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separa

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Patchwork
== Series Details == Series: series starting with [v5,1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj URL : https://patchwork.freedesktop.org/series/109382/ State : warning == Summary == Error: dim checkpatch failed 0fc08f3e0045 drm/i915: remove the TODO in pin_and_fence_fb_obj 397efa1

Re: [Intel-gfx] [PATCH v4 2/5] drm/i915/display: handle migration for dpt

2022-10-04 Thread Matthew Auld
On 04/10/2022 12:22, Ville Syrjälä wrote: On Tue, Oct 04, 2022 at 11:33:08AM +0100, Matthew Auld wrote: On platforms like DG2, it looks like the dpt path here is missing the migrate-to-lmem step on discrete platforms. Fixes: 33e7a975103c ("drm/i915/xelpd: First stab at DPT support") Signed-off-

Re: [Intel-gfx] [PATCH v4 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

2022-10-04 Thread Matthew Auld
On 04/10/2022 12:28, Ville Syrjälä wrote: On Tue, Oct 04, 2022 at 11:33:10AM +0100, Matthew Auld wrote: For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place in the mappable

[Intel-gfx] [PATCH v3 2/2] drm/i915/uapi: expose GTT alignment

2022-10-04 Thread Matthew Auld
On some platforms we potentially have different alignment restrictions depending on the memory type. We also now have different alignment restrictions for the same region across different kernel versions. Extend the region query to return the minimum required GTT alignment. Testcase: igt@gem_creat

[Intel-gfx] [PATCH v3 1/2] drm/i915: enable PS64 support for DG2

2022-10-04 Thread Matthew Auld
It turns out that on production DG2/ATS HW we should have support for PS64. This feature allows to provide a 64K TLB hint at the PTE level, which is a lot more flexible than the current method of enabling 64K GTT pages for the entire page-table, since that leads to all kinds of annoying restriction

Re: [Intel-gfx] [PATCH v4 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

2022-10-04 Thread Ville Syrjälä
On Tue, Oct 04, 2022 at 11:33:10AM +0100, Matthew Auld wrote: > For these types of display buffers, we need to able to CPU access some > part of the backing memory in prepare_plane_clear_colors(). As a result > we need to ensure we always place in the mappable part of lmem, which > becomes necessar

Re: [Intel-gfx] [PATCH v4 2/5] drm/i915/display: handle migration for dpt

2022-10-04 Thread Ville Syrjälä
On Tue, Oct 04, 2022 at 11:33:08AM +0100, Matthew Auld wrote: > On platforms like DG2, it looks like the dpt path here is missing the > migrate-to-lmem step on discrete platforms. > > Fixes: 33e7a975103c ("drm/i915/xelpd: First stab at DPT support") > Signed-off-by: Matthew Auld > Cc: Jianshui Yu

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Fix revocation of non-persistent contexts

2022-10-04 Thread Tvrtko Ursulin
On 03/10/2022 13:16, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Patch which added graceful exit for non-persistent contexts missed the fact it is not enough to set the exiting flag on a context and let the backend handle it from there. GuC backend cannot handle it because it runs independent

Re: [Intel-gfx] [PATCH i-g-t] gem_ctx_persistence: adjust reset timeout

2022-10-04 Thread Kamil Konieczny
On 2022-09-23 at 18:01:37 +0200, Andrzej Hajda wrote: > Tests on DG2 show that context cancel can take even 350ms, > due to error state capturing in guc_handle_context_reset. > Since it happens only in debug mode and tests runs in debug mode > it should be fine to adjust the timeout. > Let's double

Re: [Intel-gfx] [PATCH 2/2] drm/i915: remove circ_buf.h includes

2022-10-04 Thread Jani Nikula
On Tue, 04 Oct 2022, "Jiri Slaby (SUSE)" wrote: > The last user of macros from that include was removed in 2018 by the > commit below. > > Fixes: 6cc42152b02b ("drm/i915: Remove support for legacy debugfs crc > interface") > Cc: Jani Nikula > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: Tvrtko

Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: fix randconfig build

2022-10-04 Thread Jani Nikula
On Tue, 04 Oct 2022, "Jiri Slaby (SUSE)" wrote: > When DRM_I915=y and BACKLIGHT_CLASS_DEVICE=m, the build fails: > ld: drivers/gpu/drm/i915/display/intel_backlight.o: in function > `intel_backlight_device_register': > intel_backlight.c:(.text+0x5587): undefined reference to > `backlight_device_g

Re: [Intel-gfx] [PATCH i-g-t 3/4] tests/i915/query: sanity check reported GTT alignment

2022-10-04 Thread Das, Nirmoy
Hi Matt, On 10/3/2022 7:24 PM, Matthew Auld wrote: Ensure the kernel is reporting "normal" values here, based on our current expectations. Signed-off-by: Matthew Auld Cc: Andrzej Hajda Cc: Nirmoy Das --- tests/i915/i915_query.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deleti

[Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

2022-10-04 Thread Matthew Auld
For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place in the mappable part of lmem, which becomes necessary on small-bar systems. v2(Nirmoy & Ville): - Add some commentary fo

[Intel-gfx] [PATCH v5 5/5] drm/i915: check memory is mappable in read_from_page

2022-10-04 Thread Matthew Auld
On small-bar systems we could be given something non-mappable here, which leads to nasty oops. Make this nicer by checking if the resource is mappable or not, and return an error otherwise. v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY) Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville

[Intel-gfx] [PATCH v5 2/5] drm/i915/display: handle migration for dpt

2022-10-04 Thread Matthew Auld
On platforms like DG2, it looks like the dpt path here is missing the migrate-to-lmem step on discrete platforms. v2: - Move the vma_pin() under the for_i915_gem_ww(), otherwise the object can be moved after dropping the lock and then doing the pin. Fixes: 33e7a975103c ("drm/i915/xelpd: Fir

[Intel-gfx] [PATCH v5 3/5] drm/i915: allow control over the flags when migrating

2022-10-04 Thread Matthew Auld
In the next patch we want to move the object (if the current resource is not compatible), to the mappable part of lmem for some display buffers. Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY hint. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy

[Intel-gfx] [PATCH v5 1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Matthew Auld
The copy is async (if there even is one), but when later updating the GGTT we always sync against the binding, which will in turn sync against any moves. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- drivers/gpu/drm/i915/display/inte

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Use drm_device alias if defined

2022-10-04 Thread Jani Nikula
On Tue, 04 Oct 2022, Andi Shyti wrote: > Hi Jani, > > On Tue, Oct 04, 2022 at 11:46:38AM +0300, Jani Nikula wrote: >> On Tue, 04 Oct 2022, Andrzej Hajda wrote: >> > On 04.10.2022 09:22, Jani Nikula wrote: >> >> On Tue, 04 Oct 2022, Andrzej Hajda wrote: >> >>> Alias is shorter and more readable.

[Intel-gfx] [PATCH v4 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers

2022-10-04 Thread Matthew Auld
For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place in the mappable part of lmem, which becomes necessary on small-bar systems. v2(Nirmoy & Ville): - Add some commentary fo

[Intel-gfx] [PATCH v4 5/5] drm/i915: check memory is mappable in read_from_page

2022-10-04 Thread Matthew Auld
On small-bar systems we could be given something non-mappable here, which leads to nasty oops. Make this nicer by checking if the resource is mappable or not, and return an error otherwise. v2: drop GEM_BUG_ON(flags & I915_BO_ALLOC_GPU_ONLY) Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville

[Intel-gfx] [PATCH v4 3/5] drm/i915: allow control over the flags when migrating

2022-10-04 Thread Matthew Auld
In the next patch we want to move the object (if the current resource is not compatible), to the mappable part of lmem for some display buffers. Currently that requires being able to unset the I915_BO_ALLOC_GPU_ONLY hint. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy

[Intel-gfx] [PATCH v4 2/5] drm/i915/display: handle migration for dpt

2022-10-04 Thread Matthew Auld
On platforms like DG2, it looks like the dpt path here is missing the migrate-to-lmem step on discrete platforms. Fixes: 33e7a975103c ("drm/i915/xelpd: First stab at DPT support") Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das --- drivers/gpu/drm/i915/display/int

[Intel-gfx] [PATCH v4 1/5] drm/i915: remove the TODO in pin_and_fence_fb_obj

2022-10-04 Thread Matthew Auld
The copy is async (if there even is one), but when later updating the GGTT we always sync against the binding, which will in turn sync against any moves. Signed-off-by: Matthew Auld Cc: Jianshui Yu Cc: Ville Syrjälä Cc: Nirmoy Das Reviewed-by: Nirmoy Das --- drivers/gpu/drm/i915/display/inte

Re: [Intel-gfx] [PATCH v2 14/14] drm/i915/mtl: Add multicast steering for media GT

2022-10-04 Thread Tvrtko Ursulin
On 03/10/2022 20:32, Matt Roper wrote: On Mon, Oct 03, 2022 at 09:56:18AM +0100, Tvrtko Ursulin wrote: Hi Matt, On 01/10/2022 01:45, Matt Roper wrote: MTL's media GT only has a single type of steering ("OAADDRM") which selects between media slice 0 and media slice 1. We'll always steer to

  1   2   >