From: Kees Cook
Implement a robust overflows_type() macro to test if a variable or
constant value would overflow another variable or type. This can be
used as a constant expression for static_assert() (which requires a
constant expression[1][2]) when used on constant values. This must be
construc
On Fri, 07 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Apparently some panels declare multiple modes with random
> sync polarities. Seems a bit weird, but looks like Windows/GOP
> doesn't care, so let follow suit and accept alternate fixed
> modes regardless of their sync polarities.
From: "Suraj Kandpal"
Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.
---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vd
From: Ankit Nautiyal
Go with DSC only if the given output_format is supported.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i91
From: "Suraj Kandpal"
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/i915_reg.h | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
i
Implementation of VDSC for YCbCr420.
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 187 --
.../gpu/drm/i915/display/intel_qp_tables.h| 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
3 files changed, 180 insertions(+), 15 del
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding cor
From: "Suraj Kandpal"
Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.
---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vd
Implementation of VDSC for YCbCr420.
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 187 --
.../gpu/drm/i915/display/intel_qp_tables.h| 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
3 files changed, 180 insertions(+), 15 del
From: "Suraj Kandpal"
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/i915_reg.h | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
i
From: Ankit Nautiyal
Go with DSC only if the given output_format is supported.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i91
From: "Kandpal, Suraj"
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-adding fields missed for vdsc_
== Series Details ==
Series: drm/i915: prepare for uC loading on MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108925/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12239_full -> Patchwork_108925v2_full
Summary
== Series Details ==
Series: drm/i915/hdmi: Prune Interlaced modes for Display >= 12
URL : https://patchwork.freedesktop.org/series/109646/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12239 -> Patchwork_109646v1
Summary
-
On Thu, Oct 13, 2022 at 10:41:24AM +0530, Ankit Nautiyal wrote:
> Defeature Display Interlace support.
> Support for Interlace modes is removed from Gen 12 onwards.
> For DP we do not support interlace modes (except for very old
> platforms). Pruning the interlaced modes for HDMI for Display >=12.
Defeature Display Interlace support.
Support for Interlace modes is removed from Gen 12 onwards.
For DP we do not support interlace modes (except for very old
platforms). Pruning the interlaced modes for HDMI for Display >=12.
Bspec: 50490
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/d
== Series Details ==
Series: drm/i915/slpc: Use platform limits for min/max frequency
URL : https://patchwork.freedesktop.org/series/109632/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12238_full -> Patchwork_109632v1_full
== Series Details ==
Series: drm/i915: prepare for uC loading on MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12239 -> Patchwork_108925v2
Summary
---
== Series Details ==
Series: drm/i915: prepare for uC loading on MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108925/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
Error: Cannot open file ./drivers/gpu/drm/i915/intel_wopcm.c
WARNING: kernel-doc './scripts/ke
== Series Details ==
Series: drm/i915: prepare for uC loading on MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108925/
State : warning
== Summary ==
Error: dim checkpatch failed
927847787d62 drm/i915/huc: only load HuC on GTs that have VCS engines
b2f08a65b6df drm/i915/uc: fetch uc
The FW binaries are independently loaded on each GT. On MTL, the memory
is shared so we could potentially re-use a single allocation, but on
discrete multi-gt platforms we are going to need independent copies,
so it is easier to do the same on MTL as well, given that the amount
of duplicated memory
The media GT shares the G-unit with the root GT, so a second set of
communication registers is required for the media GuC.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++
dri
The render and media GuCs share the same interrupt enable register, so
we can no longer disable interrupts when we disable communication for
one of the GuCs as this would impact the other GuC. Instead, we keep the
interrupts always enabled in HW and use a variable in the GuC structure
to determine
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This worked because we didn't have a case where 2 FWs would be loaded on
the same GGTT at the same time. On MTL, however, this can happend if both
GTs are reset at t
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed with
separate partitioning in WOPCM for GCD/GT GuC and SA Media GuC. The size
of WOPCM is 4MB with lower 2MB for SA Media and upper 2MB for GCD/GT.
+=+===> ++ <== WOPCM TOP
From: Stuart Summers
MTL supports GuC deprivilege. Add the feature flag to this platform.
Signed-off-by: Stuart Summers
Cc: Radhakrishna Sripada
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
On MTL the primary GT doesn't have any media capabilities, so no video
engines and no HuC. We must therefore skip the HuC fetch and load on
that specific case. Given that other multi-GT platforms might have HuC
on the primary GT, we can't just check for that and it is easier to
instead check for th
The introduction of the media GT brings a few changes for GuC/HuC. The
main difference between the 2 GTs is that only the media one has the
HuC, while both have the GuC. Also, the fact that both GTs use the same
G-unit and GGTT means we now have parallel interrupt/communication
paths. Lastly, WOPCM
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads (rev9)
URL : https://patchwork.freedesktop.org/series/100428/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12238_full -> Patchwork_100428v9_full
===
On Wed, 12 Oct 2022 15:27:27 -0700, Umesh Nerlige Ramappa wrote:
>
> +static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
> +{
> + u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
> + u32 *state = ce->lrc_reg_state;
> +
> + for (offset = 0; offset < len; )
== Series Details ==
Series: Add DG2 OA support (rev6)
URL : https://patchwork.freedesktop.org/series/107584/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12238 -> Patchwork_107584v6
Summary
---
**FAILURE**
Serio
== Series Details ==
Series: Add DG2 OA support (rev6)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add DG2 OA support (rev6)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim checkpatch failed
417244c8ec48 drm/i915/perf: Fix OA filtering logic for GuC mode
09d47558b4c6 drm/i915/perf: Add 32-bit OAG and OAR formats fo
== Series Details ==
Series: drm/i915: add wait and lock to i915_vma_move_to_active
URL : https://patchwork.freedesktop.org/series/109620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12238_full -> Patchwork_109620v1_full
XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable bytes per clock setting on enabling OA.
Bspec: 51762
Bspec: 52201
v2:
- Fix commit msg (Ashutosh)
- Fix checkpatch issues
v3:
- s/commands/bytes/ in code comment and commmit msg
Signed-off-by: Ume
Earlier code used exclusive_stream to check for user passed context.
Simplify this by accessing stream->ctx.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/g
Add new OA formats for DG2.
MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893
v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
separate series with UMD changes
v3:
- Update commit mes
If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore t
DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.
v2: Drop format_size variable (Ashutosh)
Signed-off-by: Umesh Nerlige
OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.
In DG2
From: Lionel Landwerlin
We have an additional register to select which slices contribute to
OAG/OAG counter increments.
Signed-off-by: Lionel Landwerlin
Signed-off-by: Matt Roper
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c
Disable Clock gating in EU when gathering the events so that EU events
are not lost.
v2: Fix checkpatch issues
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/i915_perf.c| 23 +
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
v2: (Lionel)
- Move MI definitions to intel_gpu_commands.h
- Ensure __find_reg_in_lri does read past context image size
v3: (Ashutosh)
- Drop unnecessary use of double undersc
With GuC mode of submission, GuC is in control of defining the context
id field that is part of the OA reports. To filter reports, UMD and KMD
must know what sw context id was chosen by GuC. There is not interface
between KMD and GuC to determine this, so read the upper-dword of
EXECLIST_STATUS to
With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 31 --
drivers/gpu/drm/i
OA was disabled for DG2 as support was missing. Enable it back now.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
Reviewed-by: Ashutosh Dixit
---
drivers/gp
User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 21 +++--
1 file changed, 19 i
From: Vinay Belgaumkar
On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA
since OA does not expect engine resets during its use. Fix it by
disabling RC6.
v2: (Ashutosh)
- Bring back slpc_unset_param helper
- Update commit msg
- Use with_intel_runtime_pm helper for set/unset
v3
Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT b
Add OA format support for DG2 and various fixes for DG2.
This series has 2 uapi changes listed below:
1) drm/i915/perf: Add OAG and OAR formats for DG2
DG2 has new OA formats defined that can be selected by the
user. The UMD changes that are consumed by GPUvis are:
https://patchwork.freedesktop.
The following changes since commit fdf1a65258522edf18a0a1768fbafa61ed07e598:
linux-firmware: Update AMD cpu microcode (2022-09-30 17:33:35 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dg2_huc_7.10.3
for you to fetch changes up to 1655a5116858
On 12.10.2022 16:38, Matthew Auld wrote:
On 12/10/2022 13:43, Andrzej Hajda wrote:
Since almost all calls to i915_vma_move_to_active are prepended with
i915_request_await_object and many of them are surrounded with
i915_vma_lock, let's put both into i915_vma_move_to_active and add
i915_vma_mo
On Wed, Oct 12, 2022 at 11:51:48AM +0300, Jani Nikula wrote:
On Tue, 11 Oct 2022, Lucas De Marchi wrote:
Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
ranges. This should cover most of our needs for _MMIO_PLL3 and such.
To show what is achieved with the new macro, convert so
== Series Details ==
Series: drm/i915/slpc: Use platform limits for min/max frequency
URL : https://patchwork.freedesktop.org/series/109632/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12238 -> Patchwork_109632v1
Summary
GuC will set the min/max frequencies to theoretical max on
ATS-M. This will break kernel ABI, so limit min/max frequency
to RP0(platform max) instead.
Also modify the SLPC selftest to update the min frequency
when we have a server part so that we can iterate between
platform min and max.
Signed-o
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev4)
URL : https://patchwork.freedesktop.org/series/107550/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12237_full -> Patchwork_107550v4_full
==
On 30.09.2022 17:45, Matt Roper wrote:
> Rather than relying on the implicit behavior of intel_uncore_*()
> functions, let's always use the intel_gt_mcr_*() functions to operate on
> multicast/replicated registers.
>
> v2:
> - Add TLB invalidation registers
>
> Signed-off-by: Matt Roper
> ---
>
On Tue, 11 Oct 2022, Umesh Nerlige Ramappa
wrote:
> On Tue, Oct 11, 2022 at 08:47:00PM +0300, Jani Nikula wrote:
>>On Mon, 10 Oct 2022, Umesh Nerlige Ramappa
>>wrote:
>>> Some SKUs of same gen12 platform may have different oactxctrl
>>> offsets. For gen12, determine oactxctrl offsets at runtime
On Wed, 12 Oct 2022, Ville Syrjälä wrote:
> On Wed, Oct 12, 2022 at 05:28:27PM +0300, Jani Nikula wrote:
>> On Tue, 11 Oct 2022, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Currently we only write as many dwords into the hardware
>> > ELD buffers as drm_eld_size() tells us. That coul
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads (rev9)
URL : https://patchwork.freedesktop.org/series/100428/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12238 -> Patchwork_100428v9
Summary
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads (rev9)
URL : https://patchwork.freedesktop.org/series/100428/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Improve anti-pre-emption w/a for compute workloads (rev9)
URL : https://patchwork.freedesktop.org/series/100428/
State : warning
== Summary ==
Error: dim checkpatch failed
9800096289da drm/i915/guc: Limit scheduling properties to avoid overflow
-:45: CHECK:MACRO_AR
On Wed, 12 Oct 2022 02:48:30 -0700, Matthew Auld wrote:
>
> So with this change all the runtime pm stuff is disabled on dgfx? i.e
> intel_runtime_pm_get() always returns zero or so?
I guess it should always return non-zero (or the wakeref) since the device
is always on...
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Include the ELD has a hex blob in the crtc state dump.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> .../drm/i915/display/intel_crtc_st
== Series Details ==
Series: drm/i915: add wait and lock to i915_vma_move_to_active
URL : https://patchwork.freedesktop.org/series/109620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12238 -> Patchwork_109620v1
Summary
--
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Have the state checker validate the ELD. For now we'll
> just dump it out as a hex buffer on a mismatch, maybe
> someone will get inspired to decode it properly at some
> point...
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
On Wed, Oct 12, 2022 at 11:32:18AM +0100, Matthew Auld wrote:
On 10/10/2022 07:58, Niranjana Vishwanathapura wrote:
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not hav
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Read out the ELD from the hw so the state checker can verify it.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/dis
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Read out the ELD from the hardware buffer so that we can
> hook up the state checker to validate it.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use the precomputed crtc_state->eld for audio setup on SDVO
> just like we do with native HDMI.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
>
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the SDVO audio state computaiton into a helper.
*computation
Reviewed-by: Jani Nikula
>
> This is almost identical to intel_hdmi_has_audio(),
> except the sink capabilities are stored under intel_sdvo
> rather than intel
On 12/10/2022 15:57, Rodrigo Vivi wrote:
On Wed, Oct 12, 2022 at 10:48:30AM +0100, Matthew Auld wrote:
On 12/10/2022 09:34, Anshuman Gupta wrote:
DGFX platforms has lmem and cpu can access the lmem objects
via mmap and i915 internal i915_gem_object_pin_map() for
i915 own usages. Both of these m
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stash the ELD into the crtc_state and precompute it. This gets
> rid of the ugly ELD mutation during intel_audio_codec_enable(),
> and opens the door for the state checker.
Should note the functional change of disabling audio up
On Wed, Oct 12, 2022 at 05:33:31PM +0300, Jani Nikula wrote:
> On Tue, 11 Oct 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The audio code does a lot of RMW accesses. Utilize
> > intel_de_rmw() to make that a bit less tedious.
> >
> > There are still some hand rolled RMW left, but th
On Wed, Oct 12, 2022 at 05:28:27PM +0300, Jani Nikula wrote:
> On Tue, 11 Oct 2022, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Currently we only write as many dwords into the hardware
> > ELD buffers as drm_eld_size() tells us. That could mean the
> > remainder of the hardware buffer is
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The spec tells us to do a bunch of vblank waits in the audio
> enable/disable sequences. Make it so.
>
> The FIXMEs are nonsense since we do the audio disable very
> early and enable very late, so vblank interrupts are in fact
>
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On the older platforms the audio presence detect bit is in
> the port register, so it gets written outside audio codec hooks
> and is this separate from the ELD valid toggling. Split the
> operations into two steps on hsw+ to be
On Wed, Oct 12, 2022 at 01:26:45PM +0300, Joonas Lahtinen wrote:
> I think I commented on this already, but the patch subject should really be as
> informative as possible like: "Disable PCI runtime PM on dGPUs" as that is
> exactly
> what the patch does.
+1 here.
>
> Also bit unsure if the Fix
On Wed, Oct 12, 2022 at 10:48:30AM +0100, Matthew Auld wrote:
> On 12/10/2022 09:34, Anshuman Gupta wrote:
> > DGFX platforms has lmem and cpu can access the lmem objects
> > via mmap and i915 internal i915_gem_object_pin_map() for
> > i915 own usages. Both of these methods has pre-requisite
> > re
On Wed, Oct 12, 2022 at 11:21:59AM +0200, Andi Shyti wrote:
> Hi Anshuman,
>
> On Wed, Oct 12, 2022 at 02:04:02PM +0530, Anshuman Gupta wrote:
> > DGFX platforms has lmem and cpu can access the lmem objects
> > via mmap and i915 internal i915_gem_object_pin_map() for
> > i915 own usages. Both of t
On Wed, 12 Oct 2022, Jani Nikula wrote:
> On Tue, 11 Oct 2022, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> We currently read the ELD buffer size from hardware on g4x,
>> but on ilk+ we just hardcode it to 84 bytes. Let's unify
>> this and just do the hardware readout on all platforms,
>> i
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make the eld pointer u32* so we don't have to do super
> ugly casting in the code itself.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
>
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We currently read the ELD buffer size from hardware on g4x,
> but on ilk+ we just hardcode it to 84 bytes. Let's unify
> this and just do the hardware readout on all platforms,
> in case the size changes in the future or somethin
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No idea why we do this ELD comparions on g4x before loading
> the new ELD. Seems entirely pointless so just get rid of it.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
A
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On the "ilk" platforms AUD_CNTL_ST2 is a singleton. Protect
> it with the audio mutex in case we ever want to do parallel
> RMW access to it.
>
> Currently that should not happen since we only do audio
> enable/disable from full
On 12/10/2022 13:43, Andrzej Hajda wrote:
Since almost all calls to i915_vma_move_to_active are prepended with
i915_request_await_object and many of them are surrounded with
i915_vma_lock, let's put both into i915_vma_move_to_active and add
i915_vma_move_to_active_unlocked helper to handle non-lo
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename a few g4x bits to match the ibx+ bits.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_audio.c
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Switch the audio registers to REG_BIT() & co. Also rename
> G4X_ELDV and G4X_ELD_ADDR_MASK a bit to match the IBX
> definitions.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjäl
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The "ilk" audio codec codepaths have some duplicated code
> to figure out the correct registers to use on each platform.
> Extrat that into a single place.
*extract
Reviewed-by: Jani Nikula
>
> Cc: Chaitanya Kumar Borah
> Cc
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We don't use the audio code on crestline (CL) since it doesn't
> support native HDMI output, and SDVO has it's own way of doing
> audio.
>
> And Bearlake-C (BLC) doesn't even exist in the real world, so
> no point it trying to de
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Remove some leftovers I missed in commit
> 2dd43144e824 ("drm/i915: Streamline the artihmetic")
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
>
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename the 'dev_priv' variables to 'i915' in the audio code
> to match modern style conventions.
>
> Cc: Chaitanya Kumar Borah
> Cc: Kai Vehmanen
> Cc: Takashi Iwai
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
>
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The audio code does a lot of RMW accesses. Utilize
> intel_de_rmw() to make that a bit less tedious.
>
> There are still some hand rolled RMW left, but those have
> a lot of code in between the read and write to calculate
> the n
On Tue, 11 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we only write as many dwords into the hardware
> ELD buffers as drm_eld_size() tells us. That could mean the
> remainder of the hardware buffer is left with whatever
> stale garbage it had before, which doesn't seem ent
On Wed, Oct 12, 2022 at 01:49:36PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On HSW/BDW the hardware ELD buffer does not work if the controller
> is suspended. I'm not 100% which thing in there is needed to make it
> work (at least just forcing the controller into D0 with setpci is
>
On Wed, 12 Oct 2022, Maxime Ripard wrote:
> On Wed, Oct 12, 2022 at 03:32:32PM +0300, Jani Nikula wrote:
>> On Tue, 11 Oct 2022, Jani Nikula wrote:
>> > While it takes more vertical space, sorted build lists with one object
>> > per line are arguably easier to manage, especially when there are
>>
On 10/10/2022 20:44, John Harrison wrote:
On 10/6/2022 15:20, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Improve anti-pre-emption w/a for compute workloads (rev8)
*URL:* https://patchwork.freedesktop.org/series/100428/
*State:*failure
*Details:*
https:/
Hi,
On Wed, 12 Oct 2022, Kai Vehmanen wrote:
> On Wed, 12 Oct 2022, Ville Syrjala wrote:
>
> > On HSW/BDW the hardware ELD buffer does not work if the controller
> > is suspended. I'm not 100% which thing in there is needed to make it
> > work (at least just forcing the controller into D0 with s
On Wed, Oct 12, 2022 at 03:32:32PM +0300, Jani Nikula wrote:
> On Tue, 11 Oct 2022, Jani Nikula wrote:
> > While it takes more vertical space, sorted build lists with one object
> > per line are arguably easier to manage, especially when there are
> > conflicting changes.
> >
> > Split anything wi
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