On Tue, Oct 18, 2022 at 02:02:08PM +0300, Jani Nikula wrote:
>
> Hello stable team, please backport these two commits to stable kernels
> v5.19 and v6.0:
>
> 4e78d6023c15 ("drm/i915/bios: Validate fp_timing terminator presence")
Does not apply to 5.19.y, can you provide a working backport?
> d3
== Series Details ==
Series: Add hwmon support for dgfx selftests
URL : https://patchwork.freedesktop.org/series/109850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12258 -> Patchwork_109850v1
Summary
---
**SUCCESS
== Series Details ==
Series: Add hwmon support for dgfx selftests
URL : https://patchwork.freedesktop.org/series/109850/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./arch/x86/include/asm/bitops.h:117
== Series Details ==
Series: Add hwmon support for dgfx selftests
URL : https://patchwork.freedesktop.org/series/109850/
State : warning
== Summary ==
Error: dim checkpatch failed
9cbba6841433 drm/i915/selftests: Rename librapl library to libpower
Traceback (most recent call last):
File "scr
== Series Details ==
Series: drm/i915/guc: Add GuC-Error-Capture-Init coverage of new engine types
(rev2)
URL : https://patchwork.freedesktop.org/series/109737/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
CC [M] drivers/gpu/drm/i915
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev6)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12258 -> Patchwork_108156v6
Summary
---
**SU
From: Tilak Tangudu
hwmon provides an interface to read energy values for discrete graphics.
add hwmon support to the existing libpower library so that it can verify
power consumption values in different selftests.
Changed prototype of libpower_get_energy_uJ
Signed-off-by: Tilak Tangudu
Signed
Add an interface to obtain hwmon energy values. This is used
by selftest to verify power consumption
Signed-off-by: Riana Tauro
---
drivers/gpu/drm/i915/i915_hwmon.c | 23 ---
drivers/gpu/drm/i915/i915_hwmon.h | 1 +
2 files changed, 21 insertions(+), 3 deletions(-)
diff --
Rename functions in librapl library to libpower.
No functional changes.
Signed-off-by: Riana Tauro
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 12 ++--
drivers/gpu/drm/i915/gt/selftest_rps.c | 8
driver
Rename librapl library to libpower. Add hwmon support in libpower for
dgfx.
Riana Tauro (2):
drm/i915/selftests: Rename librapl library to libpower
drm/i915/hwmon: Add helper function to obtain energy values
Tilak Tangudu (1):
drm/i915/selftests: Add hwmon support in libpower for dgfx
dri
We missed this at initial upstream because at that time
none of the GuC enabled platforms had a compute engine.
Add this now.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc
After initial upstream merge of GuC error-capture feature, we eventually
decided to remove a lot of unnecessary warning messages when we couldn't
retrieve register lists for ADS-error-state-capture initialization. It was
a justified decision because the majority of that noise was being repeated
thr
If GuC is being used and we initialized GuC-error-capture,
we need to be warning if we don't provide an error-capture
register list in the firmware ADS, for valid GT engines.
A warning makes sense as this would impact debugability
without realizing why a reglist wasn't retrieved and reported
by GuC
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev6)
URL : https://patchwork.freedesktop.org/series/108156/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
> > > Also commit message you can aim to wrap at 75 chars as per
> > > submitting-patches.rst.
> > >
> > > > + return -ENODATA;
> > >
> > > Is this a new exit condition or the thing would exit on the !num_regs
> > > check below anyway? Just wondering if the series is only about lo
On Mon, 17 Oct 2022 01:27:35 -0700, Jani Nikula wrote:
Hi Jani,
Thanks for reviewing, great suggestions overall. I have taken care of most
of them in series version v6. Please see below.
> On Fri, 14 Oct 2022, Ashutosh Dixit wrote:
> > @@ -811,9 +809,23 @@ u64 intel_rc6_residency_ns(struct inte
From: Badal Nilawar
Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.
v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code refactor
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 resi
From: Don Hiatt
On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.
v2:
- Fixed review comments(Ashutosh)
- Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake, required
From: Badal Nilawar
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing fo
Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.
Therefore change RC6 residency functions to accept RC6 residency types
On Tue, Oct 18, 2022 at 01:20:06PM -0700, Niranjana Vishwanathapura wrote:
On Tue, Oct 18, 2022 at 07:01:57PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.
v2: Ensure req
Update: One additional change needed... after more testing i have come to
realize that
intel_guc_capture_getlistsize is also being triggered before
ADS-guc-error-capture
register-list population during initialization of the guc-error-capture module
itself
(intel_guc_capture_init). Its getting
On Tue, Oct 18, 2022 at 06:30:58PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not hav
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part
of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109820/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12254_full -> Patchwork_109820v1_full
==
On Tue, Oct 18, 2022 at 05:44:38PM -0700, John Harrison wrote:
> On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:
> > From: Aravind Iddamsetty
> >
...
> > diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
> > b/drivers/gpu/drm/i915/gt/intel_wopcm.c
> > similarity index 86%
> > rename from driver
On Tue, Oct 18, 2022 at 04:28:07PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not
== Series Details ==
Series: drm/i915/vm_bind: Add VM_BIND functionality (rev7)
URL : https://patchwork.freedesktop.org/series/105879/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12254_full -> Patchwork_105879v7_full
Summ
On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed with
separate partitioning in WOPCM for GCD/GT GuC and SA Media GuC. The size
What is GCD?
of WOPCM is 4MB with lower 2MB for SA Media and upper 2MB
== Series Details ==
Series: Add DG2 OA support (rev8)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add DG2 OA support (rev8)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim checkpatch failed
0bf14cf6597e drm/i915/perf: Fix OA filtering logic for GuC mode
dfe2d19762a0 drm/i915/perf: Add 32-bit OAG and OAR formats fo
== Series Details ==
Series: drm/i915/slpc: Optmize waitboost for SLPC
URL : https://patchwork.freedesktop.org/series/109840/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12258 -> Patchwork_109840v1
Summary
---
**SU
Hi Imre,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Imre-Deak/drm-i915-tgl-Add-locking-around-DKL-PHY-register-accesses/20221019-012209
base: git://anongit.freedesktop.org/drm/drm-t
XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable bytes per clock setting on enabling OA.
Bspec: 51762
Bspec: 52201
v2:
- Fix commit msg (Ashutosh)
- Fix checkpatch issues
v3:
- s/commands/bytes/ in code comment and commmit msg
Signed-off-by: Ume
DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.
v2: Drop format_size variable (Ashutosh)
Signed-off-by: Umesh Nerlige
With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 31 --
drivers/gpu/drm/i
Earlier code used exclusive_stream to check for user passed context.
Simplify this by accessing stream->ctx.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/g
Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT b
From: Vinay Belgaumkar
On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA
since OA does not expect engine resets during its use. Fix it by
disabling RC6.
v2: (Ashutosh)
- Bring back slpc_unset_param helper
- Update commit msg
- Use with_intel_runtime_pm helper for set/unset
v3
From: Lionel Landwerlin
We have an additional register to select which slices contribute to
OAG/OAG counter increments.
Signed-off-by: Lionel Landwerlin
Signed-off-by: Matt Roper
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c
Disable Clock gating in EU when gathering the events so that EU events
are not lost.
v2: Fix checkpatch issues
v3: User MCR helpers to write to MC reg
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/i915_
OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.
In DG2
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
v2: (Lionel)
- Move MI definitions to intel_gpu_commands.h
- Ensure __find_reg_in_lri does read past context image size
v3: (Ashutosh)
- Drop unnecessary use of double undersc
User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 21 +++--
1 file changed, 19 i
With GuC mode of submission, GuC is in control of defining the context
id field that is part of the OA reports. To filter reports, UMD and KMD
must know what sw context id was chosen by GuC. There is not interface
between KMD and GuC to determine this, so read the upper-dword of
EXECLIST_STATUS to
Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
Reviewed-by: Ashutosh Dixit
---
drivers/gp
If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore t
Add new OA formats for DG2.
MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893
v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
separate series with UMD changes
v3:
- Update commit mes
OA was disabled for DG2 as support was missing. Enable it back now.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
Add OA format support for DG2 and various fixes for DG2.
This series has 2 uapi changes listed below:
1) drm/i915/perf: Add OAG and OAR formats for DG2
DG2 has new OA formats defined that can be selected by the
user. The UMD changes that are consumed by GPUvis are:
https://patchwork.freedesktop.
Waitboost (when SLPC is enabled) results in a H2G message. This can result
in thousands of messages during a stress test and fill up an already full
CTB. There is no need to request for RP0 if GuC is already requesting the
same.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_r
On Sat, Oct 15, 2022 at 02:01:50AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pvc: Update forcewake domain for CCS register ranges
> URL : https://patchwork.freedesktop.org/series/109734/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12242_fu
On Fri, 2022-10-14 at 16:30 -0700, Matt Roper wrote:
> The bspec was just updated with a correction to the forcewake domain
> required when accessing registers in the CCS engine ranges (0x1a000 -
> 0x1 and 0x26000 - 0x27fff) on PVC; these ranges require a wake on
> the RENDER domain, not the GT
Hi Maxime,
W dniu 18.10.2022 o 12:00, Maxime Ripard pisze:
> On Mon, Oct 17, 2022 at 12:31:31PM +0200, Noralf Trønnes wrote:
>> Den 16.10.2022 20.52, skrev Mateusz Kwiatkowski:
static int vc4_vec_connector_get_modes(struct drm_connector *connector)
{
- struct drm_connector_state
Hi Maxime,
W dniu 18.10.2022 o 10:31, Maxime Ripard pisze:
> Hi,
>
> On Sun, Oct 16, 2022 at 09:46:49PM +0200, Mateusz Kwiatkowski wrote:
>> @@ -308,14 +324,15 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[]
>> = {
>> };
>>
>> static inline const struct vc4_vec_tv_mode *
>> -vc4_vec
On 10/17/2022 4:44 PM, John Harrison wrote:
On 10/12/2022 17:03, Daniele Ceraolo Spurio wrote:
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This worked because we didn't have a case where 2 FWs would be l
On Tue, Oct 18, 2022 at 07:01:57PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.
v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_
== Series Details ==
Series: drm/edid: Parse VRR cap fields from HFVSDB block
URL : https://patchwork.freedesktop.org/series/109801/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12254_full -> Patchwork_109801v1_full
Summar
== Series Details ==
Series: drm/i915/slpc: Use platform limits for min/max frequency (rev3)
URL : https://patchwork.freedesktop.org/series/109632/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12257 -> Patchwork_109632v3
S
== Series Details ==
Series: drm/i915/slpc: Use platform limits for min/max frequency (rev3)
URL : https://patchwork.freedesktop.org/series/109632/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Tue, Oct 18, 2022 at 11:01:48AM +0530, Ankit Nautiyal wrote:
> This patch parses HFVSDB fields for VRR capabilities of an
> HDMI2.1 sink and stores the VRR caps in a new structure in
> drm_hdmi_info.
>
> Signed-off-by: Ankit Nautiyal
Makes sense to add this VRR info to drm_hdmi_info struct an
GuC will set the min/max frequencies to theoretical max on
ATS-M. This will break kernel ABI, so limit min/max frequency
to RP0(platform max) instead.
Also modify the SLPC selftest to update the min frequency
when we have a server part so that we can iterate between
platform min and max.
v2: Chec
== Series Details ==
Series: drm/i915: Fix CFI violations in gt_sysfs (rev4)
URL : https://patchwork.freedesktop.org/series/108917/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12257 -> Patchwork_108917v4
Summary
---
== Series Details ==
Series: drm/i915: Fix CFI violations in gt_sysfs (rev4)
URL : https://patchwork.freedesktop.org/series/108917/
State : warning
== Summary ==
Error: dim checkpatch failed
33f051ef3eac drm/i915: Fix CFI violations in gt_sysfs
-:123: CHECK:LINE_SPACING: Please use a blank lin
== Series Details ==
Series: series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY
register accesses
URL : https://patchwork.freedesktop.org/series/109834/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12257 -> Patchwork_109834v1
===
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.
v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
Individualize fences before adding to dma_r
== Series Details ==
Series: series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY
register accesses
URL : https://patchwork.freedesktop.org/series/109834/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY
register accesses
URL : https://patchwork.freedesktop.org/series/109834/
State : warning
== Summary ==
Error: dim checkpatch failed
3b99286d8d78 drm/i915/tgl+: Add locking around DKL PHY register
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects
Not all Dekel PHY registers have a lane instance, so having to specify
this when using them is awkward. It makes more sense to define each PHY
register with its full internal PHY offset where bits 15:12 is the lane
for lane-instanced PHY registers and just a register bank index for other
PHY regist
Move the TypeC DKL PHY register definitions to intel_tc_phy_regs.h next
to the TypeC MG PHY registers.
No functional changes.
Signed-off-by: Imre Deak
---
.../i915/display/intel_display_power_well.c | 1 +
.../gpu/drm/i915/display/intel_tc_phy_regs.h | 186 ++
drivers/gpu/d
Accessing the TypeC DKL PHY registers during modeset-commit,
-verification, DP link-retraining and AUX power well toggling is racy
due to these code paths being concurrent and the PHY register bank
selection register (HIP_INDEX_REG) being shared between PHY instances
(aka TC ports) and the bank sel
On Tue, Oct 18, 2022 at 05:03:16PM +0100, Matthew Auld wrote:
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.
v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_C
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.
v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND
v4: replace vm->vm_bind_mode check with
On Mon, Oct 17, 2022 at 10:55:25AM +0200, Andrzej Hajda wrote:
> GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse.
> The bug was introduced during conversion to intel_uncore_rmw helper.
>
> Suggested-by: Matt Roper
> Fixes: 8cee664d3eb6f8 ("drm/i915: use proper helper for register up
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.
Signed-off-by: Niranjana Vishwanathapura
Sign
The following changes since commit 48407ffd7adb9511701547068b1e6f0956bd1c94:
cnm: update chips&media wave521c firmware. (2022-10-17 10:20:43 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware dg2_huc_7.10.3_pr
for you to fetch changes up to 8f86b5a
On 14/10/2022 07:48, Niranjana Vishwanathapura wrote:
On Sun, Oct 09, 2022 at 11:58:18PM -0700, Niranjana Vishwanathapura wrote:
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
Signed-off-by: Niranjana Vishwanatha
On Tue, Oct 18, 2022 at 04:53:50PM +0200, Juergen Gross wrote:
>> If we don't need the IS_ENABLED is not needed I'm all for dropping it.
>> But unless I misread the code, on arm/arm64 even PV guests are 1:1
>> mapped so that all Linux physically contigous memory also is Xen
>> contigous, so we don'
On 18.10.22 16:33, Christoph Hellwig wrote:
On Tue, Oct 18, 2022 at 04:21:43PM +0200, Jan Beulich wrote:
Leaving the "i915 abuses" part aside (because I can't tell what exactly the
abuse is), but assuming that "can't cope with bounce buffering" means they
don't actually use the allocated buffers
On Tue, Oct 18, 2022 at 04:21:43PM +0200, Jan Beulich wrote:
> Leaving the "i915 abuses" part aside (because I can't tell what exactly the
> abuse is), but assuming that "can't cope with bounce buffering" means they
> don't actually use the allocated buffers, I'd suggest this:
Except for one odd p
On Mon, 2022-10-17 at 20:05 +, Patchwork wrote:
Patch Details
Series: drm/i915: Extend Wa_1607297627 to Alderlake-P
URL:https://patchwork.freedesktop.org/series/109772/
State: failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109772v1/index.html
CI Bug Log - chang
Pushed to drm-intel-next.
Thanks for Review.
Br,
Anshuman Gupta.
From: Patchwork
Sent: Friday, October 14, 2022 7:01 PM
To: Gupta, Anshuman
Cc: intel-gfx@lists.freedesktop.org
Subject: ✓ Fi.CI.IGT: success for drm/i915/dgfx: Temporary hammer to keep
autosuspend control 'on' (rev2)
Patch Detai
== Series Details ==
Series: drm/i915: Print return value on error (rev3)
URL : https://patchwork.freedesktop.org/series/109722/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12255 -> Patchwork_109722v3
Summary
---
*
On 10/18/22 14:34, Christian König wrote:
> Am 18.10.22 um 01:07 schrieb Dmitry Osipenko:
>> On 10/17/22 20:22, Dmitry Osipenko wrote:
>>> Hello,
>>>
>>> This series moves all drivers to a dynamic dma-buf locking
>>> specification.
>>> From now on all dma-buf importers are made responsible for hol
Den 18.10.2022 11.33, skrev Maxime Ripard:
> On Mon, Oct 17, 2022 at 12:44:45PM +0200, Noralf Trønnes wrote:
>> Den 13.10.2022 15.18, skrev Maxime Ripard:
>>> As part of the command line parsing rework coming in the next patches,
>>> we'll need to lookup drm_connector_tv_mode values by their nam
Am 18.10.22 um 01:07 schrieb Dmitry Osipenko:
On 10/17/22 20:22, Dmitry Osipenko wrote:
Hello,
This series moves all drivers to a dynamic dma-buf locking specification.
From now on all dma-buf importers are made responsible for holding
dma-buf's reservation lock around all operations performed
On Tue, Oct 18, 2022 at 10:57:37AM +0200, Jan Beulich wrote:
> Shouldn't this then be xen_pv_domain() that you use here, and - if you
> really want IS_ENABLED() in addition - CONFIG_XEN_PV?
I'll need help from people that understand Xen better than me what
the exact conditions (and maybe also comm
Hello stable team, please backport these two commits to stable kernels
v5.19 and v6.0:
4e78d6023c15 ("drm/i915/bios: Validate fp_timing terminator presence")
d3a7051841f0 ("drm/i915/bios: Use hardcoded fp_timing size for generating LFP
data pointers")
References:
https://lore.kernel.org/r/fac
On Fri, 14 Oct 2022, "Kahola, Mika" wrote:
> Maybe these could be moved into intel_cx0_reg_defs.h file?
Register definitions to intel_cx0_regs.h. See
$ find drivers/gpu/drm/i915/ -name "*_regs.h"
Any common helpers such as REG_FIELD_GET8() and friends to
i915_reg_defs.h where we already have so
On Mon, Oct 17, 2022 at 04:32:28PM +0200, Hans de Goede wrote:
> Hi,
>
> On 10/17/22 15:35, Jani Nikula wrote:
> > On Mon, 17 Oct 2022, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 10/17/22 13:19, Thorsten Leemhuis wrote:
> >>> CCing the regression mailing list, as it should be in the loop for all
On Mon, Oct 17, 2022 at 12:31:31PM +0200, Noralf Trønnes wrote:
> Den 16.10.2022 20.52, skrev Mateusz Kwiatkowski:
> >> static int vc4_vec_connector_get_modes(struct drm_connector *connector)
> >> {
> >> - struct drm_connector_state *state = connector->state;
> >>struct drm_display_mode *mod
On Mon, Oct 17, 2022 at 12:44:45PM +0200, Noralf Trønnes wrote:
> Den 13.10.2022 15.18, skrev Maxime Ripard:
> > As part of the command line parsing rework coming in the next patches,
> > we'll need to lookup drm_connector_tv_mode values by their name, already
> > defined in drm_tv_mode_enum_list.
== Series Details ==
Series: series starting with [1/2] drm/i915/pps: Add get_pps_idx() hook as part
of pps_get_register() cleanup
URL : https://patchwork.freedesktop.org/series/109820/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12254 -> Patchwork_109820v1
On Mon, Oct 17, 2022 at 12:37:56PM +0200, Andrzej Hajda wrote:
> This patch replaces all occurences of the form
> intel_uncore_write(reg, intel_uncore_read(reg) OP val)
> with intel_uncore_rmw.
>
> Signed-off-by: Andrzej Hajda
> ---
> Apparently I have missed this pattern during refactoring.
>
>
Thanks Jani for review.
Floated a new version after addressing the review comments in this series.
https://patchwork.freedesktop.org/series/109820/
Regards,
Animesh
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, October 17, 2022 6:39 PM
> To: Manna, Animesh ; intel-
> g...@lis
Simplified pps_get_register() which use get_pps_idx() hook to derive the
pps instance and get_pps_idx() will be initialized at pps_init().
v1: Initial version. Got r-b from Jani.
v2: Corrected unintentional change around memset() call. [Jani]
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Uma Shankar
S
>From display gen12 onwards to support dual EDP two instances of pps added.
Currently backlight controller and pps instance can be mapped together
for a specific panel. Currently dual PPS support is broken. This patch
fixes it and enables for display 12+.
v1: Iniital revision.
v2: Called intel_bio
Hi,
On Sun, Oct 16, 2022 at 09:46:49PM +0200, Mateusz Kwiatkowski wrote:
> @@ -308,14 +324,15 @@ static const struct vc4_vec_tv_mode vc4_vec_tv_modes[]
> = {
> };
>
> static inline const struct vc4_vec_tv_mode *
> -vc4_vec_tv_mode_lookup(unsigned int mode)
> +vc4_vec_tv_mode_lookup(unsigned i
== Series Details ==
Series: i915 "GPU HANG", bisected to a2daa27c0c61 "swiotlb: simplify
swiotlb_max_segment"
URL : https://patchwork.freedesktop.org/series/109817/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/109817/revisions/1/mbox/ not
appl
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