== Series Details ==
Series: Fixes integer overflow or integer truncation issues in page lookups,
ttm place configuration and scatterlist creation (rev2)
URL : https://patchwork.freedesktop.org/series/110413/
State : warning
== Summary ==
Error: dim checkpatch failed
dd0ceb452378 overflow: In
Small typos in commit message (inline below)
Otherwise the change looks good to me
Reviewed-by: Ankit Nautiyal
On 10/26/2022 5:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Split the EXT2_MAX register progrmaming into its own funciton.
nitpick : 'programming' , 'function' typos.
Regar
== Series Details ==
Series: drm/i915: rename intel_gsc to intel_heci_gsc
URL : https://patchwork.freedesktop.org/series/110446/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_110446v1_full
Summary
--
Seems the offset is same since IVB.
The Gamma correction max seem to be defined since IVB, but this doesnt
seem to be used during ivb_load_luts, but only for multi-segmented gamma.
Is it that the default value of 1.0 is sufficient for other platforms?
Regards,
Ankit
On 10/26/2022 5:08 PM, V
On 02-Nov-22 3:02 PM, Jani Nikula wrote:
On Wed, 02 Nov 2022, Swati Sharma wrote:
Hi Matt,
Yes. Though h/w supports DSC from gen10, DSC is enabled from gen11+ from
driver.
We can see "has_dsc" flag enabled in gen11+.
#define GEN11_FEATURES \
>---.__runtime.has_dsc = 1, \
Also, in the
Lets use RUNTIME_INFO->has_dsc since platforms supporting dsc has this
flag enabled.
This is done based on the review comments received on
https://patchwork.freedesktop.org/patch/509393/
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
drivers/gpu/drm/i915/d
Looks Good to me.
Reviewed-by: Ankit Nautiyal
On 10/26/2022 5:08 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Switch intel_color.c over to the modern 'i915' variable
naming scehme. The only exceptions are the i9xx LUT access
functions which still need the magic 'dev_priv' for the
register ma
Makes sense.
LGTM.
Reviewed-by: Ankit Nautiyal
On 10/26/2022 5:08 PM, Ville Syrjala wrote:
From: Ville Syrjälä
No need to use _MMIO_PIPE2() for SKL_BOTTOM_COLOR
since all pipe registers are evenly spread on skl+.
Switch to _MMIO_PIPE() and thus avoid the hidden dev_priv.
Signed-off-by: Vil
Looks good to me.
Reviewed-by: Ankit Nautiyal
On 10/26/2022 5:08 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Use sizeof(variable) instead of sizeof(type) in the hopes of
less chance of screwing things up.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 16 +
> From: Jason Gunthorpe
> Sent: Tuesday, November 1, 2022 8:49 PM
> > > ---
> > > drivers/gpu/drm/i915/gvt/kvmgt.c | 3 +
> > > drivers/s390/cio/vfio_ccw_ops.c | 3 +
> > > drivers/s390/crypto/vfio_ap_ops.c | 3 +
> > > drivers/vfio/container.c | 108 ++--
== Series Details ==
Series: Fix for two GuC issues (rev2)
URL : https://patchwork.freedesktop.org/series/110269/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_110269v2_full
Summary
---
**FAIL
> From: Jason Gunthorpe
> Sent: Tuesday, November 1, 2022 7:51 PM
>
> On Tue, Nov 01, 2022 at 02:19:04AM -0700, Nicolin Chen wrote:
> > On Tue, Nov 01, 2022 at 08:09:52AM +, Tian, Kevin wrote:
> >
> > > > From: Jason Gunthorpe
> > > > Sent: Wednesday, October 26, 2022 2:51 AM
> > > >
> > > >
> From: Jason Gunthorpe
> Sent: Tuesday, November 1, 2022 8:26 PM
> And this:
>
> /*
>* If the device does not have
> IOMMU_CAP_ENFORCE_CACHE_COHERENCY then
>* any domain later attached to it will also not support it. If the cap
>* is set then the iommu_domain eventu
== Series Details ==
Series: DSC slice/PSR2 SU panel y granularity alignment
URL : https://patchwork.freedesktop.org/series/110434/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_110434v1_full
Summary
== Series Details ==
Series: drm/i915: Don't wait forever in drop_caches (rev2)
URL : https://patchwork.freedesktop.org/series/110395/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12333 -> Patchwork_110395v2
Summary
--
== Series Details ==
Series: drm/i915: Don't wait forever in drop_caches (rev2)
URL : https://patchwork.freedesktop.org/series/110395/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or
member 'lock
== Series Details ==
Series: drm/i915: Don't wait forever in drop_caches (rev2)
URL : https://patchwork.freedesktop.org/series/110395/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/tgl+: Enable DC power states on all eDP ports
URL : https://patchwork.freedesktop.org/series/110433/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_110433v1_full
From: John Harrison
At the end of each test, IGT does a drop caches call via debugfs with
special flags set. One of the possible paths waits for idle with an
infinite timeout. That causes problems for debugging issues when CI
catches a "can't go idle" test failure. Best case, the CI system times
On 11/2/2022 07:20, Tvrtko Ursulin wrote:
On 02/11/2022 12:12, Jani Nikula wrote:
On Tue, 01 Nov 2022, john.c.harri...@intel.com wrote:
From: John Harrison
At the end of each test, IGT does a drop caches call via sysfs with
sysfs?
Sorry, that was meant to say debugfs. I've also been working
== Series Details ==
Series: drm/i915/pps: improve eDP power on flow. (rev3)
URL : https://patchwork.freedesktop.org/series/110038/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12333 -> Patchwork_110038v3
Summary
---
== Series Details ==
Series: drm/i915/selftest: Bump up sample period for busy stats selftest
URL : https://patchwork.freedesktop.org/series/110454/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12333 -> Patchwork_110454v1
== Series Details ==
Series: drm/i915: Introduce the GSC CS
URL : https://patchwork.freedesktop.org/series/110432/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_110432v1_full
Summary
---
**FAI
After i915 dirver initialized, a panel power off cycle delay
always append before turn eDP on. If eDP display did not
power on before. With this change, power off duration might
longer than power cycle delay. So driver can save power cycle
delay to speed up driver initialization time.
v2: fix comm
On 11/2/2022 14:43, Daniele Ceraolo Spurio wrote:
On MTL there are no BCS engines on the media GT, so we can't always use
BCS0 in the test. There is no actual reason to use a BCS engine over an
engine of a different class, so switch to using any available engine.
Signed-off-by: Daniele Ceraolo S
On Wed, Nov 02, 2022 at 12:18:37PM +, Matthew Auld wrote:
> On Tue, 1 Nov 2022 at 21:58, Brian Norris wrote:
> >
> > On Fri, Oct 28, 2022 at 5:24 PM Patchwork
> > wrote:
> > >
> > > Patch Details
> > > Series:drm/i915: Set PROBE_PREFER_ASYNCHRONOUS
> > > URL:https://patchwork.freedesktop.org/
Engine busyness samples around a 10ms period is failing with busyness
ranging approx. from 87% to 115%. The expected range is +/- 5% of the
sample period.
When determining busyness of active engine, the GuC based engine
busyness implementation relies on a 64 bit timestamp register read. The
latenc
== Series Details ==
Series: drm/i915/guc: don't hardcode BCS0 in guc_hang selftest
URL : https://patchwork.freedesktop.org/series/110448/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12333 -> Patchwork_110448v1
Summary
--
== Series Details ==
Series: drm/i915/guc: don't hardcode BCS0 in guc_hang selftest
URL : https://patchwork.freedesktop.org/series/110448/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or
member '
== Series Details ==
Series: drm/i915/selftests: Reduce oversaturation of request smoketesting
URL : https://patchwork.freedesktop.org/series/110426/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_110426v1_full
===
Hi Niranjana,
On Tue, Nov 01, 2022 at 10:14:16PM -0700, Niranjana Vishwanathapura wrote:
> Currently on DG1, which do not have LLC, we hit the below
> warning while rebinding an userptr invalidated object.
>
> WARNING: CPU: 4 PID: 13008 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:34
> __i915_ge
== Series Details ==
Series: drm/i915: rename intel_gsc to intel_heci_gsc
URL : https://patchwork.freedesktop.org/series/110446/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_110446v1
Summary
---
*
On Wed, Nov 02, 2022 at 06:57:51PM +0200, Ville Syrjälä wrote:
> On Thu, Oct 27, 2022 at 06:53:23PM +0200, Peter Zijlstra wrote:
> > On Thu, Oct 27, 2022 at 04:09:01PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 26, 2022 at 01:43:00PM +0200, Peter Zijlstra wrote:
> >
> > > > Could you please giv
== Series Details ==
Series: vfio-ccw parent rework (rev2)
URL : https://patchwork.freedesktop.org/series/109899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_109899v2_full
Summary
---
**FAIL
== Series Details ==
Series: drm/i915: rename intel_gsc to intel_heci_gsc
URL : https://patchwork.freedesktop.org/series/110446/
State : warning
== Summary ==
Error: dim checkpatch failed
205e96968cdd drm/i915: rename intel_gsc to intel_heci_gsc
-:108: WARNING:FILE_PATH_CHANGES: added, moved o
== Series Details ==
Series: drm/i915: rename intel_gsc to intel_heci_gsc
URL : https://patchwork.freedesktop.org/series/110446/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hi Niranjana,
On Tue, Nov 01, 2022 at 10:14:16PM -0700, Niranjana Vishwanathapura wrote:
> Currently on DG1, which do not have LLC, we hit the below
> warning while rebinding an userptr invalidated object.
>
> WARNING: CPU: 4 PID: 13008 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:34
> __i915_ge
I had a massive disk crash, and my pull request is unsigned this one time.
However, it is signed with the promise the next tag will be signed again!
-
drm-misc-fixes-2022-11-02-1:
drm-misc-fixes for v6.1-rc4:
- Small fixes to make rockchip work better.
- Fix imx Kconfig.
- Small fix to imx' mo
On MTL there are no BCS engines on the media GT, so we can't always use
BCS0 in the test. There is no actual reason to use a BCS engine over an
engine of a different class, so switch to using any available engine.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
---
drivers/gpu/drm/i915/
Starting on MTL, the GSC FW is loaded at runtime and will be managed
directly by i915. This means we now have a naming clash around the GSC,
as we have 2 different aspects of it that we need to handle: the HECI
interfaces we export pre-mtl and the new full FW loading and support we
have to introduc
== Series Details ==
Series: Fix for two GuC issues (rev2)
URL : https://patchwork.freedesktop.org/series/110269/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_110269v2
Summary
---
**SUCCESS**
N
== Series Details ==
Series: Fixes integer overflow or integer truncation issues in page lookups,
ttm place configuration and scatterlist creation
URL : https://patchwork.freedesktop.org/series/110413/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12332_full -> Patchwork_1104
On Thu, Jul 14, 2022 at 01:24:14PM +0900, Naoya Horiguchi wrote:
> +/*
> + * pud_huge() returns 1 if @pud is hugetlb related entry, that is normal
> + * hugetlb entry or non-present (migration or hwpoisoned) hugetlb entry.
> + * Otherwise, returns 0.
> + */
> int pud_huge(pud_t pud)
> {
> - r
== Series Details ==
Series: DSC slice/PSR2 SU panel y granularity alignment
URL : https://patchwork.freedesktop.org/series/110434/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_110434v1
Summary
---
On 11/2/22 3:29 PM, Eric Farman wrote:
> On Wed, 2022-11-02 at 16:01 +0100, Eric Farman wrote:
>> Move the stuff associated with the mdev parent (and thus the
>> subchannel struct) into its own struct, and leave the rest in
>> the existing private structure.
>>
>> The subchannel will point to the p
== Series Details ==
Series: drm/i915/tgl+: Enable DC power states on all eDP ports
URL : https://patchwork.freedesktop.org/series/110433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_110433v1
Summary
--
On Wed, Nov 02, 2022 at 12:52:32PM +0100, Rasmus Villemoes wrote:
> On 24/10/2022 22.11, Gwan-gyeong Mun wrote:
> > From: Kees Cook
> >
> > Implement a robust overflows_type() macro to test if a variable or
> > constant value would overflow another variable or type. This can be
> > used as a cons
== Series Details ==
Series: drm/i915/tgl+: Enable DC power states on all eDP ports
URL : https://patchwork.freedesktop.org/series/110433/
State : warning
== Summary ==
Error: dim checkpatch failed
41570281b352 drm/i915: Allocate power domain set wakerefs dynamically
087d66bbc539 drm/i915: Mov
== Series Details ==
Series: drm/i915/tgl+: Enable DC power states on all eDP ports
URL : https://patchwork.freedesktop.org/series/110433/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, 2022-11-02 at 16:01 +0100, Eric Farman wrote:
> Move the stuff associated with the mdev parent (and thus the
> subchannel struct) into its own struct, and leave the rest in
> the existing private structure.
>
> The subchannel will point to the parent, and the parent will point
> to the pri
== Series Details ==
Series: drm/i915: Introduce the GSC CS
URL : https://patchwork.freedesktop.org/series/110432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_110432v1
Summary
---
**SUCCESS**
From: John Harrison
If a context has already been registered prior to first submission
then context init code was not being called. The noticeable effect of
that was the scheduling priority was left at zero (meaning super high
priority) instead of being set to normal. This would occur with
kernel
From: John Harrison
The engine busyness stats has a worker function to do things like
64bit extend the 32bit hardware counters. The GuC's reset prepare
function flushes out this worker function to ensure no corruption
happens during the reset. Unforunately, the worker function has an
infinite wai
From: John Harrison
Fix for a deadlock issue between the GuC busyness stats worker and GT
resets. Also fix kernel contexts not getting the correct scheduling
priority at start of day.
v2: Rename existing uses of _trylock rather than adding a _noretry
version. Also improve the comment a bit.
Sig
== Series Details ==
Series: drm/i915: header cleanups, again
URL : https://patchwork.freedesktop.org/series/110404/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12331_full -> Patchwork_110404v1_full
Summary
---
**F
On Wed, Nov 02, 2022 at 08:34:48PM +0200, Imre Deak wrote:
> On Wed, Nov 02, 2022 at 07:35:17PM +0200, Ville Syrjälä wrote:
> > On Wed, Nov 02, 2022 at 07:15:26PM +0200, Imre Deak wrote:
> > > Starting with TGL eDP is supported on ports B+ (besides port A), so make
> > > sure DC states are not bloc
On Wed, 02 Nov 2022, Imre Deak wrote:
> Factor out functions to get/put the AUX_IO power domain for the main
> link on DDI ports.
>
> While at it clarify the corresponding code comment.
>
> No functional change.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 84 +
== Series Details ==
Series: drm/i915: Introduce the GSC CS
URL : https://patchwork.freedesktop.org/series/110432/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Introduce the GSC CS
URL : https://patchwork.freedesktop.org/series/110432/
State : warning
== Summary ==
Error: dim checkpatch failed
0cfd9bdf1be5 drm/i915/mtl: add initial definitions for GSC CS
31fe0d686c6a drm/i915/mtl: pass the GSC CS info to the GuC
On Wed, 02 Nov 2022, Imre Deak wrote:
> Since the intel_display_power_domain_set struct, currently its current
> size close 1kB, can be allocated on the stack, it's better to allocate
> the per-domain wakeref pointer array - used for debugging - within the
> struct dynamically, so do this.
>
> The
== Series Details ==
Series: drm/i915/display: clear plane color control register when turn plane
off (rev2)
URL : https://patchwork.freedesktop.org/series/106883/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_106883v2
==
Hi Ville,
On 11/2/2022 6:55 PM, Ville Syrjälä wrote:
On Mon, Oct 24, 2022 at 10:08:29AM +0200, Das, Nirmoy wrote:
On 10/21/2022 6:34 PM, Ville Syrjälä wrote:
On Fri, Sep 23, 2022 at 09:35:14AM +0200, Nirmoy Das wrote:
i915_gem_drain_freed_objects() might not be enough to
free all the objects
On Wed, Nov 02, 2022 at 07:35:17PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 02, 2022 at 07:15:26PM +0200, Imre Deak wrote:
> > Starting with TGL eDP is supported on ports B+ (besides port A), so make
> > sure DC states are not blocked on any such ports. For this add an
> > AUX_IO_ power domain for
== Series Details ==
Series: drm/i915/display: clear plane color control register when turn plane
off (rev2)
URL : https://patchwork.freedesktop.org/series/106883/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Funct
== Series Details ==
Series: drm/i915/selftests: Reduce oversaturation of request smoketesting
URL : https://patchwork.freedesktop.org/series/110426/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_110426v1
On Wed, Nov 02, 2022 at 07:45:43PM +0200, Jouni Högander wrote:
> Do not enable psr2 if panel ganularity is not aligned with DSC slice
> height when DSC is enabled
>
> Cc: José Roberto de Souza
> Cc: Mika Kahola
>
> Signed-off-by: Jouni Högander
This check against DSC makes sense since we hav
On Mon, Oct 24, 2022 at 10:08:29AM +0200, Das, Nirmoy wrote:
>
> On 10/21/2022 6:34 PM, Ville Syrjälä wrote:
> > On Fri, Sep 23, 2022 at 09:35:14AM +0200, Nirmoy Das wrote:
> >> i915_gem_drain_freed_objects() might not be enough to
> >> free all the objects and RCU delayed work might get
> >> sche
On Wed, 2022-11-02 at 19:45 +0200, Jouni Högander wrote:
> Selective update area is now aligned with DSC slice height when
> DSC is enabled. Remove inappropriate warning about missing DSC
> alignment.
Reviewed-by: José Roberto de Souza
>
> Cc: José Roberto de Souza
> Cc: Mika Kahola
>
> Fixe
On Wed, 2022-11-02 at 19:45 +0200, Jouni Högander wrote:
> Do not enable psr2 if panel ganularity is not aligned with DSC slice
> height when DSC is enabled
>
Reviewed-by: José Roberto de Souza
> Cc: José Roberto de Souza
> Cc: Mika Kahola
>
> Signed-off-by: Jouni Högander
> ---
> drivers/
On Tue, 2022-11-01 at 21:02 +, Souza, Jose wrote:
> On Tue, 2022-11-01 at 20:55 +, Hogander, Jouni wrote:
> > On Tue, 2022-11-01 at 20:00 +, Souza, Jose wrote:
> > > On Fri, 2022-10-21 at 08:49 +0300, Jouni Högander wrote:
> > > > Selective update area is now aligned with DSC slice heig
Selective update area is now aligned with DSC slice height when
DSC is enabled. Remove inappropriate warning about missing DSC
alignment.
Cc: José Roberto de Souza
Cc: Mika Kahola
Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/
Do not enable psr2 if panel ganularity is not aligned with DSC slice
height when DSC is enabled
Cc: José Roberto de Souza
Cc: Mika Kahola
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/di
This patchset ensures panel y granularity aligns with DSC slice height
and disable PSR2 if this is not the case. Also inappropriate DSC
alignment warning is removed.
Cc: José Roberto de Souza
Cc: Mika Kahola
Jouni Högander (2):
drm/i915/psr: Ensure panel granularity aligns with DSC slice hei
On Wed, Nov 02, 2022 at 07:15:26PM +0200, Imre Deak wrote:
> Starting with TGL eDP is supported on ports B+ (besides port A), so make
> sure DC states are not blocked on any such ports. For this add an
> AUX_IO_ power domain for each port with eDP support. These domains
> similarly to AUX_IO_A enab
On 02/11/2022 15:57, Nirmoy Das wrote:
From: Chris Wilson
The goal in launching the request smoketest is to have sufficient tasks
running across the system such that we are likely to detect concurrency
issues. We aim to have 2 tasks using the same engine, gt, device (each
level of locking ar
Starting with TGL eDP is supported on ports B+ (besides port A), so make
sure DC states are not blocked on any such ports. For this add an
AUX_IO_ power domain for each port with eDP support. These domains
similarly to AUX_IO_A enable only the AUX_IO_ power well for an
enabled port, whereas the exi
MTL+ requires the AUX_IO power for the main link only on eDP, so don't
enable it in other cases.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/
BXT and GLK were missing the AUX_IO_A power domain -> PHY A common power
well mapping, add these now. This didn't cause a problem as the
AUX_IO_A and DDI_LANES_A power domains are acquired together.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_power_map.c | 2 ++
1 fil
Add the missing DC_OFF power domain -> DC_OFF power well mappings on all
platforms. This didn't cause a problem as the DC_OFF power domain is
only used on JSL, where the mapping was already correct.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_power_map.c | 8
Factor out functions to get/put the AUX_IO power domain for the main
link on DDI ports.
While at it clarify the corresponding code comment.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 84 ++--
1 file changed, 51 insertions(+
Since the intel_display_power_domain_set struct, currently its current
size close 1kB, can be allocated on the stack, it's better to allocate
the per-domain wakeref pointer array - used for debugging - within the
struct dynamically, so do this.
The memory freeing is guaranteed by the fact that the
Move the definition of the AUX_IO_A power domain, requiring only the
corresponding AUX_IO_A power well to be enabled, before all the
AUX_ power domains, which require both the AUX_IO_ and the
DC_OFF power wells to be enabled.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i9
The patchset makes sure that the display DC power states are enabled on
all eDP ports; atm these can stay blocked on the TGL+ ports B+. It
also has a few minor related display power domain fixes.
Imre Deak (7):
drm/i915: Allocate power domain set wakerefs dynamically
drm/i915: Move the POWER_D
== Series Details ==
Series: vfio-ccw parent rework (rev2)
URL : https://patchwork.freedesktop.org/series/109899/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_109899v2
Summary
---
**SUCCESS**
N
We need to tell the GuC that the GSC CS is there.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 11 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +--
2 files changed, 10 insertions(+), 8 deleti
There is no userspace user for this CS yet, we only need it for internal
kernel ops (e.g. HuC, PXP), so don't expose it.
v2: even if it's not exposed, rename the engine so it is easier to
identify in the debug logs (Matt)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
---
drivers/gpu/drm
The GSC CS has its own dedicated bit in the GDRST register.
Bspec: 52549
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matt Roper
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
2 files changed, 2 insertions(+)
diff --g
The GSC CS re-uses the same interrupt bits that the GSC used in older
platforms. This means that we can now have an engine interrupt coming
out of OTHER_CLASS, so we need to handle that appropriately.
v2: clean up the if statement for the engine irq (Tvrtko)
Signed-off-by: Daniele Ceraolo Spurio
Starting on MTL, the GSC is no longer managed with direct MMIO access,
but we instead have a dedicated command streamer for it. As a first step
for adding support for this CS, add the required definitions.
Note that, although it is now a CS, the GSC retains its old
class:instance value (OTHER_CLASS
Starting on MTL, the GSC microcontroller resides inside the media GT
and the driver can communicate with it via a new Command Streamer, the
GSC CS. As a first step in supporting the GSC integration within the
media GT, this series adds the required defines and basic support for
this CS. Note that,
On Wed, 02 Nov 2022, Jani Nikula wrote:
> On Fri, 14 Oct 2022, Mika Kahola wrote:
>> Create a separate file to store registers for PICA chips
>> C10 and C20.
>>
>> Signed-off-by: Radhakrishna Sripada
>> Signed-off-by: Mika Kahola
>> ---
>> .../gpu/drm/i915/display/intel_cx0_reg_defs.h | 136 ++
On Thu, Oct 27, 2022 at 06:53:23PM +0200, Peter Zijlstra wrote:
> On Thu, Oct 27, 2022 at 04:09:01PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 26, 2022 at 01:43:00PM +0200, Peter Zijlstra wrote:
>
> > > Could you please give the below a spin?
> >
> > Thanks. I've added this to our CI branch. I'
On Fri, 14 Oct 2022, Mika Kahola wrote:
> Create a separate file to store registers for PICA chips
> C10 and C20.
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Mika Kahola
> ---
> .../gpu/drm/i915/display/intel_cx0_reg_defs.h | 136 ++
> 1 file changed, 136 insertions
== Series Details ==
Series: vfio-ccw parent rework (rev2)
URL : https://patchwork.freedesktop.org/series/109899/
State : warning
== Summary ==
Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or
member 'lock' not described in 'i
== Series Details ==
Series: vfio-ccw parent rework (rev2)
URL : https://patchwork.freedesktop.org/series/109899/
State : warning
== Summary ==
Error: dim checkpatch failed
23f3cebda691 vfio/ccw: create a parent struct
-:57: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
== Series Details ==
Series: Fixes integer overflow or integer truncation issues in page lookups,
ttm place configuration and scatterlist creation
URL : https://patchwork.freedesktop.org/series/110413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12332 -> Patchwork_110413v1
Re-reported.
-Original Message-
From: Nikula, Jani
Sent: Wednesday, November 2, 2022 8:17 AM
To: Patchwork
Cc: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: header cleanups, again
On Wed, 02 Nov 2022, Patchwork wrote:
> == Se
On Wed, Nov 02, 2022 at 05:09:27PM +0100, Das, Nirmoy wrote:
On 11/2/2022 11:36 AM, Matthew Auld wrote:
On 02/11/2022 07:39, Das, Nirmoy wrote:
On 11/2/2022 6:14 AM, Niranjana Vishwanathapura wrote:
Currently on DG1, which do not have LLC, we hit the below
warning while rebinding an userptr
== Series Details ==
Series: Fixes integer overflow or integer truncation issues in page lookups,
ttm place configuration and scatterlist creation
URL : https://patchwork.freedesktop.org/series/110413/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode use
== Series Details ==
Series: Fixes integer overflow or integer truncation issues in page lookups,
ttm place configuration and scatterlist creation
URL : https://patchwork.freedesktop.org/series/110413/
State : warning
== Summary ==
Error: dim checkpatch failed
2d63cbfb6b5f overflow: Introduce
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