== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/110576/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12347 -> Patchwork_110576v1
Summary
---
**FAILURE**
Seriou
Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.
---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is
From: Swati Sharma
DSC_YCBCR420_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC YCbCr420.
Also, new debugfs entry is created to enforce YCbCr420 output format.
This is required because of our driver policy.
If a mode is supported in both RGB and YCbCr420 ou
From: Swati Sharma
If force_dsc_ycbcr420_en is set through debugfs allow DSC iff
output_format is INTEL_OUTPUT_FORMAT_YCBCR420.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.
From: Swati Sharma
Removed extra newlines and did few styling fixes.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gp
Implementation of VDSC for YCbCr420.
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 187 --
.../gpu/drm/i915/display/intel_qp_tables.h| 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
3 files changed, 180 insertions(+), 15 del
From: Ankit Nautiyal
Add helper function to check if the DP sink supports DSC with the given
output format.
Signed-off-by: Ankit Nautiyal
---
include/drm/display/drm_dp_helper.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display
From: Ankit Nautiyal
Go with DSC only if the given output_format is supported.
v2: Use drm helper to get DSC format support for sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 +
1 file changed, 28 insertions(+)
diff --git a/driver
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/i915_reg.h | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 765a10e0de88..89cb0
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding cor
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/110576/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/110576/
State : warning
== Summary ==
Error: dim checkpatch failed
5dd859f0d749 drm/dp_helper: Add helper to check if the sink supports given
format with DSC
-:20: CHECK:LINE_SPACING: Please u
From: Swati Sharma
Removed extra newlines and did few styling fixes.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gp
From: Swati Sharma
DSC_YCBCR420_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC YCbCr420.
Also, new debugfs entry is created to enforce YCbCr420 output format.
This is required because of our driver policy.
If a mode is supported in both RGB and YCbCr420 ou
Implementation of VDSC for YCbCr420.
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 187 --
.../gpu/drm/i915/display/intel_qp_tables.h| 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
3 files changed, 180 insertions(+), 15 del
From: Swati Sharma
If force_dsc_ycbcr420_en is set through debugfs allow DSC iff
output_format is INTEL_OUTPUT_FORMAT_YCBCR420.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.
Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.
---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is
From: Ankit Nautiyal
Go with DSC only if the given output_format is supported.
v2: Use drm helper to get DSC format support for sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 +
1 file changed, 28 insertions(+)
diff --git a/driver
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/i915_reg.h | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 765a10e0de88..89cb0
From: Ankit Nautiyal
Add helper function to check if the DP sink supports DSC with the given
output format.
Signed-off-by: Ankit Nautiyal
---
include/drm/display/drm_dp_helper.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding cor
From: Swati Sharma
If force_dsc_ycbcr420_en is set through debugfs allow DSC iff
output_format is INTEL_OUTPUT_FORMAT_YCBCR420.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.
From: Swati Sharma
Removed extra newlines and did few styling fixes.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gp
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/i915_reg.h | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 765a10e0de88..89cb0
Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.
---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is
From: Ankit Nautiyal
Go with DSC only if the given output_format is supported.
v2: Use drm helper to get DSC format support for sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 +
1 file changed, 28 insertions(+)
diff --git a/driver
Implementation of VDSC for YCbCr420.
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 187 --
.../gpu/drm/i915/display/intel_qp_tables.h| 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
3 files changed, 180 insertions(+), 15 del
From: Swati Sharma
DSC_YCBCR420_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC YCbCr420.
Also, new debugfs entry is created to enforce YCbCr420 output format.
This is required because of our driver policy.
If a mode is supported in both RGB and YCbCr420 ou
From: Ankit Nautiyal
Add helper function to check if the DP sink supports DSC with the given
output format.
Signed-off-by: Ankit Nautiyal
---
include/drm/display/drm_dp_helper.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding cor
Add new struture to store FRL related configurations for a pipe.
These members to be calculated during compute config phase, when FRL
mode is to be used.
Signed-off-by: Ankit Nautiyal
---
.../drm/i915/display/intel_display_types.h| 23 +++
1 file changed, 23 insertions(+)
di
Add support for FRL Link training state and transition
to different states during FRL Link training.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 383 ++
drivers/gpu/drm/i915/display/intel_hdm
In FRL mode, the Scrambling is always enabled by the HW.
The High TMDS Char Rate and Scrambing Enable bit of
reg TRANS_DDI_FUNC_CTRL are only set in TMDS mode and not
in FRL mode.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +++-
1 file changed, 7 insertio
In case of HDMI2.1 FRL training failure for a given mode, the user
should be sent a uevent signalling Link failure.
This patch adds support for sending uevent to userspace in case of link
training failure.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 30
While disabling HDMI, reset the FRL transcoder config if FRL mode was
used.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_
For platforms supporting HDMI2.1 we need to fill the lane count
in Transcoder and DDI/PORT registers for FRL mode.
Similarly, FRL SHIFTER ENABLE, and DATA_WIDTH bits are to be set
in FRL mode. These bits are written in both the DDI_BUF_CTL and
PORT_BUF_CTL registers.
Signed-off-by: Ankit Nautiyal
This patch adds the bits for port width for TRANS_DDI_FUNC_CTL and
port data width for DDI_BUF_CTL.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/i915_reg.h | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/
This patch adds bits related to HDMI2.1 in PORT_BUF_CTL_1 that
is needed to be programmed for D2D Interface for Ports in
IO expansion Die.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/d
Add registers for FRL configuration.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 765a10e0de88..b50e1349d22c 100644
--- a/drive
HDMI2.1 specifies new SCDC registers to configure FRL Training
between source and sink and get the FRL Training updated from
and HDMI2.1 sink.
This patch adds new SCDC registers and helper functions to
read and configure these registers.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/display
Re-use the drm helpers for getting max FRL rate for an HDMI sink.
This patch removes the duplicate code and calls the already defined
drm helpers for the task.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 -
1 file changed, 4 insertions(+), 13 de
From: Vandita Kulkarni
>From the max_frl_rate field of vbt parse the maxfrl_rate.
Signed-off-by: Vandita Kulkarni
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_bios.c | 51 +++
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i91
HDMI2.1 supports higher resolutions using Fixed Rate Link.
Source need to do FRL link training on the 4 lanes before video
stream transmission.
This patch adds the members to crtc_state and intel_hdmi for
identifying the FRL supporting HDMI sink and to maintain the frl
training information, after
From: Mika Kahola
(Patch is part of the series to add C10/C20 PHY support, which is in
review : https://patchwork.freedesktop.org/series/109714/)
Create a separate file to store registers for PICA chips
C10 and C20.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/d
Add the helpers for getting the max FRL rate with and without DSC
for an HDMI sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/drm_edid.c | 38 ++
include/drm/drm_edid.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/drm_ed
This set is RFC for adding support for HDMI2.1 FRL Link training.
FRL or Fixed Rate Link is defined by HDMI2.1 spec for supporting higher
bit-rate. As per HDMI2.1 specification, a new data-channel or lane is
added in FRL mode, by repurposing the TMDS clock Channel. This enables
HDMI to support 48 G
From: Swati Sharma
If force_dsc_ycbcr420_en is set through debugfs allow DSC iff
output_format is INTEL_OUTPUT_FORMAT_YCBCR420.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.
From: Swati Sharma
Removed extra newlines and did few styling fixes.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gp
From: Swati Sharma
DSC_YCBCR420_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC YCbCr420.
Also, new debugfs entry is created to enforce YCbCr420 output format.
This is required because of our driver policy.
If a mode is supported in both RGB and YCbCr420 ou
Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.
---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is
Implementation of VDSC for YCbCr420.
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 187 --
.../gpu/drm/i915/display/intel_qp_tables.h| 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
3 files changed, 180 insertions(+), 15 del
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/i915_reg.h | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 765a10e0de88..89cb0
From: Ankit Nautiyal
Add helper function to check if the DP sink supports DSC with the given
output format.
Signed-off-by: Ankit Nautiyal
---
include/drm/display/drm_dp_helper.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display
From: Ankit Nautiyal
Go with DSC only if the given output_format is supported.
v2: Use drm helper to get DSC format support for sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 28 +
1 file changed, 28 insertions(+)
diff --git a/driver
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding cor
== Series Details ==
Series: Add hwmon support for dgfx selftests (rev2)
URL : https://patchwork.freedesktop.org/series/109850/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12347_full -> Patchwork_109850v2_full
Summary
---
== Series Details ==
Series: Add hwmon support for dgfx selftests (rev2)
URL : https://patchwork.freedesktop.org/series/109850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12347 -> Patchwork_109850v2
Summary
---
**
== Series Details ==
Series: Add hwmon support for dgfx selftests (rev2)
URL : https://patchwork.freedesktop.org/series/109850/
State : warning
== Summary ==
Error: dim checkpatch failed
dfa6349c5bf1 drm/i915/selftests: Rename librapl library to libpower
Traceback (most recent call last):
Fi
== Series Details ==
Series: Add hwmon support for dgfx selftests (rev2)
URL : https://patchwork.freedesktop.org/series/109850/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./arch/x86/include/asm/bitop
From: Tilak Tangudu
hwmon provides an interface to read energy values for discrete graphics.
add hwmon support to the existing libpower library so that it can verify
power consumption values in different selftests.
Changed prototype of libpower_get_energy_uJ
Signed-off-by: Tilak Tangudu
Signed
Add an interface to obtain hwmon energy values. This is used
by selftest to verify power consumption
v2 : use i915_hwmon prefix (Anshuman)
Signed-off-by: Riana Tauro
---
drivers/gpu/drm/i915/i915_hwmon.c | 23 ---
drivers/gpu/drm/i915/i915_hwmon.h | 1 +
2 files changed, 21
Rename librapl files to libpower and replace librapl
with libpower prefix. No functional changes
v2: update commit message (Anshuman)
Signed-off-by: Riana Tauro
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 12 ++--
driver
Rename librapl library to libpower. Add hwmon support in libpower for
dgfx.
Use libpower in selftests.
Rev2 : Update commit message
Riana Tauro (2):
drm/i915/selftests: Rename librapl library to libpower
drm/i915/hwmon: Add helper function to obtain energy values
Tilak Tangudu (1):
drm/i9
Hi all,
After merging the drm-misc tree, today's linux-next build (htmldocs)
produced this warning:
include/drm/drm_fb_helper.h:204: warning: Function parameter or member
'hint_leak_smem_start' not described in 'drm_fb_helper'
Introduced by commit
e7c5c29a9eb1 ("drm/fb-helper: Set flag in st
Linus,
As discussed here:
https://lore.kernel.org/all/20221106212427.739928...@goodmis.org/
Add a "shutdown" state for timers. This is performed by the new
timer_shutdown_sync() and timer_shutdown() function calls. When this is
called on a timer, it will no longer be able to be re-armed. Th
On Tue, 22 Feb 2022 00:57:02 -0800, Andi Shyti wrote:
>
Old thread, new comment below at the bottom. Please take a look. Thanks.
> Hi Tvrtko and Joonas,
>
> > > > > > Now tiles have their own sysfs interfaces under the gt/
> > > > > > directory. Because RC6 is a property that can be configured on
del_timer_sync() is often called before the object that owns the timer is
freed. But sometimes there's a race that enables the timer again before it is
freed and causes a use after free when that timer triggers. This patch set
adds a new "shutdown" timer state, which is set on the new timer_shutdow
Den 27.10.2022 00.02, skrev Mateusz Kwiatkowski:
> Hi Maxime,
>
> First of all, nice idea with the helper function that can be reused by
> different
> drivers. This is neat!
>
> But looking at this function, it feels a bit overcomplicated. You're creating
> the two modes, then checking which
Den 26.10.2022 17.33, skrev max...@cerno.tech:
> Most of the TV connectors will need a similar get_modes implementation
> that will, depending on the drivers' capabilities, register the 480i and
> 576i modes.
>
> That implementation will also need to set the preferred flag and order
> the modes
Hi,
Can you tell me what are we waiting for? Maybe I can help.
Thanks.
Matthieu
On Wed, Oct 12 2022 at 07:16:29 PM +0200, Matthieu CHARETTE
wrote:
By crash, I mean that an error is returned here:
https://kernel.googlesource.com/pub/scm/linux/kernel/git/torvalds/linux.git/+/refs/heads/master
On Wed, Nov 2, 2022 at 4:23 PM Oded Gabbay wrote:
>
> On Mon, Sep 12, 2022 at 12:17 AM Michał Winiarski
> wrote:
> >
> > IDR is deprecated, and since XArray manages its own state with internal
> > locking, it simplifies the locking on DRM side.
> > Additionally, don't use the IRQ-safe variant, si
Den 26.10.2022 17.33, skrev max...@cerno.tech:
> Our new tv mode option allows to specify the TV mode from a property.
> However, it can still be useful, for example to avoid any boot time
> artifact, to set that property directly from the kernel command line.
>
> Let's add some code to allow i
Den 26.10.2022 17.33, skrev max...@cerno.tech:
> We'll need to get the pixel clock to generate proper display modes for
> all the current named modes. Let's add it to struct drm_cmdline_mode and
> fill it when parsing the named mode.
>
> Signed-off-by: Maxime Ripard
> ---
I would just squash
Den 26.10.2022 17.33, skrev max...@cerno.tech:
> The current code to deal with named modes will only set the mode name, and
> then it's up to drivers to try to match that name to whatever mode or
> configuration they see fit.
>
I couldn't find any driver that does that, all I could find that c
Like commit c4f135d643823a86 ("workqueue: Wrap flush_workqueue() using a
macro") says, flush_scheduled_work() is dangerous and will be forbidden.
We are on the way for removing all flush_scheduled_work() callers from
the kernel, and there are only 4 callers remaining as of linux-20221104.
driver
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