On 11/11/2022 2:08 AM, Ville Syrjälä wrote:
On Fri, Oct 28, 2022 at 03:14:03PM +0530, Ankit Nautiyal wrote:
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch adds new member to crtc_state to represent the final
output_format to
== Series Details ==
Series: series starting with [v2,1/4] i915: Move list_count() to list.h for
broader use
URL : https://patchwork.freedesktop.org/series/110870/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12379_full -> Patchwork_110870v1_full
test_plane_panning requires about 10 times bigger amount of memory than
memory required by framebuffer in default display mode. In case of some
configurations it can exceed available memory (4k modes on small-bar
systems), causing test aborts.
Closes:
The last user of macros from that include was removed in 2018 by the
commit below.
Fixes: 6cc42152b02b ("drm/i915: Remove support for legacy debugfs crc
interface")
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: David Airlie
Cc: Daniel Vetter
Cc:
On Tue, Nov 08, 2022 at 09:49:45AM +, Tvrtko Ursulin wrote:
On 07/11/2022 17:32, Lucas De Marchi wrote:
That section should still be inside "DRM client usage stats" rather than
as a sibling.
Signed-off-by: Lucas De Marchi
---
Documentation/gpu/drm-usage-stats.rst | 1 -
1 file changed,
On 11/11/2022 2:36 AM, Ville Syrjälä wrote:
On Fri, Oct 28, 2022 at 03:14:05PM +0530, Ankit Nautiyal wrote:
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch uses the members of intel_dp->dfp to only store the
format conversion
On 2022/11/14 22:37, Yang, Lixiao wrote:
> On 2022/11/14 20:51, Yi Liu wrote:
>> On 2022/11/10 00:57, Jason Gunthorpe wrote:
>>> On Tue, Nov 08, 2022 at 11:18:03PM +0800, Yi Liu wrote:
On 2022/11/8 17:19, Nicolin Chen wrote:
> On Mon, Nov 07, 2022 at 08:52:44PM -0400, Jason Gunthorpe
On Mon, 2022-11-14 at 20:17 -0800, Ceraolo Spurio, Daniele wrote:
>
> On 10/21/2022 10:39 AM, Alan Previn wrote:
> > Make intel_pxp_is_active a global check and implicitly find
> > the PXP-owning-GT.
> >
> > As per prior two patches, callers of this function shall now
> > pass in i915 since
On Mon, 2022-11-14 at 20:11 -0800, Ceraolo Spurio, Daniele wrote:
>
> On 10/21/2022 10:39 AM, Alan Previn wrote:
> > @@ -68,11 +69,34 @@ bool intel_gtpxp_is_supported(struct intel_pxp *pxp)
> > return false;
> > }
> >
> > -bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> >
On Mon, 2022-11-14 at 20:00 -0800, Ceraolo Spurio, Daniele wrote:
>
> On 10/21/2022 10:39 AM, Alan Previn wrote:
> > In preparation for future MTL-PXP feature support, PXP control
> > @@ -142,22 +166,21 @@ void intel_pxp_init(struct intel_pxp *pxp)
> > {
> > struct intel_gt *gt =
> > This patch series aims to enable the YCbCr420 format for DSC. Changes
> > are mostly compute params related for hdmi,dp and dsi along with the
> > addition of new rc_tables for native_420 and corresponding changes to
> > macros used to fetch them.
>
> Huh, what's the deal with all the series
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev12)
URL : https://patchwork.freedesktop.org/series/108156/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12378_full -> Patchwork_108156v12_full
Summary
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Tuesday, November 15, 2022 1:27 AM
> To: Gupta, Anshuman
> Cc: intel-gfx@lists.freedesktop.org; kamil.koniec...@linux.intel.com;
> Tangudu, Tilak ; Nilawar, Badal
>
> Subject: Re: [PATCH i-g-t v2 1/3] lib/igt_pm: Refactor get
On 10/21/2022 10:39 AM, Alan Previn wrote:
Make intel_pxp_key_check implicitly find the PXP-owning-GT.
Callers of this function shall now pass in i915 since PXP
is a global GPU feature. Make intel_pxp_key_check implicitly
find the right gt to verify pxp session key establishment count
so it's
On 10/21/2022 10:39 AM, Alan Previn wrote:
Make intel_pxp_is_start implicitly find the PXP-owning-GT.
Callers of this function shall now pass in i915 since PXP
is a global GPU feature. Make intel_pxp_start implicitly
find the right gt to start PXP arb session so
it's transparent to the
On 10/21/2022 10:39 AM, Alan Previn wrote:
Ensure i915_pxp_tee_component_bind / unbind implicitly sorts out
getting the correct per-GT PXP control-context from the PXP-owning-GT
when establishing or ending connection. Thus, replace _i915_to_pxp_gt
with intel_pxp_get_owning_gt (also takes in
On 10/21/2022 10:39 AM, Alan Previn wrote:
Make intel_pxp_is_active a global check and implicitly find
the PXP-owning-GT.
As per prior two patches, callers of this function shall now
pass in i915 since PXP is a global GPU feature. Make
intel_pxp_is_active implicitly find the right gt so it's
On 10/21/2022 10:39 AM, Alan Previn wrote:
Make intel_pxp_is_enabled a global check and implicitly find the
PXP-owning-GT.
PXP feature support is a device-config flag. In preparation for MTL
PXP control-context shall reside on of the two GT's. That said,
update intel_pxp_is_enabled to take
On 10/21/2022 10:39 AM, Alan Previn wrote:
In preparation for future MTL-PXP feature support, PXP control
context should only valid on the correct gt tile. Depending on the
device-info this depends on which tile owns the VEBOX and KCR.
PXP is still a global feature though (despite its
On Tue, Nov 15, 2022 at 12:55:42AM +, Sean Christopherson wrote:
> On Tue, Nov 15, 2022, Yan Zhao wrote:
> > On Mon, Nov 14, 2022 at 11:24:16PM +, Sean Christopherson wrote:
> > > On Tue, Nov 15, 2022, Yan Zhao wrote:
> > > > On Mon, Nov 14, 2022 at 04:32:34PM +, Sean Christopherson
On 11/9/22 11:57 AM, Jason Gunthorpe wrote:
> On Tue, Nov 08, 2022 at 11:18:03PM +0800, Yi Liu wrote:
>> On 2022/11/8 17:19, Nicolin Chen wrote:
>>> On Mon, Nov 07, 2022 at 08:52:44PM -0400, Jason Gunthorpe wrote:
>>>
This is on github: https://github.com/jgunthorpe/linux/commits/vfio_iommufd
== Series Details ==
Series: drm/i915: drm/i915/tgl+: Enable DC power states on all eDP ports
URL : https://patchwork.freedesktop.org/series/110862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12377_full -> Patchwork_110862v1_full
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add missing checks for
cdclk crawling
URL : https://patchwork.freedesktop.org/series/110882/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12379 -> Patchwork_110882v1
On Mon, Nov 14, 2022 at 04:07:13PM -0800, Srivatsa, Anusha wrote:
>
>
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Monday, November 14, 2022 4:01 PM
> > To: Srivatsa, Anusha
> > Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
> >
> > Subject: Re: [PATCH 2/3]
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Add missing checks for
cdclk crawling
URL : https://patchwork.freedesktop.org/series/110882/
State : warning
== Summary ==
Error: dim checkpatch failed
77c35543c996 drm/i915/display: Add missing checks for cdclk
== Series Details ==
Series: series starting with [v2,1/4] i915: Move list_count() to list.h for
broader use
URL : https://patchwork.freedesktop.org/series/110870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12379 -> Patchwork_110870v1
== Series Details ==
Series: drm/i915: Finish (de)gamma readout (rev8)
URL : https://patchwork.freedesktop.org/series/79614/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12379 -> Patchwork_79614v8
Summary
---
> -Original Message-
> From: Roper, Matthew D
> Sent: Monday, November 14, 2022 4:01 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
>
> Subject: Re: [PATCH 2/3] drm/i915/display: Do both crawl and squash when
> changing cdclk
>
> On Mon, Nov 14, 2022
On Mon, Nov 14, 2022 at 03:14:33PM -0800, Srivatsa, Anusha wrote:
...
> > > +static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > > + const struct intel_cdclk_config *cdclk_config,
> > > + enum pipe pipe)
> > > +{
> > > + struct intel_cdclk_config
== Series Details ==
Series: series starting with [v2,1/4] i915: Move list_count() to list.h for
broader use
URL : https://patchwork.freedesktop.org/series/110870/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
On Mon, Nov 14, 2022 at 11:24:16PM +, Sean Christopherson wrote:
> On Tue, Nov 15, 2022, Yan Zhao wrote:
> > On Mon, Nov 14, 2022 at 04:32:34PM +, Sean Christopherson wrote:
> > > On Mon, Nov 14, 2022, Yan Zhao wrote:
> > > > On Sat, Nov 12, 2022 at 12:43:07AM +, Sean Christopherson
== Series Details ==
Series: drm/i915: Finish (de)gamma readout (rev8)
URL : https://patchwork.freedesktop.org/series/79614/
State : warning
== Summary ==
Error: dim checkpatch failed
88c0420d5b67 drm/i915: Clean up legacy palette defines
d4d9f8eed90c drm/i915: Clean up 10bit precision
> -Original Message-
> From: Roper, Matthew D
> Sent: Monday, November 14, 2022 2:16 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä
>
> Subject: Re: [PATCH 2/3] drm/i915/display: Do both crawl and squash when
> changing cdclk
>
> On Mon, Nov 14, 2022
On 11/7/2022 8:56 PM, Alan Previn wrote:
Previously, we only used PXP FW interface version-42 structures for
PXP arbitration session on ADL/TGL products and version-43 for HuC
authentication on DG2. That worked fine despite not differentiating such
versioning of the PXP firmware interaction
On Mon, Nov 14, 2022 at 04:32:34PM +, Sean Christopherson wrote:
> On Mon, Nov 14, 2022, Yan Zhao wrote:
> > On Sat, Nov 12, 2022 at 12:43:07AM +, Sean Christopherson wrote:
> > > On Sat, Nov 12, 2022, Yan Zhao wrote:
> > > > And I'm also not sure if a slots_arch_lock is required for
> > >
== Series Details ==
Series: drm: Analog TV Improvements (rev10)
URL : https://patchwork.freedesktop.org/series/107892/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12378 -> Patchwork_107892v10
Summary
---
== Series Details ==
Series: drm: Analog TV Improvements (rev10)
URL : https://patchwork.freedesktop.org/series/107892/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm: Analog TV Improvements (rev10)
URL : https://patchwork.freedesktop.org/series/107892/
State : warning
== Summary ==
Error: dim checkpatch failed
33225d7686a2 docs/fb: Document current named modes
8c65b8e4719a drm/tests: Add Kunit Helpers
-:33:
On Mon, Nov 14, 2022 at 12:57:16PM -0800, Anusha Srivatsa wrote:
> From: Ville Syrjälä
>
> For MTL, changing cdclk from between certain frequencies has
> both squash and crawl. Use the current cdclk config and
> the new(desired) cdclk config to construtc a mid cdclk config.
> Set the cdclk
On 11/10/2022 01:43, Tvrtko Ursulin wrote:
On 09/11/2022 17:46, John Harrison wrote:
On 11/9/2022 03:05, Tvrtko Ursulin wrote:
On 08/11/2022 20:15, John Harrison wrote:
On 11/8/2022 01:01, Tvrtko Ursulin wrote:
On 07/11/2022 19:14, John Harrison wrote:
On 11/7/2022 08:17, Tvrtko Ursulin
On 11/10/2022 02:33, Jani Nikula wrote:
On Wed, 09 Nov 2022, Michal Wajdeczko wrote:
Instead of merging this patch now, oriented on GT only, I would rather
wait until we discuss and plan solution for the all sub-components.
Once that's done (with agreement on naming and output) we can start
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev12)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12378 -> Patchwork_108156v12
Summary
---
== Series Details ==
Series: drm/edid/firmware: stop using a throwaway platform device
URL : https://patchwork.freedesktop.org/series/110859/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12376_full -> Patchwork_110859v1_full
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev12)
URL : https://patchwork.freedesktop.org/series/108156/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Mon, Nov 07, 2022 at 04:30:28PM -0800, Lucas De Marchi wrote:
> There were several updates in the driver on how the workarounds are
> handled since its documentation was written. Update the documentation to
> reflect the current reality.
>
> Signed-off-by: Lucas De Marchi
> ---
>
From: Ville Syrjälä
For MTL, changing cdclk from between certain frequencies has
both squash and crawl. Use the current cdclk config and
the new(desired) cdclk config to construtc a mid cdclk config.
Set the cdclk twice:
- Current cdclk -> mid cdclk
- mid cdclk -> desired cdclk
v2: Add check in
As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
cdclk_sanitize() function was written assuming vco was a signed integer.
vco gets assigned to -1 (essentially ~0) for the case where PLL
might be enabled and vco is not a frequency that will ever
get used. In such a scenario the right thing to do is disable the
PLL and re-enable it again with a
== Series Details ==
Series: drm/i915: drm/i915/tgl+: Enable DC power states on all eDP ports
URL : https://patchwork.freedesktop.org/series/110862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12377 -> Patchwork_110862v1
On Mon, Nov 14, 2022 at 06:08:41PM +0530, Anshuman Gupta wrote:
> Created igt_pm_open_pci_firmware_node() to refactor
> the retrieving the firmware_node fd code.
>
> igt_pm_open_pci_firmware_node() will be used by other
> firmware_node consumers.
>
> While doing that fixed the leaked fd as well.
== Series Details ==
Series: drm/i915: drm/i915/tgl+: Enable DC power states on all eDP ports
URL : https://patchwork.freedesktop.org/series/110862/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Mon, Nov 14, 2022 at 01:02:46PM +0200, Jani Nikula wrote:
> On Mon, 14 Nov 2022, Hans de Goede wrote:
> > Hi,
> >
> > On 11/14/22 11:10, Jani Nikula wrote:
> >> On Mon, 14 Nov 2022, Hans de Goede wrote:
> >>> Hi,
> >>>
> >>> On 11/14/22 00:23, Stephen Rothwell wrote:
> Hi all,
>
>
On Mon, Nov 14, 2022 at 10:21:50AM -0500, Matthew Rosato wrote:
> On 11/14/22 9:59 AM, Jason Gunthorpe wrote:
> > On Mon, Nov 14, 2022 at 09:55:21AM -0500, Matthew Rosato wrote:
> AFAICT there is no equivalent means to specify
> vfio_iommu_type1.dma_entry_limit when using iommufd; looks
On Mon, Nov 14, 2022 at 01:11:23PM +0200, Jani Nikula wrote:
> On Fri, 11 Nov 2022, "Steven 'Steve' Kendall" wrote:
> > Some machines with Intel UHD Graphics 620 (8086:5917) such as Dell
> > Latitude 7490 are unable to wake from sleep. Disable DMC for
> > Intel UHD Graphics 620.
>
> Cc: some
On Mon, Nov 14, 2022 at 1:22 PM Andy Shevchenko
wrote:
>
> The list API now provides the list_count() to help with counting
> existing nodes in the list. Uilise it.
s/Uilise/Utilise
== Series Details ==
Series: drm/edid/firmware: stop using a throwaway platform device
URL : https://patchwork.freedesktop.org/series/110859/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12376 -> Patchwork_110859v1
== Series Details ==
Series: drm/edid/firmware: stop using a throwaway platform device
URL : https://patchwork.freedesktop.org/series/110859/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12376 -> Patchwork_110859v1
Issue si related to https://gitlab.freedesktop.org/drm/intel/-/issues/6794.
Re-reported.
Lakshmi.
-Original Message-
From: Nikula, Jani
Sent: Monday, November 14, 2022 5:33 PM
To: Patchwork ; Vudum, Lakshminarayana
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.BAT: failure
On Mon, Nov 14, 2022 at 06:11:51PM +, Ruhl, Michael J wrote:
...
> So all of the non-list_for_each code appears to be an inline.
This is not true.
> This which, resembles the non-list_for_each pattern is a macro?
>
> Just curious as to why the macro rather than inline?
See above.
>-Original Message-
>From: dri-devel On Behalf Of
>Andy Shevchenko
>Sent: Monday, November 14, 2022 11:22 AM
>To: Jakob Koschel ; Andy Shevchenko
>; Greg Kroah-Hartman
>; Mathias Nyman
>; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org; linux-ker...@vger.kernel.org;
Den 14.11.2022 14.00, skrev Maxime Ripard:
> KMS supports a number of named modes already, but it's never been
> documented anywhere, let's fix that.
>
> Signed-off-by: Maxime Ripard
>
> ---
Reviewed-by: Noralf Trønnes
== Series Details ==
Series: drm/i915/pps: improve eDP power on flow. (rev4)
URL : https://patchwork.freedesktop.org/series/110038/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12375_full -> Patchwork_110038v4_full
The list API now provides the list_count() to help with counting
existing nodes in the list. Uilise it.
Signed-off-by: Andy Shevchenko
---
v2: no change
drivers/usb/gadget/udc/bcm63xx_udc.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git
The list API now provides the list_count() to help with counting
existing nodes in the list. Uilise it.
Signed-off-by: Andy Shevchenko
---
v2: no change
drivers/usb/host/xhci-ring.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/host/xhci-ring.c
Some of the existing users, and definitely will be new ones, want to
count existing nodes in the list. Provide a generic API for that by
moving code from i915 to list.h.
Signed-off-by: Andy Shevchenko
---
v2: dropped the duplicate code in i915 (LKP)
drivers/gpu/drm/i915/gt/intel_engine_cs.c |
The list API now provides the list_count() to help with counting
existing nodes in the list. Uilise it.
Signed-off-by: Andy Shevchenko
---
v2: no change
drivers/usb/gadget/legacy/hid.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/gadget/legacy/hid.c
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, November 11, 2022 11:40 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D
>
> Subject: Re: [PATCH] drm/i915/display: Add missing checks for cdclk crawling
>
> On Fri, Nov 11, 2022 at
From: Ville Syrjälä
Some gen2/gen3 parts have a 10bit gamma mode, on some pipes.
Expose it.
The format is different to the later i965+ style in that we
store a 10bit value and a 6 bit floating point slope for each
entry. Ie. the hardware extrapolates the intermediate steps
from the current LUT
From: Ville Syrjälä
On ilk+ and glk class hardware we current make a mess of
things when we have to both generate limited range output
and use the hw gamma LUT. Since we do the range compression
using the pipe CSC unit (which is situated before the gamma
LUT in the pipe) we are in fact applying
From: Ville Syrjälä
Currently crtc_state_is_legacy_gamma() has a very specific set
of conditions, not all of which are actually necessary. Also
Also when we detect those conditions check_luts() just skips
all the checks. That will no longer work for glk soon when we'll
start to use the hw
From: Ville Syrjälä
Use consistent bit definitions for the 10bit precision palette bits.
We just define these alongside the ilk/snb register definitions and
point to those from the ivb+ defines.
Also use the these appropriately in the LUT entry pack/unpack
functions.
Reviewed-by: Jani Nikula
From: Ville Syrjälä
Add the approproate c8_planes checks to make the LUT
code ready for C8 palette readout. Note we currently
lack the actual c8_planes readout, so this won't work
yet. But no harm in making the code somewhat more ready
for the day when we do get c8_planes readout.
From: Ville Syrjälä
We now have all the code necessary for gamma/degamma readout on
ivb/hsw. Plug it all in. As with bdw+ the cooked {pre,post}_csc_lut
make this trivial even in split gamma mode.
Note that on HSW if IPS is enabled the hardware will hang if
you try to access the LUT in split
From: Ville Syrjälä
Every platform now implemnts .read_luts(). Make it mandatory.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening.
From: Ville Syrjälä
Rename a the LUT state check foo_gamma_precision() functions
to foo_post_csc_lut_precision() to make it more clear what
they really do.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 22 +++---
1 file changed, 11
From: Ville Syrjälä
On glk we can no longer reorder the hw LUTS vs. pipe CSC like
we could on eaerlier platforms, and neither do we have a
separate output CSC like on icl+. That means if we use the
pipe CSC for YCbCr output we are currently applying the gamma
LUT after the RGB->YCbCr conversion,
From: Ville Syrjälä
We have full readout now for all platforms (sans the icl+
multi-segment readout hw fail), so hook up the LUT state
checker for everyone.
We add a new vfunc for this since different platforms need
to handle the details a bit differently.
The implementation is rather
From: Ville Syrjälä
Satisfy my ocd and define ilk_lut_12p4_ldw() before ilk_lut_12p4_udw().
That is the order all the other similar functions use.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 16
1 file changed, 8
From: Ville Syrjälä
Since CHV has the dedicate CGM degamma unit readout is trivial.
Just do it.
v2: deal with post_csc_lut
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 36 ++
1 file changed, 36 insertions(+)
diff
From: Ville Syrjälä
The degamma LUT is interpolated so we need the 128th (==1.0)
entry to represent the full < 1.0 input range. Only the 129th
and 130th entries are strictly for the >=1.0 extended range
inputs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
1 file
From: Ville Syrjälä
Just like ivb+, ilk/snb can select whether the hw lut acts as
gamma or degamma. Make the readout cognizant of that fact.
v2: deal with pre_csc_lut
v3: use ilk_has_post_csc_lut() helper
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Read out the gamma/degamma LUT on bdw+. Now that the
{pre,post}_csc_lut match the hardware LUT size even
in split gamma mode this is trivial.
v2: deal with {pre,post}_csc_lut
split gamma is no longer a problem
v3: add ilk_has_post_csc_lut() helper
Reviewed-by: Uma
From: Ville Syrjälä
Read out the degamma LUT on glk+. No state cheker as of yet since
it requires dealing with the glk csc vs. degamma mess.
v2: deal with post_csc_lut
v3: add icl_has_{pre,post}_csc_lut(*) helpers
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Add the missing ldw vs. udw information to the CGM (de)gamma
bit definitions to make it a bit easier to see which should
be used where.
Also use the these appropriately in the LUT entry pack/unpack
functions.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Use consistent bit definitions for the legacy gamma LUT. We just
define these alongside the pre-ilk register definitions and point
to those from the ilk+ defines.
Also use the these appropriately in the LUT entry pack/unpack
functions.
Reviewed-by: Jani Nikula
From: Ville Syrjälä
Use consistent bit definitions for the 12.4bit precision palette bits.
We just define these alongside the ilk/snb register definitions and
point to those from the icl+ superfine segment defines (and we also
already pointed to them from the ivb+ precision palette defines).
From: Ville Syrjälä
The gamma readout stuff was left half finished. No degamma
readout, and no readout whatsoever on ivb/bdw/skl/bxt.
Let's finish it.
Since we have the {pre,post}_csc_lut stuff this is fairly
easy to do now. The implementation of the LUT checker is
a bit more repetitive than
On Mon, 14 Nov 2022, Patchwork wrote:
> == Series Details ==
>
> Series: drm/edid/firmware: stop using a throwaway platform device
> URL : https://patchwork.freedesktop.org/series/110859/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12376 -> Patchwork_110859v1
>
On 11/14/22 9:59 AM, Jason Gunthorpe wrote:
> On Mon, Nov 14, 2022 at 09:55:21AM -0500, Matthew Rosato wrote:
AFAICT there is no equivalent means to specify
vfio_iommu_type1.dma_entry_limit when using iommufd; looks like
we'll just always get the default 65535.
>>>
>>> No, there is
== Series Details ==
Series: Enable Pipewriteback (rev10)
URL : https://patchwork.freedesktop.org/series/107440/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12375_full -> Patchwork_107440v10_full
Summary
---
On Mon, Nov 14, 2022 at 09:55:21AM -0500, Matthew Rosato wrote:
> >> AFAICT there is no equivalent means to specify
> >> vfio_iommu_type1.dma_entry_limit when using iommufd; looks like
> >> we'll just always get the default 65535.
> >
> > No, there is no arbitary limit on iommufd
>
> Yeah,
On 11/14/22 9:23 AM, Jason Gunthorpe wrote:
> On Thu, Nov 10, 2022 at 10:01:13PM -0500, Matthew Rosato wrote:
>> On 11/7/22 7:52 PM, Jason Gunthorpe wrote:
>>> This series provides an alternative container layer for VFIO implemented
>>> using iommufd. This is optional, if CONFIG_IOMMUFD is not set
On Fri, Nov 11, 2022 at 12:16:02PM +0800, Yi Liu wrote:
> > +#if IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER)
> > +MODULE_ALIAS_MISCDEV(VFIO_MINOR);
> > +MODULE_ALIAS("devname:vfio/vfio");
>
> will this line also result in systemd to create this devnodes at boot
> based on the module info even if
On Fri, Nov 11, 2022 at 12:12:36PM +0800, Yi Liu wrote:
> > +int vfio_iommufd_bind(struct vfio_device *vdev, struct iommufd_ctx *ictx)
> > +{
> > + u32 ioas_id;
> > + u32 device_id;
> > + int ret;
> > +
> > + lockdep_assert_held(>dev_set->lock);
> > +
> > + /*
> > +* If the driver
== Series Details ==
Series: drm/edid/firmware: stop using a throwaway platform device
URL : https://patchwork.freedesktop.org/series/110859/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12376 -> Patchwork_110859v1
On 2022/11/14 22:38, Jason Gunthorpe wrote:
On Mon, Nov 14, 2022 at 08:51:58PM +0800, Yi Liu wrote:
Our side, Yu He, Lixiao Yang has done below tests on Intel platform with
the above kernel, results are:
1) GVT-g test suit passed, Intel iGFx passthrough passed.
2) NIC passthrough test with
On Mon, Nov 14, 2022 at 08:51:58PM +0800, Yi Liu wrote:
> Our side, Yu He, Lixiao Yang has done below tests on Intel platform with
> the above kernel, results are:
>
> 1) GVT-g test suit passed, Intel iGFx passthrough passed.
>
> 2) NIC passthrough test with different guest memory (1G/4G),
On 2022/11/14 20:51, Yi Liu wrote:
> On 2022/11/10 00:57, Jason Gunthorpe wrote:
>> On Tue, Nov 08, 2022 at 11:18:03PM +0800, Yi Liu wrote:
>>> On 2022/11/8 17:19, Nicolin Chen wrote:
On Mon, Nov 07, 2022 at 08:52:44PM -0400, Jason Gunthorpe wrote:
> This is on github:
>
On Thu, Nov 10, 2022 at 10:01:13PM -0500, Matthew Rosato wrote:
> On 11/7/22 7:52 PM, Jason Gunthorpe wrote:
> > This series provides an alternative container layer for VFIO implemented
> > using iommufd. This is optional, if CONFIG_IOMMUFD is not set then it will
> > not be compiled in.
> >
> >
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