== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev7)
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12436 -> Patchwork_107550v7
Hi Jani,
Thank you for the patch.
On Wed, Oct 05, 2022 at 01:51:43PM +0300, Jani Nikula wrote:
> Add new function drm_connector_list_iter_filter_begin() to initialize
> connector list iterator with a filter function. Subsequent iteration on
> the list will only return connectors on which the filt
Currently we use the highest input BPC supported by DP sink while using
DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports
DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
input BPC that is used between Source and the PCON without DSC, which
might not work
Currently, DSC with YCBCR420 is not supported.
Return -EINVAL when trying with DSC with output_format as YCBCR420.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch adds new member to crtc_state to represent the final
output_format to the sink. In case of a DFP this can be different than
the output_format, as per the format conversion done via the P
Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 51 +++--
1 file changed, 2
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
v2: Rebase
S
Currently we compute the output format first and later try DSC if the
bandwidth without compression is not sufficient for that output format.
Since we do not support DSC with YCbCr420 format, this creates problem
for YCbCr420 only modes, that can be still be set if DFP has color
conversion and DSC
Add an inline helper function to check if the sink_format is set to
YCBCR420 format.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
drivers/gpu/drm/i915/display/intel_dp.c| 4 ++--
drivers/gpu/drm/i915/display/intel_hdmi.c |
New member to store the YCBCR20 Pass through capability of the DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/inte
Start passing the sink_format, to all functions that take a bool
ycbcr420_output as parameter. This will make the functions generic,
and will serve as a slight step towards 4:2:2 support later.
Suggested-by: Ville Syrj_l_
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device and uses the crtc_state
sink_format member, to program the protocol-converter for
colo
For YCbCr420 output, scaler is required for downsampling.
Scaler can be used only when source size smaller than 4096x5120.
So go for native YCbCr420 only if there are no scaler constraints.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 +++
1
This series fixes issues faced when an HDMI2.1 sink that does not
support DSC is connected via HDMI2.1PCON. It also includes other minor
HDMI2.1 PCON fixes/refactoring.
Patch 1-2 Have minor fixes/cleanups.
Patch 3-6 Pull the decision making to use DFP conversion capabilities
for every mode during
Hi Christian,
Looks good to me.
Reviewed-by: Arunpravin Paneer Selvam
for the series.
Regards,
Arun.
On 11/25/2022 3:51 PM, Christian König wrote:
We already fallback to a dummy BO with no backing store when we
allocate GDS,GWS and OA resources and to GTT when we allocate VRAM.
Drop all thos
== Series Details ==
Series: drm/i915: Fake dual eDP VBT fixes (rev4)
URL : https://patchwork.freedesktop.org/series/110693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12435 -> Patchwork_110693v4
Summary
---
**SUC
== Series Details ==
Series: drm/i915: Fake dual eDP VBT fixes (rev4)
URL : https://patchwork.freedesktop.org/series/110693/
State : warning
== Summary ==
Error: dim checkpatch failed
8a03452322e7 drm/i915: Introduce intel_panel_init_alloc()
3098cd62da06 drm/i915: Do panel VBT init early if th
From: Ville Syrjälä
Always include both the encoder and PPS instance information
in the debug prints so that we know what piece of hardware
we're actually dealing with.
v2: Make sure pps is selected before debug prints/etc. in
intel_pps_vdd_on_unlocked() on vlv/chv
There is no pps on pip
== Series Details ==
Series: drm/i915: Fake dual eDP VBT fixes (rev3)
URL : https://patchwork.freedesktop.org/series/110693/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12435 -> Patchwork_110693v3
Summary
---
**FAI
== Series Details ==
Series: drm/i915: Fake dual eDP VBT fixes (rev3)
URL : https://patchwork.freedesktop.org/series/110693/
State : warning
== Summary ==
Error: dim checkpatch failed
75c8e4541d7c drm/i915: Introduce intel_panel_init_alloc()
175ec6587f67 drm/i915: Do panel VBT init early if th
From: Ville Syrjälä
Always include both the encoder and PPS instance information
in the debug prints so that we know what piece of hardware
we're actually dealing with.
v2: Make sure pps is selected before debug prints/etc. in
intel_pps_vdd_on_unlocked() on vlv/chv
There is no pps on pip
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