Hello Jose,
Thank you for your comments. Please see my responses below and check
the new version I have sent.
On Tue, 2022-11-29 at 19:46 +0200, Jouni Högander wrote:
> On Tue, 2022-11-29 at 14:00 +, Souza, Jose wrote:
> > On Tue, 2022-11-29 at 09:51 +0200, Jouni Högander wrote:
> > >
== Series Details ==
Series: drm/i915/dp: wait on timeout before retry include sw delay (rev2)
URL : https://patchwork.freedesktop.org/series/111303/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12457 -> Patchwork_111303v2
Currently we are observing occasionally display flickering or complete
freeze. This is narrowed down to be caused by single full frame update
(SFF).
SFF bit after it's written gets cleared by HW in subsequent vblank
i.e. when the update is sent to the panel. SFF bit is required to be
written
== Series Details ==
Series: drm/i915/dp: wait on timeout before retry include sw delay (rev2)
URL : https://patchwork.freedesktop.org/series/111303/
State : warning
== Summary ==
Error: dim checkpatch failed
7b8a6c674948 drm/i915/dp: Change aux_ctl reg read to polling read
-:35:
The busy timeout logic checks for the AUX BUSY, then waits for the
timeout period and then after timeout reads the register for BUSY set
and fails.
Instead replace interrupt with polling so as to read the AUX CTL
register often before the timeout period.
v2: replace interrupt with polling read
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
This reverts commit 99510e1afb4863a225207146bd988064c5fd0629.
DSB is now getting disabled locally in the color management
code so we don't need to apply this big hammer via the device
info (not that we have other DSB users at
LGTM.
Reviewed-by: Ankit Nautiyal
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
The DSB has problem loading the LUTs at the moment. Some
of that is due to the palette anti collision logic, some
due to what seem real hw issues. Disable it the whole
thing locally in the
Patch looks good to me.
There are couple of minor nitpicks mentioned inline.
In any case this is:
Reviewed-by: Ankit Nautiyal
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
We could have many different uses for the DSB(s) during a
single commit, so the current approach of
== Series Details ==
Series: Align DDI_BUF_CTL Active timeouts with Bspec updates (rev3)
URL : https://patchwork.freedesktop.org/series/111373/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12457 -> Patchwork_111373v3
Makes sense to me.
Reviewed-by: Ankit Nautiyal
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
The use of DSB has to be done differently on a case by case basis.
So no way this kind of blind mmio fallback in the guts of the DSB
code will work properly. Move it at least one
LGTM.
Reviewed-by: Ankit Nautiyal
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Document the precision of the LUT "max" registers, just
so we don't have to dig through the spec so much.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 10 +-
LGTM.
Reviewed-by: Ankit Nautiyal
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Various gamma units on various platforms have some problems loading
the LUT index and auto-increment bit at the same time. We have to
do this in two steps. The first known case was the glk
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Use REG_BIT() & co. for the LUT index registers, and also
use the REG_FIELD_PREP() stuff a bit more consistently when
generating the values for said registers.
Signed-off-by: Ville Syrjälä
---
LGTM.
Reviewed-by: Ankit Nautiyal
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Use REG_BIT() & co. for GAMMA_MODE bits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git
LGTM.
Reviewed-by: Ankit Nautiyal
On 11/23/2022 8:56 PM, Ville Syrjala wrote:
From: Ville Syrjälä
s/GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED/GAMMA_MODE_MODE_12BIT_MULTI_SEG/
to make this thing slightly shorter.
Also fix up the platform comment while at it.
Signed-off-by: Ville Syrjälä
---
== Series Details ==
Series: series starting with [v5,1/4] i915: Move list_count() to list.h as
list_count_nodes() for broader use
URL : https://patchwork.freedesktop.org/series/111482/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12455_full -> Patchwork_111482v1_full
For Gen12+ wait for 1ms for Combo Phy and 3ms for TC Phy for
DDI_BUF_CTL to be active for TC phy. (Bspec:49190)
v2: Minor refactoring for better readability. (Imre)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++-
1 file changed, 14
On Wed, 30 Nov 2022 17:05:34 -0800, Umesh Nerlige Ramappa wrote:
>
> 0x20cc (WAIT_FOR_RC6_EXIT on other platforms) is repurposed on MTL. Use
> a separate mux table to verify oa configs passed by user.
> I looked for WAIT_FOR_RC6_EXIT in the bspec and did not find it defined for
> MTL, so it's
On Wed, 30 Nov 2022 17:05:32 -0800, Umesh Nerlige Ramappa wrote:
>
> On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem
> caused a hang that was attributed to saving and restoring the GPR
> registers used for noa_wait.
>
> Add an additional page in noa_wait BO to save/restore GPR
On Wed, 30 Nov 2022 17:05:33 -0800, Umesh Nerlige Ramappa wrote:
>
> Similar to ACM, OA timestamp that is part of the OA report is shifted
> when compared to the CS timestamp. Add MTL to the WA.
Reviewed-by: Ashutosh Dixit
>
> Signed-off-by: Umesh Nerlige Ramappa
> ---
>
On Wed, 30 Nov 2022 17:05:35 -0800, Umesh Nerlige Ramappa wrote:
>
> Without an entry in oa_init_supported_formats, OA will not be functional
> in MTL. Enable OA support by enabling 32 bit OAG formats for MTL.
Reviewed-by: Ashutosh Dixit
> Signed-off-by: Umesh Nerlige Ramappa
> ---
>
On Mon, 2022-11-28 at 16:48 -0800, Alan Previn wrote:
> A gap was recently discovered where if an application did not
> invalidate all of the stream keys (intentionally or not), and the
> driver did a full PXP global teardown on the GT subsystem, we
> find that future session creation would fail
== Series Details ==
Series: drm/i915/mtl: Add OAG 32 bit format support for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/111512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12457 -> Patchwork_111512v2
== Series Details ==
Series: drm/i915/mtl: Add OAG 32 bit format support for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/111512/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: add guard padding around i915_vma (rev4)
URL : https://patchwork.freedesktop.org/series/110720/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12457 -> Patchwork_110720v4
Summary
---
On Wed, Nov 30, 2022 at 05:05:31PM -0800, Umesh Nerlige Ramappa wrote:
Enable OA for MTL by adding 32-bit OA format support and relevant fixes.
Signed-off-by: Umesh Nerlige Ramappa
Test-with: 20221129010522.994524-1-umesh.nerlige.rama...@intel.com
0x20cc (WAIT_FOR_RC6_EXIT on other platforms) is repurposed on MTL. Use
a separate mux table to verify oa configs passed by user.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git
Without an entry in oa_init_supported_formats, OA will not be functional
in MTL. Enable OA support by enabling 32 bit OAG formats for MTL.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem
caused a hang that was attributed to saving and restoring the GPR
registers used for noa_wait.
Add an additional page in noa_wait BO to save/restore GPR registers for
the noa_wait logic.
Signed-off-by: Umesh Nerlige Ramappa
---
Similar to ACM, OA timestamp that is part of the OA report is shifted
when compared to the CS timestamp. Add MTL to the WA.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
Enable OA for MTL by adding 32-bit OA format support and relevant fixes.
Signed-off-by: Umesh Nerlige Ramappa
Test-with: 20221129010522.994524-1-umesh.nerlige.rama...@intel.com
Umesh Nerlige Ramappa (4):
drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs
drm/i915/mtl: Add
== Series Details ==
Series: add guard padding around i915_vma (rev4)
URL : https://patchwork.freedesktop.org/series/110720/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: add guard padding around i915_vma (rev4)
URL : https://patchwork.freedesktop.org/series/110720/
State : warning
== Summary ==
Error: dim checkpatch failed
6a062612120d drm/i915: Limit the display memory alignment to 32 bit instead of
64
ab5c06d48524 drm/i915:
Without an entry in oa_init_supported_formats, OA will not be functional
in MTL. Enable OA support by enabling 32 bit OAG formats for MTL.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Similar to ACM, OA timestamp that is part of the OA report is shifted
when compared to the CS timestamp. Add MTL to the WA.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
Enable OA for MTL by adding 32-bit OA format support and relevant fixes.
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige Ramappa (4):
drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs
drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch
drm/i915/mtl: Update
0x20cc (WAIT_FOR_RC6_EXIT on other platforms) is repurposed on MTL. Use
a separate mux table to verify oa configs passed by user.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git
On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem
caused a hang that was attributed to saving and restoring the GPR
registers used for noa_wait.
Add an additional page in noa_wait BO to save/restore GPR registers for
the noa_wait logic.
Signed-off-by: Umesh Nerlige Ramappa
---
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Initial display workarounds
URL : https://patchwork.freedesktop.org/series/111507/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12457 -> Patchwork_111507v1
On 11/23/2022 12:45, Michal Wajdeczko wrote:
On 23.11.2022 02:25, John Harrison wrote:
On 11/22/2022 09:54, Michal Wajdeczko wrote:
On 18.11.2022 02:58, john.c.harri...@intel.com wrote:
From: John Harrison
Re-work the existing GuC CT printers and extend as required to match
the new wrapping
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Initial display workarounds
URL : https://patchwork.freedesktop.org/series/111507/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Initial display workarounds
URL : https://patchwork.freedesktop.org/series/111507/
State : warning
== Summary ==
Error: dim checkpatch failed
8c18d75df531 drm/i915/mtl: Initial display workarounds
-:122:
On 11/29/2022 00:43, Tvrtko Ursulin wrote:
On 28/11/2022 16:52, Andrzej Hajda wrote:
In case context is exiting preempt_timeout_ms is used for timeout,
but since introduction of DRM_I915_PREEMPT_TIMEOUT_COMPUTE it increases
to 7.5 seconds. Heartbeat occurs earlier but it is still 2.5s.
Fixes:
From: Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the
vma (depending on the scanout orientation). bspec recommends that we
provide a tile-row in either directions, and suggests using 168 PTE,
warning that the accesses will wrap around the ends of the GGTT.
This reverts commit 2ef6efa79fecd5e3457b324155d35524d95f2b6b.
Checking the presence if the IRST (Intel Rapid Start Technology)
through the ACPI to decide whether to rebuild or not the GGTT
puts us at the mercy of the boot firmware and we need to
unnecessarily rely on third parties.
Because now
From: Chris Wilson
Introduce the concept of padding the i915_vma with guard pages before
and after. The major consequence is that all ordinary uses of i915_vma
must use i915_vma_offset/i915_vma_size and not i915_vma.node.start/size
directly, as the drm_mm_node will include the guard pages that
From: Chris Wilson
We already wrap i915_vma.node.start for use with the GGTT, as there we
can perform additional sanity checks that the node belongs to the GGTT
and fits within the 32b registers. In the next couple of patches, we
will introduce guard pages around the objects _inside_ the
The coming commit "drm/i915: Introduce guard pages to i915_vma"
from Chris, was originally changing display_alignment to u32
from u64. The reason is that the display GGTT is and will be
limited o 4GB.
Put it in a separate patch and use "max(...)" instead of
"max_t(64, ...)" when asigning the
Hi,
This series adds guards around vma's but setting a pages at the
beginning and at the end that work as padding.
The first user of the vma guard are scanout objects which don't
need anymore to add scratch to all the unused ggtt's and speeding
up up considerably the boot and resume by several
On Wed, Nov 30, 2022 at 12:14:20PM -0800, Dixit, Ashutosh wrote:
On Wed, 30 Nov 2022 12:00:57 -0800, Umesh Nerlige Ramappa wrote:
On Tue, Nov 29, 2022 at 05:51:13PM -0800, Dixit, Ashutosh wrote:
> On Mon, 28 Nov 2022 17:21:46 -0800, Umesh Nerlige Ramappa wrote:
>>
>> +/*
>> + * Ref:
From: Matt Roper
This patch introduces initial workarounds for mtl platform
Bspec:66622
Signed-off-by: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 4 +-
From: Jouni Högander
This patch introduces initial workarounds for mtl platform
Bspec: 66624
Signed-off-by: Matt Atwood
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
On Wed, Nov 30, 2022 at 04:46:50PM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: dedicated MCR locking and hardware semaphore (rev3)
> URL : https://patchwork.freedesktop.org/series/111220/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12455 ->
On 11/30/2022 01:47, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* More GuC firmware version improvements (rev3)
*URL:* https://patchwork.freedesktop.org/series/111218/
*State:*failure
*Details:*
On 11/30/2022 00:30, Tvrtko Ursulin wrote:
On 29/11/2022 21:12, john.c.harri...@intel.com wrote:
From: John Harrison
Engine resets are supposed to never happen. But in the case when one
Engine resets or engine reset failures? Hopefully the latter.
Oops. Yes, that was meant to say "engine
== Series Details ==
Series: drm/i915/pvc: Implement recommended caching policy
URL : https://patchwork.freedesktop.org/series/111491/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12456 -> Patchwork_111491v1
Summary
On Wed, 30 Nov 2022 12:00:57 -0800, Umesh Nerlige Ramappa wrote:
>
> On Tue, Nov 29, 2022 at 05:51:13PM -0800, Dixit, Ashutosh wrote:
> > On Mon, 28 Nov 2022 17:21:46 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >> +/*
> >> + * Ref: 14010536224:
> >> + * 0x20cc is repurposed on MTL, so use a
On Tue, Nov 29, 2022 at 05:51:13PM -0800, Dixit, Ashutosh wrote:
On Mon, 28 Nov 2022 17:21:46 -0800, Umesh Nerlige Ramappa wrote:
+/*
+ * Ref: 14010536224:
+ * 0x20cc is repurposed on MTL, so use a separate array for MTL.
Wondering if it was WAIT_FOR_RC6_EXIT (seen in gen12_oa_mux_regs)
On Wed, 2022-11-30 at 18:43 +0100, Greg Kroah-Hartman wrote:
> On Wed, Nov 30, 2022 at 09:20:28AM -0500, Rodrigo Vivi wrote:
> > On Wed, Nov 16, 2022 at 02:47:33PM +0200, Alexander Usyskin wrote:
> > > When driver wakes up the firmware from the low power state,
> > > it is sending a memory ready
On Tue, Nov 29, 2022 at 10:05:18PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/hdmi: SPD infoframe update for discrete
> URL : https://patchwork.freedesktop.org/series/111450/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12446 ->
On Wed, Nov 30, 2022 at 09:20:28AM -0500, Rodrigo Vivi wrote:
> On Wed, Nov 16, 2022 at 02:47:33PM +0200, Alexander Usyskin wrote:
> > When driver wakes up the firmware from the low power state,
> > it is sending a memory ready message.
> > The send is done via synchronous/blocking function to
On Wed, 2022-11-30 at 09:32 -0800, Matt Roper wrote:
> On Tue, Nov 29, 2022 at 06:02:45PM -0800, Alan Previn wrote:
> > Starting with MTL, there will be two GT-tiles, a render and media
> > tile. PXP as a service for supporting workloads with protected
>
> Drive-by comment: we've been a bit
On Tue, Nov 29, 2022 at 06:02:45PM -0800, Alan Previn wrote:
> Starting with MTL, there will be two GT-tiles, a render and media
> tile. PXP as a service for supporting workloads with protected
Drive-by comment: we've been a bit inconsistent about terminology in
the past, but my understanding is
On Wed, Nov 30, 2022 at 09:07:23AM -0800, Wayne Boyer wrote:
> As per the performance tuning guide, set the HOSTCACHEEN bit to
> implement the recommended caching policy on PVC.
>
> Signed-off-by: Wayne Boyer
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
>
On Tue, Nov 29, 2022 at 06:15:23AM +, Patchwork wrote:
> == Series Details ==
>
> Series: i915: dedicated MCR locking and hardware semaphore (rev2)
> URL : https://patchwork.freedesktop.org/series/111220/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12440_full
On 11/29/2022 3:48 PM, Teres Alexis, Alan Previn wrote:
Besides the nit below, just would like to echo the same thing Nikula said about
not including the type definition in the
main uc header (which i know can be a bit more work especially if we go with
allocation of the structure at init
As per the performance tuning guide, set the HOSTCACHEEN bit to
implement the recommended caching policy on PVC.
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
2 files changed, 2 insertions(+)
diff --git
== Series Details ==
Series: i915: dedicated MCR locking and hardware semaphore (rev3)
URL : https://patchwork.freedesktop.org/series/111220/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12455 -> Patchwork_111220v3
== Series Details ==
Series: i915: dedicated MCR locking and hardware semaphore (rev3)
URL : https://patchwork.freedesktop.org/series/111220/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [v5,1/4] i915: Move list_count() to list.h as
list_count_nodes() for broader use
URL : https://patchwork.freedesktop.org/series/111482/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12455 -> Patchwork_111482v1
On Wed, Nov 30, 2022 at 09:21:07PM +0530, Balasubramani Vivekanandan wrote:
> On 28.11.2022 15:30, Matt Roper wrote:
> > PPAT setup involves a series of multicast writes. This can be optimized
> > slightly be acquiring forcewake and the steering lock just once for the
> > entire sequence.
> >
>
PPAT setup involves a series of multicast writes. This can be optimized
slightly be acquiring forcewake and the steering lock just once for the
entire sequence.
v2:
- We should use FW_REG_WRITE instead of FW_REG_READ. (Bala)
Suggested-by: Balasubramani Vivekanandan
Signed-off-by: Matt Roper
== Series Details ==
Series: series starting with [v5,1/4] i915: Move list_count() to list.h as
list_count_nodes() for broader use
URL : https://patchwork.freedesktop.org/series/111482/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit
On 28.11.2022 15:30, Matt Roper wrote:
> PPAT setup involves a series of multicast writes. This can be optimized
> slightly be acquiring forcewake and the steering lock just once for the
> entire sequence.
>
> Suggested-by: Balasubramani Vivekanandan
>
> Signed-off-by: Matt Roper
> ---
>
On 28.11.2022 15:30, Matt Roper wrote:
> We've been overloading uncore->lock to protect access to the MCR
> steering register. That's not really what uncore->lock is intended for,
> and it would be better if we didn't need to hold such a high-traffic
> spinlock for the whole sequence of (apply
On 28.11.2022 15:30, Matt Roper wrote:
> Passing the GT rather than uncore to the lowest level MCR read and write
> functions will make it easier to introduce dedicated MCR locking in a
> following patch.
>
> Signed-off-by: Matt Roper
Reviewed-by: Balasubramani Vivekanandan
Regards,
Bala
>
On 28.11.2022 15:30, Matt Roper wrote:
> The kerneldoc function name was not updated when this function was
> converted to a non-fw form.
>
> Fixes: 192bb40f030a ("drm/i915/gt: Manage uncore->lock while waiting on MCR
> register")
> Reported-by: kernel test robot
> Signed-off-by: Matt Roper
On Wed, Nov 16, 2022 at 02:47:33PM +0200, Alexander Usyskin wrote:
> When driver wakes up the firmware from the low power state,
> it is sending a memory ready message.
> The send is done via synchronous/blocking function to ensure
> that firmware is in ready state. However, in case of firmware
>
On Wed, 30 Nov 2022 at 14:43, Maxime Ripard wrote:
>
> Hi Maarten
>
> On Wed, Nov 30, 2022 at 02:16:05PM +0100, Maarten Lankhorst wrote:
> > A single fix to vmwgfx mks-guest-stats ioctl.
> > I lost my internet connection when pushing the tag, so I put together this
> > mail
> > manually. I hope
On Wed, 2022-11-30 at 10:42 -0300, Gustavo Sousa wrote:
> On Thu, Nov 24, 2022 at 01:27:40PM -0300, Gustavo Sousa wrote:
> > Just a quick note: firmware PR hasn't been applied yet. Waiting...
>
> Firmware PR merged into linux-firmware!
Thanks for the patch and the heads up.
Patch is now pushed
On Wed, 30 Nov 2022 at 14:03, Tvrtko Ursulin
wrote:
> On 29/11/2022 18:05, Matthew Auld wrote:
> > On Fri, 25 Nov 2022 at 11:14, Tvrtko Ursulin
> > wrote:
> >>
> >>
> >> + Matt
> >>
> >> On 25/11/2022 10:21, Christian König wrote:
> >>> TTM is just wrapping core DMA functionality here, remove
Some of the existing users, and definitely will be new ones, want to
count existing nodes in the list. Provide a generic API for that by
moving code from i915 to list.h.
Reviewed-by: Lucas De Marchi
Acked-by: Jani Nikula
Signed-off-by: Andy Shevchenko
---
v5: added tag (Lucas), renamed API to
The list API provides the list_count_nodes() to help with counting
existing nodes in the list. Utilise it.
Signed-off-by: Andy Shevchenko
---
v5: used renamed API (LKP)
v4: no change
v3: no change
v2: no change
drivers/usb/gadget/udc/bcm63xx_udc.c | 11 +++
1 file changed, 3
The list API provides the list_count_nodes() to help with counting
existing nodes in the list. Utilise it.
Signed-off-by: Andy Shevchenko
---
v5: used renamed API (LKP)
v4: no change
v3: fixed typo in the commit message (Fabio)
The list API provides the list_count_nodes() to help with counting
existing nodes in the list. Utilise it.
Acked-by: Mathias Nyman
Signed-off-by: Andy Shevchenko
---
v5: used renamed API (LKP)
v4: added tag (Mathias)
v3: no change
v2: no change
drivers/usb/host/xhci-ring.c | 7 ++-
1 file
Thank you both for the instructive feedback! :-)
--
Gustavo Sousa
Hi Maarten
On Wed, Nov 30, 2022 at 02:16:05PM +0100, Maarten Lankhorst wrote:
> A single fix to vmwgfx mks-guest-stats ioctl.
> I lost my internet connection when pushing the tag, so I put together this
> mail
> manually. I hope you remember where drm-misc is hosted. :)
For reference, you can
On Thu, Nov 24, 2022 at 01:27:40PM -0300, Gustavo Sousa wrote:
> Just a quick note: firmware PR hasn't been applied yet. Waiting...
Firmware PR merged into linux-firmware!
--
Gustavo Sousa
On Wed, 2022-11-30 at 11:47 +, Tvrtko Ursulin wrote:
>
> On 30/11/2022 02:29, Rodrigo Vivi wrote:
> > RC6 is a sleep state that doesn't depend on the cpu sleep,
> > or any of the APM or ACPI or anything related to the
> > CONFIG_PM.
> >
> > A long time ago we have removed the module
Hey Daniel and Dave,
A single fix to vmwgfx mks-guest-stats ioctl.
I lost my internet connection when pushing the tag, so I put together this mail
manually. I hope you remember where drm-misc is hosted. :)
Enjoy!
Maarten Lankhorst
drm-misc-fixes-2022-11-30:
drm-misc-fixes for v6.1-rc8/final:
-
On 29/11/2022 18:05, Matthew Auld wrote:
On Fri, 25 Nov 2022 at 11:14, Tvrtko Ursulin
wrote:
+ Matt
On 25/11/2022 10:21, Christian König wrote:
TTM is just wrapping core DMA functionality here, remove the mid-layer.
No functional change.
Signed-off-by: Christian König
---
On Wed, Nov 23, 2022 at 9:03 AM Gustavo Sousa wrote:
>
> The following changes since commit 391fb47caabaae8719fb72ba4891d1fc27ca1923:
>
> amdgpu: update green sardine DMCUB firmware (2022-11-17 10:42:59 -0500)
>
> are available in the Git repository at:
>
>
== Series Details ==
Series: drm/i915: Remove CONFIG_PM dependency from RC6.
URL : https://patchwork.freedesktop.org/series/111465/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12449_full -> Patchwork_111465v1_full
On 30/11/2022 02:29, Rodrigo Vivi wrote:
RC6 is a sleep state that doesn't depend on the cpu sleep,
or any of the APM or ACPI or anything related to the
CONFIG_PM.
A long time ago we have removed the module parameter
that allows the RC6 disablement. We want that feature enabled
everywhere.
== Series Details ==
Series: series starting with [v6,1/1] drm/i915/pxp: Promote pxp subsystem to
top-level of i915
URL : https://patchwork.freedesktop.org/series/111463/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12449_full -> Patchwork_111463v1_full
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Thursday, November 10, 2022 4:54 PM
> To: Sharma, Swati2 ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsc: Refactor dsc gen checks
>
> On Thu, 10 Nov 2022, Swati Sharma wrote:
== Series Details ==
Series: Add new CDCLK step for RPL-U
URL : https://patchwork.freedesktop.org/series/111472/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
CC [M] drivers/gpu/drm/i915/display/intel_cdclk.o
== Series Details ==
Series: More GuC firmware version improvements (rev3)
URL : https://patchwork.freedesktop.org/series/111218/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12449_full -> Patchwork_111218v3_full
Summary
On Wed, 30 Nov 2022, "Teres Alexis, Alan Previn"
wrote:
> ++Nikula if he has suggestions on the bottom most comment.
>
> On Tue, 2022-11-29 at 16:28 -0500, Vivi, Rodrigo wrote:
>> On Mon, Nov 28, 2022 at 04:31:52PM -0800, Alan Previn wrote:
>> > Starting with MTL, there will be two GT-tiles, a
On Wed, 30 Nov 2022, Chaitanya Kumar Borah
wrote:
> There are still RPL-U boards which does not support the 480Mhz step of
> CDCLK. We can differentiate these board by checking the CPUID Brand
> String. 480Mhz step is only supported in SKUs which does not contain
> the string "Genuine Intel" in
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