On Fri, 30 Dec 2022 12:55:08 +0100
Boris Brezillon wrote:
> On Fri, 30 Dec 2022 11:20:42 +0100
> Boris Brezillon wrote:
>
> > Hello Matthew,
> >
> > On Thu, 22 Dec 2022 14:21:11 -0800
> > Matthew Brost wrote:
> >
> > > In XE, the new Intel GPU driver, a choice has made to have a 1 to 1
> >
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Thursday, December 22, 2022 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ;
> ville.syrj...@linux.intel.com
> Subject: [PATCH] drm/i915/dsb: Remove check for dsb in dsb_commit
>
> The dsb context should be alr
Hello Jani,
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, November 30, 2022 2:08 PM
> To: Borah, Chaitanya Kumar ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville
> Subject: Re: [Intel-gfx] [RFC 2/2] drm/i915: Add additional check for 480Mhz
> step CDCLK
>
> On We
Hello Jani,
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, November 30, 2022 1:58 PM
> To: Borah, Chaitanya Kumar ; intel-
> g...@lists.freedesktop.org
> Cc: Syrjala, Ville
> Subject: Re: [Intel-gfx] [RFC 1/2] drm/i915: Add RPL-U CDCLK table
>
> On Wed, 30 Nov 2022, Chaitan
RPL-U boards with ES silicon does not support the 480Mhz step of
CDCLK. To differentiate between QS and ES part CPU brand string
is the only feasible way as of now. ES parts have "Genuine Intel"
in their brand string while QS parts have a more specific brand
string, for ex. "13th Gen Intel(R) Core(
With addition of new quirk QUIRK_480MHZ_CDCLK_STEP, it is imperative
that quirks should be initialized before CDCLK initialization. Refactor
the code accordingly.
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_display.c | 2 --
drivers/gpu/drm/i915/i915_driver.c
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c
A new CDCLK step of 480MHz has been added on SKUs that has a
RPL-U device id. This is done to support 120Hz displays with
more efficiency.
RPL-U device ids are currently added within the RPL-P sub
platform. It seems to be an overkill to add a separate sub
platform just to support this change. Ther
A new step of 480MHz has been added on SKUs that have a RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
RPL-U device ids are currently added within the RPL-
== Series Details ==
Series: Enable HDCP2.x via GSC CS (rev5)
URL : https://patchwork.freedesktop.org/series/111876/
State : warning
== Summary ==
Error: dim checkpatch failed
9a07090d8197 drm/i915/gsc: Create GSC request submission mechanism
Traceback (most recent call last):
File "scripts/
It requires to move intel specific HDCP API structures to
i915_cp_fw_hdcp_interface.h from driver/misc/mei/hdcp/mei_hdcp.h
so that any content protection fw interfaces can use these
structures.
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
MTL uses GSC command streamer i.e gsc cs to send HDCP/PXP commands
to GSC f/w. It requires to keep hdcp display driver
agnostic to content protection f/w (ME/GSC fw) in the form of
i915_hdcp_fw_ops generic ops.
Adding HDCP GSC CS interface by leveraging the i915_hdcp_fw_ops generic
ops instead of
Add function that takes care of sending command to gsc cs. We start
of with allocation of memory for our command intel_hdcp_gsc_message that
contains gsc cs memory header as directed in specs followed by the
actual payload hdcp message that we want to send.
Spec states that we need to poll pending
Need to fill wired cmd in structures at a single place as they remain
same for both gsc and mei.
--v3
-remove inline function from header [Jani]
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_hdcp_interface.c |
HDCP and PXP will require a common function to allow it to
submit commands to the gsc cs. Also adding the gsc mtl header
that needs to be added on to the existing payloads of HDCP
and PXP.
--v4
-Seprate gsc load and heci cmd submission into different
functions in different files for better scalabi
As now we have more then one type of content protection
secrity firmware. Let change the i915_cp_fw_hdcp_interface.h
header naming convention to suit generic f/w type.
%s/MEI_/HDCP_
%s/mei_dev/hdcp_dev
As interface to CP FW can be either a non i915 component or
i915 intergral component, change str
From: Anshuman Gupta
Change the include/drm/i915_mei_hdcp_interface.h to
include/drm/i915_hdcp_interface.h
Cc: Tomas Winkler
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
Signed-off-by: Suraj Kandpal
Acked-by: Tomas Winkler
---
.../drm/i915/display/int
These patches enable HDCP2.x on machines MTL and above.
>From MTL onwards CSME is spilt into GSC and CSC and now
we use GSC CS instead of MEI to talk to firmware to start
HDCP authentication
--v2
-Fixing some checkpatch changes which I forgot before sending
out the series
--v3
-Drop cp and fw to
On Sun, Jan 01, 2023 at 08:48:13PM -0500, Demi Marie Obenour wrote:
> On Sun, Jan 01, 2023 at 08:17:52PM -0500, Demi Marie Obenour wrote:
> > On Mon, Jan 02, 2023 at 02:00:51AM +0100, Marek Marczykowski-Górecki wrote:
> > > On Sun, Jan 01, 2023 at 07:03:18PM -0500, Demi Marie Obenour wrote:
> > > >
On Sun, Jan 01, 2023 at 07:03:18PM -0500, Demi Marie Obenour wrote:
> On Mon, Jan 02, 2023 at 12:24:54AM +0100, Marek Marczykowski-Górecki wrote:
> > On Thu, Dec 22, 2022 at 10:29:57AM +0200, Ville Syrjälä wrote:
> > > On Fri, Dec 16, 2022 at 03:30:13PM +, Andrew Cooper wrote:
> > > > On 08/12/
On Thu, Dec 22, 2022 at 10:29:57AM +0200, Ville Syrjälä wrote:
> On Fri, Dec 16, 2022 at 03:30:13PM +, Andrew Cooper wrote:
> > On 08/12/2022 1:55 pm, Marek Marczykowski-Górecki wrote:
> > > Hi,
> > >
> > > There is an issue with i915 on Xen PV (dom0). The end result is a lot of
> > > glitches,
On 12/29/2022 4:51 PM, Andrzej Hajda wrote:
On 22.12.2022 07:34, Ankit Nautiyal wrote:
The dsb context should be already checked for NULL, before dsb_commit
gets
called. So remove the check for dsb inside dsb_commit.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dsb
On Fri, Dec 30, 2022 at 04:59:38AM -0500, Rodrigo Vivi wrote:
> Hi Dave and Daniel,
>
> Here goes the initial fixes for 6.2.
>
> The most critical ones seems to be the evict fix from Matt and
> the MIPI DSI from Jani. Both targeting stable trees.
>
> I'm sorry for sending this on a Friday and no
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