Re: [Intel-gfx] [PATCH] drm/i915/fbc: Avoid full proxy f_ops for FBC debug attributes

On Wed, Dec 28, 2022 at 06:18:12AM -0500, Rodrigo Vivi wrote: > On Tue, Dec 27, 2022 at 11:36:13PM +0530, Deepak R Varma wrote: > > On Tue, Dec 27, 2022 at 12:13:56PM -0500, Rodrigo Vivi wrote: > > > On Tue, Dec 27, 2022 at 01:30:53PM +0530, Deepak R Varma wrote: > > > > Using DEFINE_SIMPLE_ATTRIBU

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

== Series Details == Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled URL : https://patchwork.freedesktop.org/series/112355/ State : success == Summary == CI Bug Log - changes from CI_DRM_12537_full -> Patchwork_112355v1_full ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

== Series Details == Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled URL : https://patchwork.freedesktop.org/series/112355/ State : success == Summary == CI Bug Log - changes from CI_DRM_12537 -> Patchwork_112355v1 =

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

== Series Details == Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled URL : https://patchwork.freedesktop.org/series/112355/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

== Series Details == Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled URL : https://patchwork.freedesktop.org/series/112355/ State : warning == Summary == Error: dim checkpatch failed af0cece2d473 drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabl

[Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

Make sure that PIPEDMCs are enabled whenever the corresponding pipe is enabled. This is required at least by the latest ADLP v2.18 firmware, which adds a new handler enabled by default and running whenever the pipe is enabled at the vertical referesh rate. Bspec: 50344, 67620 Signed-off-by: Imre

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix timeslots argument for DP DSC SST case

== Series Details == Series: drm/i915: Fix timeslots argument for DP DSC SST case URL : https://patchwork.freedesktop.org/series/112349/ State : success == Summary == CI Bug Log - changes from CI_DRM_12536_full -> Patchwork_112349v1_full Su

Re: [Intel-gfx] [PATCH] drm/i915: Use "%zu" to format size_t

On Fri, Dec 30, 2022 at 07:35:00PM +0100, Nirmoy Das wrote: > Switch to %zu for printing size_t which will > fix compilation warning for 32-bit build. > > Reported-by: kernel test robot > Signed-off-by: Nirmoy Das Reviewed-by: Andi Shyti Andi > --- > drivers/gpu/drm/i915/gem/i915_gem_shmem.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix timeslots argument for DP DSC SST case

== Series Details == Series: drm/i915: Fix timeslots argument for DP DSC SST case URL : https://patchwork.freedesktop.org/series/112349/ State : success == Summary == CI Bug Log - changes from CI_DRM_12536 -> Patchwork_112349v1 Summary

Re: [Intel-gfx] [PATCH v2] drm/i915: dell wyse 3040 shutdown fix

On Tue, 27 Dec 2022 20:40:03 +0300 Alexey Lukyachuk wrote: > On Tue, 27 Dec 2022 11:39:25 -0500 > Rodrigo Vivi wrote: > > > On Sun, Dec 25, 2022 at 09:55:08PM +0300, Alexey Lukyanchuk wrote: > > > dell wyse 3040 doesn't peform poweroff properly, but instead remains in > > > turned power on sta

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement workaround for DP2 UHBR bandwidth check

== Series Details == Series: drm/i915: Implement workaround for DP2 UHBR bandwidth check URL : https://patchwork.freedesktop.org/series/112345/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12536 -> Patchwork_112345v1 Summa

[Intel-gfx] [PATCH] drm/i915: Fix timeslots argument for DP DSC SST case

We now accept timeslots param exactly how the variable sounds: amount of timeslots, but not ratio timeslots/64. So for SST case(when we have all timeslots for use), it should be 64, but not 1. This caused some issues in the tests. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/displ

Re: [Intel-gfx] [PATCH] drm/i915: Use "%zu" to format size_t

Nirmoy, thanks for fixing it Reviewed-by: Gwan-gyeong Mun On 12/30/22 8:35 PM, Nirmoy Das wrote: Switch to %zu for printing size_t which will fix compilation warning for 32-bit build. Reported-by: kernel test robot Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/gem/i915_gem_shmem.c |

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in dsb_commit

Thanks Sai, will submit for re-run. From: Yedireswarapu, SaiX Nandan Sent: Monday, January 2, 2023 5:09 PM To: Nautiyal, Ankit K ; intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Cc: Veesam, RavitejaX ; Latvala, Petri Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check f

Re: [Intel-gfx] [RFC PATCH 00/20] Initial Xe driver submission

On Mon, 02 Jan 2023, Thomas Zimmermann wrote: > Hi > > Am 22.12.22 um 23:21 schrieb Matthew Brost: >> Hello, >> >> This is a submission for Xe, a new driver for Intel GPUs that supports both >> integrated and discrete platforms starting with Tiger Lake (first platform >> with >> Intel Xe Archite

[Intel-gfx] [PATCH] drm/i915: Implement workaround for DP2 UHBR bandwidth check

According to spec, we should check if output_bpp * pixel_rate is less than DDI clock * 72, if UHBR is used. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/d

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in dsb_commit

Hi, Series is too old, the results have already been deleted. Need a full re-run of this series. https://patchwork.freedesktop.org/series/112159/ Please provide the new patchwork series revision if issue is still observed. Thanks, Y Sai Nandan From: Yedireswarapu, SaiX Nandan Sent: Monday, Ja

Re: [Intel-gfx] [RFC 1/4] drm/i915/quirks: Add quirk for 480MHz CDCLK step

On Mon, 02 Jan 2023, Jani Nikula wrote: > On Mon, 02 Jan 2023, Chaitanya Kumar Borah > wrote: >> A new CDCLK step of 480MHz has been added on SKUs that has a >> RPL-U device id. This is done to support 120Hz displays with >> more efficiency. >> >> RPL-U device ids are currently added within the

Re: [Intel-gfx] [PATCH v7 0/2] drm/i915/mtl: handle some MTL scaler limitations

On Fri, 2022-12-23 at 15:05 +0200, Luca Coelho wrote: > Hi, > > Here's an updated version of the patches after Ville's last comments. > The versioning history is in the patches themselves. > > Please review. > > Cheers, > Luca. > > > Animesh Manna (1): > drm/i915/mtl: update scaler source an

Re: [Intel-gfx] [RFC 3/4] drm/i915: Initialize intel quirks before CDCLK initialization

On Mon, 02 Jan 2023, Chaitanya Kumar Borah wrote: > With addition of new quirk QUIRK_480MHZ_CDCLK_STEP, it is imperative > that quirks should be initialized before CDCLK initialization. Refactor > the code accordingly. Any refactors here should improve the clarity between display and the rest; t

Re: [Intel-gfx] [RFC 2/4] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U

On Mon, 02 Jan 2023, Chaitanya Kumar Borah wrote: > A new step of 480MHz has been added on SKUs that have a RPL-U > device id to support 120Hz displays more efficiently. Use a > new quirk to identify the machine for which this change needs > to be applied. Again, it's not a quirk, and should not

Re: [Intel-gfx] [RFC 1/4] drm/i915/quirks: Add quirk for 480MHz CDCLK step

On Mon, 02 Jan 2023, Chaitanya Kumar Borah wrote: > A new CDCLK step of 480MHz has been added on SKUs that has a > RPL-U device id. This is done to support 120Hz displays with > more efficiency. > > RPL-U device ids are currently added within the RPL-P sub > platform. It seems to be an overkill t

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add new CDCLK step for RPL-U (rev2)

== Series Details == Series: Add new CDCLK step for RPL-U (rev2) URL : https://patchwork.freedesktop.org/series/111472/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12534 -> Patchwork_111472v2 Summary --- **FAILURE*

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable HDCP2.x via GSC CS (rev5)

== Series Details == Series: Enable HDCP2.x via GSC CS (rev5) URL : https://patchwork.freedesktop.org/series/111876/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12534 -> Patchwork_111876v5 Summary --- **FAILURE**

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in dsb_commit

Hi Ankit, Can you please provide the patchwork series link (If there needed any re-reporting). Thanks, Y Sai Nandan From: Nautiyal, Ankit K Sent: Monday, January 2, 2023 2:17 PM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana ; Yedireswarapu, SaiX Nandan Subject: Re: ✗ Fi.CI.

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in dsb_commit

Hi Lakshmi/Sai The following issues are known issues, not related to the patch: * igt@i915_selftest@live@execlists: https://gitlab.freedesktop.org/drm/intel/-/issues/2940 fi-bsw-n3050: PASS

Re: [Intel-gfx] [PATCH v2] arch: rename all internal names __xchg to __arch_xchg

On Thu, Dec 29, 2022 at 12:34 PM Andrzej Hajda wrote: > __xchg will be used for non-atomic xchg macro. > > Signed-off-by: Andrzej Hajda > Reviewed-by: Arnd Bergmann Acked-by: Geert Uytterhoeven [m68k] Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of

Re: [Intel-gfx] [RFC PATCH 00/20] Initial Xe driver submission

Hi Am 22.12.22 um 23:21 schrieb Matthew Brost: Hello, This is a submission for Xe, a new driver for Intel GPUs that supports both integrated and discrete platforms starting with Tiger Lake (first platform with Intel Xe Architecture). The intention of this new driver is to have a fresh base to w