== Series Details ==
Series: drm/i915: Set wedged if enable guc communication failed
URL : https://patchwork.freedesktop.org/series/114366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12778_full -> Patchwork_114366v1_full
== Series Details ==
Series: drm/i915/mtl: Add engine TLB invalidation (rev2)
URL : https://patchwork.freedesktop.org/series/114159/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12774_full -> Patchwork_114159v2_full
Summar
On 2023-02-13 at 15:34:45 +0100, Janusz Krzysztofik wrote:
> If any of *-without-i915 subtests fails or skips for any reason, it may
> leave the i915 module unloaded while keeping our device list populated
> with initially collected data. In a follow up igt_fixture section we then
> try to reopen
On Friday, 24 February 2023 09:38:54 CET Kamil Konieczny wrote:
> On 2023-02-13 at 15:34:45 +0100, Janusz Krzysztofik wrote:
> > If any of *-without-i915 subtests fails or skips for any reason, it may
> > leave the i915 module unloaded while keeping our device list populated
> > with initially coll
On 23/02/2023 18:41, Badal Nilawar wrote:
Apply Wa_14017073508 for MTL SoC die A step instead of graphics step.
To get the SoC die stepping there is no direct interface so using
revid as revid 0 aligns with SoC die A step.
Bspec: 55420
Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 fo
On Tue, Feb 21, 2023 at 10:53:04AM +0200, Jouni Högander wrote:
> Currently we are using hardcoded 7 for io and fast wake lines.
>
> According to Bspec io and fast wake times are both 42us for
> DISPLAY_VER >= 12 and 50us and 32us for older platforms.
>
> Calculate line counts for these and confi
This series (or at least the suballocator helper) is a prerequisite
for the new Xe driver.
There was an unresolved issue when the series was last up for review,
and that was the per allocation aligment. Last message was from
Maarten Lankhorst arguing that the larger per-driver alignment used
would
From: Maarten Lankhorst
Suballocating a buffer object is something that is not driver-specific
and useful for many drivers.
Use a slightly modified version of amdgpu_sa.c
v2:
- Style cleanups.
- Added / Modified documentation.
- Use u64 for the sizes and offset. The code dates back to 2012 and
From: Maarten Lankhorst
Now that we have a generic suballocation helper, Use it in amdgpu.
For lines that get moved or changed, also fix up pre-existing style issues.
Signed-off-by: Maarten Lankhorst
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
Reviewed-by: Christian Köni
From: Maarten Lankhorst
Use the generic suballocation helper for radeon.
v3:
- Select the suballoc helper in Kconfig (Thomas).
Signed-off-by: Maarten Lankhorst
Co-developed-by: Thomas Hellström
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König
---
drivers/gpu/drm/radeon/Kconfig
PHY programming support for PICA C10 and C20 Type-C chips.
v2: Move intel_cx0_reg_defs.h to intel_cx0_phy_regs.h (Jani)
Move pmdemand as part of intel_display structure
PLL table updates
v3: Renaming C20 read/write functions (Gustavo)
Code readibility fixes (Gustavo)
HDMI PLL table
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/int
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers/
From: Radhakrishna Sripada
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the
From: Radhakrishna Sripada
Like DG2, we still don't have a proper algorithm that can be used
for calculating PHY settings, but we do have tables of register
values for a handful of the more common link rates. Some support is
better than none, so let's go ahead and add/use these tables when we
can
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
v2: Rename intel_c20_write() to intel_c20_sram_write() (Gustavo)
Remove unnecessary bit masks (Gustavo)
Fix comments on C20 pl
From: Radhakrishna Sripada
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
and preemphasis 1 instead of two times of le
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to us
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3 files c
Calculate port clock with C20 phy.
v2: Initialize parameters
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 64 +++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 65 inse
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
v2: Update rbr, hbr1, hbr2, and hbr3 pll configurations 4 and 5
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
v2: DP2.0 Tx Eq tables has been updated in BSpec.
Update also the driver code as per BSpec 65449
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
.../gpu/drm/i915/d
Enabling and disabling sequence for Thunderbolt PLL.
v2: Use __intel_de_wait_for_register() instead of
__intel_wait_for_register() (Jani)
Use '0' instead of ~XELPDP_TBT_CLOCK_ACK (Gustavo)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 136
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions(-)
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_c
PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
from PICA chip to south display engine and from there to north display
engine. This patch adds functionality to enable hotplug detection for
all Type-C ports (4 ports available).
Differently from HPD in south display, PICA
Add register writes to enable powering up Type-C subsystem i.e. TCSS.
For MeteorLake we need to request TCSS to power up and check the TCSS
power state after 500 us.
In addition, for PICA we need to set/clear the Type-C PHY ownnership
bit when Type-C device is connected/disconnected.
v2: Call tcs
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4 insertions
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by:
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers/gpu
== Series Details ==
Series: drm/helpers: Make the suballocation manager drm generic (rev2)
URL : https://patchwork.freedesktop.org/series/114299/
State : warning
== Summary ==
Error: dim checkpatch failed
9a396adf2225 drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper
Traceback
On Fri, 2023-02-24 at 11:32 +0200, Lisovskiy, Stanislav wrote:
> On Tue, Feb 21, 2023 at 10:53:04AM +0200, Jouni Högander wrote:
> > Currently we are using hardcoded 7 for io and fast wake lines.
> >
> > According to Bspec io and fast wake times are both 42us for
> > DISPLAY_VER >= 12 and 50us and
== Series Details ==
Series: drm/helpers: Make the suballocation manager drm generic (rev2)
URL : https://patchwork.freedesktop.org/series/114299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12774 -> Patchwork_114299v2
Su
On 2/23/2023 10:50 PM, Ville Syrjälä wrote:
On Tue, Feb 21, 2023 at 02:06:06PM +0530, Nautiyal, Ankit K wrote:
On 2/21/2023 1:07 AM, Ville Syrjälä wrote:
On Mon, Feb 20, 2023 at 05:53:48PM +0530, Ankit Nautiyal wrote:
The decision to use DFP output format conversion capabilities should be
du
Am 21.02.23 um 09:53 schrieb Jouni Högander:
Currently we are using hardcoded 7 for io and fast wake lines.
According to Bspec io and fast wake times are both 42us for
DISPLAY_VER >= 12 and 50us and 32us for older platforms.
Calculate line counts for these and configure them into PSR2_CTL
acc
On Fri, 10 Feb 2023 at 14:06, Andi Shyti wrote:
>
> Currently, for operations like memory clear or copy for big
> chunks of memory, we generate multiple requests executed in a
> chain.
>
> But if one of the requests generated fails we would not know it
> to unless it happens to the last request, b
Hi Matt,
On Tue, Dec 20, 2022 at 11:27:36AM +, Matthew Auld wrote:
> This was mostly needed to differentiate between mappable and
> non-mappable lmem, such that ttm would understand non-mappable ->
> mappable moves (or vice versa), and not just turn them into noops. We
> have since gained prop
> > On Thu, 23 Feb 2023, "Shankar, Uma" wrote:
> > >> -Original Message-
> > >> From: Nautiyal, Ankit K
> > >> Sent: Thursday, February 23, 2023 10:06 AM
> > >> To: intel-gfx@lists.freedesktop.org
> > >> Cc: Roper, Matthew D ; Shankar, Uma
> > >> ; Sharma, Swati2
> > >> Subject: [PATCH
look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 23.2.2023 20.39, Jonathan Cavitt wrote:
Refactor the supports_x_tiling and fast_blit_ok helper
functions in the live client selftest to better reflect
when XY_FAST_COPY_BLT supports X-tile and can be used.
Signed-off-by: Jonathan Cavitt
---
== Series Details ==
Series: drm/helpers: Make the suballocation manager drm generic (rev2)
URL : https://patchwork.freedesktop.org/series/114299/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12774_full -> Patchwork_114299v2_full
==
On Fri, 24 Feb 2023, Badal Nilawar wrote:
> Apply Wa_14017073508 for MTL SoC die A step instead of graphics step.
> To get the SoC die stepping there is no direct interface so using
> revid as revid 0 aligns with SoC die A step.
>
> Bspec: 55420
>
> Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support (rev6)
URL : https://patchwork.freedesktop.org/series/109714/
State : warning
== Summary ==
Error: dim checkpatch failed
c3e73104d4c0 drm/i915/mtl: Initial DDI port setup
361905cc8fa2 drm/i915/mtl: Add DP rates
3ba7e64de82a
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support (rev6)
URL : https://patchwork.freedesktop.org/series/109714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12775 -> Patchwork_109714v6
Summary
---
On Fri, Feb 24, 2023 at 03:43:37AM +, Liu, Yi L wrote:
> > From: Tian, Kevin
> > Sent: Friday, February 24, 2023 10:48 AM
> >
> > > From: Jason Gunthorpe
> > > Sent: Friday, February 24, 2023 10:36 AM
> > >
> > > On Fri, Feb 24, 2023 at 02:21:33AM +, Tian, Kevin wrote:
> > >
> > > > Yi, w
On Fri, Feb 24, 2023 at 12:58:22PM +0800, Yan Zhao wrote:
> On Wed, Feb 22, 2023 at 08:59:51AM -0400, Jason Gunthorpe wrote:
> > On Wed, Feb 22, 2023 at 07:44:12AM +, Liu, Yi L wrote:
> > > > From: Tian, Kevin
> > > > Sent: Wednesday, February 22, 2023 3:40 PM
> > > >
> > > > > From: Liu, Yi
These are left overs from the conversion towards intel_de_rmw.
Fixes: aa80b2b12b89 ("drm/i915/display/panel: use intel_de_rmw if possible in
panel related code")
Cc: Andrzej Hajda
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_backlight.c | 11 ---
1 file changed, 4
On 22/02/2023 15:56, Matthew Auld wrote:
On 22/02/2023 15:26, Jonathan Cavitt wrote:
MTL currently uses gen8_ppgtt_insert_huge when managing huge pages.
This is because
MTL reports as not supporting 64K pages, or more accurately, the
system that reports
whether a platform has 64K pages reports
On Thu, Feb 23, 2023 at 10:08:51AM +0100, Andrzej Hajda wrote:
> On 17.02.2023 19:54, Matt Roper wrote:
> > MTL's primary GT can continue to use the same engine TLB invalidation
> > programming as past Xe_HP-based platforms. However the media GT needs
> > some special handling:
> > * Invalidatio
On Thu, Feb 23, 2023 at 03:20:28PM -0500, Rodrigo Vivi wrote:
> On Fri, Feb 24, 2023 at 12:11:40AM +0530, Badal Nilawar wrote:
> > Apply Wa_14017073508 for MTL SoC die A step instead of graphics step.
> > To get the SoC die stepping there is no direct interface so using
> > revid as revid 0 aligns
On Thu, Feb 23, 2023 at 10:39:54AM -0800, Jonathan Cavitt wrote:
> Refactor the supports_x_tiling and fast_blit_ok helper
> functions in the live client selftest to better reflect
> when XY_FAST_COPY_BLT supports X-tile and can be used.
>
> Signed-off-by: Jonathan Cavitt
Bspec: 47982
Reviewed-by
-Original Message-
From: Auld, Matthew
Sent: Friday, February 24, 2023 7:51 AM
To: Cavitt, Jonathan ;
intel-gfx@lists.freedesktop.org
Cc: Dutt, Sudeep ; thomas.hellst...@linux.intel.com;
maarten.lankho...@linux.intel.com; Vetter, Daniel ; De
Marchi, Lucas ; chris.p.wil...@linux.intel.c
On Fri, Feb 24, 2023 at 05:03:05AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/mtl: X-Tile support changes to client blits
> URL : https://patchwork.freedesktop.org/series/114309/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12774_full -> Pat
On Fri, Feb 24, 2023 at 10:37:07AM -0500, Rodrigo Vivi wrote:
> These are left overs from the conversion towards intel_de_rmw.
>
> Fixes: aa80b2b12b89 ("drm/i915/display/panel: use intel_de_rmw if possible in
> panel related code")
> Cc: Andrzej Hajda
> Signed-off-by: Rodrigo Vivi
Reviewed-by:
On 24.02.2023 16:37, Rodrigo Vivi wrote:
These are left overs from the conversion towards intel_de_rmw.
Fixes: aa80b2b12b89 ("drm/i915/display/panel: use intel_de_rmw if possible in panel
related code")
Cc: Andrzej Hajda
Signed-off-by: Rodrigo Vivi
Reviewed-by: Andrzej Hajda
Regards
And
26 files changed, 536 insertions(+), 299 deletions(-)
---
base-commit: 1ddc2e762c6a109af52f3c39534c7115aebe
change-id: 20230224-track_gt-1b3da8bdacd7
Best regards,
--
Andrzej Hajda
From: Chris Wilson
Extract the callstack tracking of intel_runtime_pm.c into its own
utility so that that we can reuse it for other online debugging of
scoped wakerefs.
Signed-off-by: Chris Wilson
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/Kconfig.debug | 9 +
drivers/g
From: Chris Wilson
Track every intel_gt_pm_get() until its corresponding release in
intel_gt_pm_put() by returning a cookie to the caller for acquire that
must be passed by on released. When there is an imbalance, we can see who
either tried to free a stale wakeref, or who forgot to free theirs.
Wakeref has dedicated type. Assumption it will be int
compatible forever is incorrect.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drive
== Series Details ==
Series: drm/i915: Remove unused tmp assignment.
URL : https://patchwork.freedesktop.org/series/114336/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12775 -> Patchwork_114336v1
Summary
---
**SUCC
On 20.12.2022 12:27, Matthew Auld wrote:
This was mostly needed to differentiate between mappable and
non-mappable lmem, such that ttm would understand non-mappable ->
mappable moves (or vice versa), and not just turn them into noops. We
have since gained proper .intersects() and .compatible() ho
Some PCI IDs got accidentally removed when subplatform was added.
Fixes: 61b795a9c352 ("drm/i915: Add RPL-U sub platform")
Cc: Chaitanya Kumar Borah
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/d
On 24/02/2023 16:13, Cavitt, Jonathan wrote:
-Original Message-
From: Auld, Matthew
Sent: Friday, February 24, 2023 7:51 AM
To: Cavitt, Jonathan ;
intel-gfx@lists.freedesktop.org
Cc: Dutt, Sudeep ; thomas.hellst...@linux.intel.com;
maarten.lankho...@linux.intel.com; Vetter, Daniel ; De
On Wed, Feb 22, 2023 at 01:52:23PM -0800, Dixit, Ashutosh wrote:
On Thu, 16 Feb 2023 16:58:45 -0800, Umesh Nerlige Ramappa wrote:
Hi Umesh,
Now that we may have multiple OA units in a single GT as well as on
separate GTs, create an engine group that maps to a single OA unit.
v2: (Jani)
- D
MTL currently uses gen8_ppgtt_insert_huge when managing huge pages. This is
because
MTL reports as not supporting 64K pages, or more accurately, the system that
reports
whether a platform has 64K pages reports false for MTL. This is only half
correct,
as the 64K page support reporting system o
== Series Details ==
Series: drm/i915: track gt->wakerefs
URL : https://patchwork.freedesktop.org/series/114338/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 4d6d7ce9baaf9e67a85a53afc69a36af716f7670 Add linux-next specific
files for 20230224
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202302111601.jty4lkra-...@intel.com
https
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support (rev6)
URL : https://patchwork.freedesktop.org/series/109714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12775_full -> Patchwork_109714v6_full
Summar
== Series Details ==
Series: drm/i915: track gt->wakerefs
URL : https://patchwork.freedesktop.org/series/114338/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12776 -> Patchwork_114338v1
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915/adlp: Restoring ADL-P/RPL-U IDs.
URL : https://patchwork.freedesktop.org/series/114340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12776 -> Patchwork_114340v1
Summary
---
**SU
== Series Details ==
Series: drm/i915: Use correct huge page manager for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/114259/
State : warning
== Summary ==
Error: dim checkpatch failed
e3e53cca9170 drm/i915: Use correct huge page manager for MTL
-:6: WARNING:COMMIT_LOG_LONG_LINE:
On Tue, Feb 21, 2023 at 10:51:57AM -0800, Dixit, Ashutosh wrote:
On Fri, 17 Feb 2023 17:57:02 -0800, Dixit, Ashutosh wrote:
On Fri, 17 Feb 2023 16:05:50 -0800, Umesh Nerlige Ramappa wrote:
> On Fri, Feb 17, 2023 at 12:58:18PM -0800, Dixit, Ashutosh wrote:
> > On Thu, 16 Feb 2023 16:58:48 -0800,
== Series Details ==
Series: drm/i915: Use correct huge page manager for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/114259/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12776 -> Patchwork_114259v2
Summary
--
On Tue, Feb 21, 2023 at 03:53:57PM -0800, Dixit, Ashutosh wrote:
On Thu, 16 Feb 2023 16:58:49 -0800, Umesh Nerlige Ramappa wrote:
Hi Umesh,
Patch is mostly ok but a few questions below:
Current implementation of perf defaults to render and configures the
default OAG unit. Since there are m
== Series Details ==
Series: drm/i915: Remove unused tmp assignment.
URL : https://patchwork.freedesktop.org/series/114336/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12775_full -> Patchwork_114336v1_full
Summary
---
From: Rob Clark
This series adds a deadline hint to fences, so realtime deadlines
such as vblank can be communicated to the fence signaller for power/
frequency management decisions.
This is partially inspired by a trick i915 does, but implemented
via dma-fence for a couple of reasons:
1) To c
From: Rob Clark
v2: rebase
Signed-off-by: Rob Clark
---
drivers/gpu/drm/i915/i915_request.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 7503dcb9043b..44491e7e214c 100644
--- a/drivers
On Fri, 24 Feb 2023 11:37:01 -0800, Umesh Nerlige Ramappa wrote:
>
> On Tue, Feb 21, 2023 at 03:53:57PM -0800, Dixit, Ashutosh wrote:
> > On Thu, 16 Feb 2023 16:58:49 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >
> > Hi Umesh,
> >
> > Patch is mostly ok but a few questions below:
> >
> >> Current im
Define MCR_REG() in the same header where i915_mcr_reg_t is defined,
like i915_reg_t and _MMIO(). It's a more natural place for such a
definition so it's not mixed with the registers for the platforms.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 --
drivers/gpu
On Fri, Feb 24, 2023 at 01:12:21PM -0800, Lucas De Marchi wrote:
> Define MCR_REG() in the same header where i915_mcr_reg_t is defined,
> like i915_reg_t and _MMIO(). It's a more natural place for such a
> definition so it's not mixed with the registers for the platforms.
>
> Signed-off-by: Lucas
On Fri, Feb 24, 2023 at 08:27:52AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/mtl: Add engine TLB invalidation (rev2)
> URL : https://patchwork.freedesktop.org/series/114159/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12774_full -> Patchwo
== Series Details ==
Series: drm/i915: Move MCR_REG define to i915_reg_defs.h
URL : https://patchwork.freedesktop.org/series/114359/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12777 -> Patchwork_114359v1
Summary
---
== Series Details ==
Series: drm/i915: track gt->wakerefs
URL : https://patchwork.freedesktop.org/series/114338/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12776_full -> Patchwork_114338v1_full
Summary
---
**SUCCE
== Series Details ==
Series: drm/i915/adlp: Restoring ADL-P/RPL-U IDs.
URL : https://patchwork.freedesktop.org/series/114340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12776_full -> Patchwork_114340v1_full
Summary
-
Add err code check for enable_communication on resume path, set wedged if
failed.
Signed-off-by: Zhanjun Dong
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 5 -
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 +++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
== Series Details ==
Series: drm/i915: Use correct huge page manager for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/114259/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12776_full -> Patchwork_114259v2_full
On Fri, Feb 24, 2023 at 11:34:44AM -0500, Rodrigo Vivi wrote:
> Some PCI IDs got accidentally removed when subplatform was added.
I don't think they got removed? INTEL_RPLP_IDS still includes the
entire INTEL_RPLU_IDS list:
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
== Series Details ==
Series: drm/i915: Set wedged if enable guc communication failed
URL : https://patchwork.freedesktop.org/series/114366/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12778 -> Patchwork_114366v1
Summary
-
== Series Details ==
Series: drm/i915/sseu: fix max_subslices array-index-out-of-bounds access (rev2)
URL : https://patchwork.freedesktop.org/series/114199/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, Feb 23, 2023 at 12:05:02PM -0800, Dixit, Ashutosh wrote:
On Thu, 16 Feb 2023 16:58:50 -0800, Umesh Nerlige Ramappa wrote:
Hi Umesh,
MTL introduces additional OA units dedicated to media use cases. Add
support for programming these OA units by passing the media engine class
and insta
== Series Details ==
Series: drm/i915/sseu: fix max_subslices array-index-out-of-bounds access (rev2)
URL : https://patchwork.freedesktop.org/series/114199/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12778 -> Patchwork_114199v2
==
== Series Details ==
Series: drm/i915: Move MCR_REG define to i915_reg_defs.h
URL : https://patchwork.freedesktop.org/series/114359/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12777_full -> Patchwork_114359v1_full
Summar
On Fri, 24 Feb 2023 16:58:39 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> On Thu, Feb 23, 2023 at 12:05:02PM -0800, Dixit, Ashutosh wrote:
> > On Thu, 16 Feb 2023 16:58:50 -0800, Umesh Nerlige Ramappa wrote:
> >>
> >
> > Hi Umesh,
> >
> >> MTL introduces additional OA units dedicated to medi
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