== Series Details ==
Series: drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step (rev2)
URL : https://patchwork.freedesktop.org/series/114508/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12800 -> Patchwork_114508v2
Summ
> From: Liu, Yi L
> Sent: Monday, February 27, 2023 7:11 PM
[...]
> @@ -2392,13 +2416,25 @@ static int
> vfio_pci_dev_set_pm_runtime_get(struct vfio_device_set *dev_set)
> return ret;
> }
>
> +static bool vfio_dev_in_iommufd_ctx(struct vfio_pci_core_device *vdev,
> +
> From: Jason Gunthorpe
> Sent: Thursday, March 2, 2023 1:47 AM
>
> On Wed, Mar 01, 2023 at 09:19:07AM +, Liu, Yi L wrote:
> > > From: Liu, Yi L
> > > Sent: Monday, February 27, 2023 7:12 PM
> > [...]
> > > +long vfio_device_ioctl_bind_iommufd(struct vfio_device_file *df,
> > > +
> From: Jason Gunthorpe
> Sent: Thursday, March 2, 2023 1:49 AM
>
> On Wed, Mar 01, 2023 at 02:04:00PM +, Liu, Yi L wrote:
> > diff --git a/drivers/vfio/group.c b/drivers/vfio/group.c
> > index 2a13442add43..ed3ffe7ceb3f 100644
> > --- a/drivers/vfio/group.c
> > +++ b/drivers/vfio/group.c
> >
Hi Janusz,
On Sat, Feb 25, 2023 at 11:12:18PM +0100, Janusz Krzysztofik wrote:
> Users reported oopses on list corruptions when using i915 perf with a
> number of concurrently running graphics applications. Root cause analysis
> pointed at an issue in barrier processing code -- a race among perf
On Mon, 27 Feb 2023 18:23:24 -0800, Umesh Nerlige Ramappa wrote:
>
> @@ -3378,12 +3376,13 @@ void i915_oa_init_reg_state(const struct
> intel_context *ce,
> const struct intel_engine_cs *engine)
> {
> struct i915_perf_stream *stream;
> + struct i915_perf_group
On Wed, Mar 01, 2023 at 01:38:52AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/sseu: fix max_subslices array-index-out-of-bounds access
> (rev4)
> URL : https://patchwork.freedesktop.org/series/114199/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from C
== Series Details ==
Series: Misc Meteorlake patches (rev3)
URL : https://patchwork.freedesktop.org/series/112700/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_112700v3
Summary
---
**SUCCESS**
On Fri, Feb 17, 2023 at 09:51:37PM +0100, Daniel Vetter wrote:
> Hi all,
>
> [I thought I've sent this out earlier this week, but alas got stuck, kinda
> bad timing now since I'm out next week but oh well]
>
> So xe is a quite substantial thing, and I think we need a clear plan how to
> land
> t
== Series Details ==
Series: Misc Meteorlake patches (rev3)
URL : https://patchwork.freedesktop.org/series/112700/
State : warning
== Summary ==
Error: dim checkpatch failed
f2efa48f76b8 drm/i915/mtl: Fix Wa_16015201720 implementation
3d4b9acde185 drm/i915/gt: generate per tile debugfs files
3
Hi Mika,
> -Original Message-
> From: Kahola, Mika
> Sent: Friday, February 24, 2023 2:14 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Atwood, Matthew S
> ; Roper, Matthew D
> ; De Marchi, Lucas ;
> Sousa, Gustavo ; Souza, Jose
> ; Sripada, Radhakrishna
>
> Subject: [PAT
== Series Details ==
Series: drm/i915: vblank stuff (rev3)
URL : https://patchwork.freedesktop.org/series/112170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_112170v3
Summary
---
**SUCCESS**
N
> I am not sure if Tiles is appropriate usage here. Since MTL does not have the
> concept of tiles.
> Shouldn't we be using gt instead of tile in our usage?
>
> With s/tile/gt/g,
> Reviewed-by: Radhakrishna Sripada
yes, GT is preferred to tile, generally. Thanks for the review, I
will change t
== Series Details ==
Series: drm/i915/display: split out DSC and DSS registers
URL : https://patchwork.freedesktop.org/series/114523/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114523v1
Summary
---
On Mon, 27 Feb 2023 18:23:28 -0800, Umesh Nerlige Ramappa wrote:
>
Hi Umesh,
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 8df261c5ab9b..8ce20004a9dd 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2758,6 +2758,28 @@ enum drm
On 27.02.2023 12:50, Jani Nikula wrote:
On Fri, 24 Feb 2023, Andrzej Hajda wrote:
From: Chris Wilson
Extract the callstack tracking of intel_runtime_pm.c into its own
utility so that that we can reuse it for other online debugging of
scoped wakerefs.
Signed-off-by: Chris Wilson
Signed-off-b
I am not sure if Tiles is appropriate usage here. Since MTL does not have the
concept of tiles.
Shouldn't we be using gt instead of tile in our usage?
With s/tile/gt/g,
Reviewed-by: Radhakrishna Sripada
> -Original Message-
> From: dri-devel On Behalf Of Andi
> Shyti
> Sent: Wednesday
> -Original Message-
> From: dri-devel On Behalf Of Andi
> Shyti
> Sent: Wednesday, March 1, 2023 3:03 AM
> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Cc: Tvrtko Ursulin ; Andi Shyti
> ; Patelczyk, Maciej ; Andi
> Shyti ; Wajdeczko, Michal
>
> Subject: [PATCH
== Series Details ==
Series: drm/i915/dsi: fix DSS CTL register offsets for TGL+
URL : https://patchwork.freedesktop.org/series/114522/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114522v1
Summary
-
This patch can be ignored. As the original Author submitted the series here
https://patchwork.freedesktop.org/series/114510/
- Radhakrishna(RK) Sripada
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Wednesday, March 1, 2023 12:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc:
== Series Details ==
Series: drm/i915: pm cleanups, rename to clock gating
URL : https://patchwork.freedesktop.org/series/114519/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114519v1
Summary
---
== Series Details ==
Series: Add vfio_device cdev for iommufd support (rev6)
URL : https://patchwork.freedesktop.org/series/113696/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/113696/revisions/6/mbox/ not
applied
Applying: vfio: Allocate per de
== Series Details ==
Series: drm/i915: pm cleanups, rename to clock gating
URL : https://patchwork.freedesktop.org/series/114519/
State : warning
== Summary ==
Error: dim checkpatch failed
b692b7687640 drm/i915/wm: remove display/ prefix from include
3c139b502a1f drm/i915/pm: drop intel_pm_set
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/power: move dc state members to
struct i915_power_domains
URL : https://patchwork.freedesktop.org/series/114515/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114515v1
=
Irq reset and post install are to be made multi-gt aware for the
interrupts to work for the media tile on Meteorlake. Iterate through
all the gts to process irq reset for each gt.
Based on original version by Paulo and Tvrtko
Cc: Paulo Zanoni
Cc: Tvrtko Ursulin
Reviewed-by: Lucas De Marchi
Sig
From: Andi Shyti
In the view of multi-gt we want independent per gt debug files.
In debugfs create gt0/ gt1/ ... gtN/ for tile related files. In 4
tiles, the debugfs would be structured as follows:
/sys/kernel/debug/dri
└── 0
├── gt0
From: Tejas Upadhyay
lock the fbdev obj before calling into
i915_vma_pin_iomap(). This helps to solve below :
<7>[ 93.563308] i915 :00:02.0: [drm:intelfb_create [i915]] no BIOS fb,
allocating a new one
<4>[ 93.581844] [ cut here ]
<4>[ 93.581855] WARNING: CPU:
From: José Roberto de Souza
Latch reset of phys during DC9 and when driver is unloaded to avoid
phy reset.
Specification ask us to program it closer to the step that enables
DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
latch during driver load.
BSpec: 49197
Reviewed-by: Ma
This series adds misc MTL patches. This is a new rev of
earlier series with dropped CCS patches. Review feedback for other
patches included.
Andi Shyti (1):
drm/i915/gt: generate per tile debugfs files
José Roberto de Souza (1):
drm/i915/display/mtl: Program latch to phy reset
Radhakrishna
The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
extended the workaround Wa_16015201720 to MTL. However the registers
that the original WA implemented moved for MTL.
Implement the workaround with the correct register.
v3: Skip clock gating for pipe C, D DMC's and fix the titl
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/power: move dc state members to
struct i915_power_domains
URL : https://patchwork.freedesktop.org/series/114515/
State : warning
== Summary ==
Error: dim checkpatch failed
873ffa5c0eff drm/i915/power: move dc state members to
== Series Details ==
Series: drm/i915/active: Fix misuse of non-idle barriers as fence trackers
(rev6)
URL : https://patchwork.freedesktop.org/series/113950/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_113950v6
On Wed, Mar 01, 2023 at 03:42:51PM +0530, Badal Nilawar wrote:
> Apply Wa_14017073508 for MTL Media step instead of graphics step.
>
> v2: Use Media stepping instead of SoC die stepping (Matt)
>
> Bspec: 66623
>
> Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia")
> Signed-off-
== Series Details ==
Series: Some debugfs refactoring and improvements
URL : https://patchwork.freedesktop.org/series/114510/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114510v1
Summary
---
**SU
== Series Details ==
Series: Some debugfs refactoring and improvements
URL : https://patchwork.freedesktop.org/series/114510/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, Mar 01, 2023 at 02:04:00PM +, Liu, Yi L wrote:
> diff --git a/drivers/vfio/group.c b/drivers/vfio/group.c
> index 2a13442add43..ed3ffe7ceb3f 100644
> --- a/drivers/vfio/group.c
> +++ b/drivers/vfio/group.c
> @@ -777,6 +777,11 @@ void vfio_device_group_unregister(struct vfio_device
> *d
On Wed, Mar 01, 2023 at 09:19:07AM +, Liu, Yi L wrote:
> > From: Liu, Yi L
> > Sent: Monday, February 27, 2023 7:12 PM
> [...]
> > +long vfio_device_ioctl_bind_iommufd(struct vfio_device_file *df,
> > + unsigned long arg)
> > +{
> > + struct vfio_device *device
From: Ville Syrjälä
The pipe needs a certain amount of time during vblank to prefill
sufficiently. If the vblank is too short the relevant watermark
level must be disabled.
Start implementing the necessary calculations to check this.
Scaler and DSC prefill are left out for now as handling those
From: Ville Syrjälä
Extract the skl+ wm latency determination into a small helper
so that everyone has the same idea what the latency should be.
This introduces a slight functional change in that
skl_cursor_allocation() will now start to account for the
extra 4 usec that the kbk/cfl/cml IPC w/a
From: Ville Syrjälä
Remainder of the vblank length/start stuff, rebased to deal
with the watermark max_level vs. num_level changes.
Ville Syrjälä (2):
drm/i915: Extract skl_wm_latency()
drm/i915: Reject wm levels that exceed vblank time
drivers/gpu/drm/i915/display/skl_watermark.c | 155 ++
On Wed, Mar 01, 2023 at 05:38:39PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 01, 2023 at 05:14:09PM +0200, Jani Nikula wrote:
> > On TGL+ the DSS control registers are at different offsets, and there's
> > one per pipe. Fix the offsets to fix dual link DSI for TGL+.
> >
> > There would be helpers
On Wed, Mar 01, 2023 at 05:21:10PM +0200, Jani Nikula wrote:
> On Wed, 01 Mar 2023, "Hogander, Jouni" wrote:
> > On Mon, 2023-02-20 at 18:47 +0200, Ville Syrjala wrote:
> >> From: Ville Syrjälä
> >>
> >> Grab the HDR DPCD refresh timeout (time we need to wait after
> >> writing the sourc OUI bef
On Wed, Mar 01, 2023 at 05:14:09PM +0200, Jani Nikula wrote:
> On TGL+ the DSS control registers are at different offsets, and there's
> one per pipe. Fix the offsets to fix dual link DSI for TGL+.
>
> There would be helpers for this in the DSC code, but just do the quick
> fix now for DSI. Long t
On Wed, 01 Mar 2023, "Hogander, Jouni" wrote:
> On Mon, 2023-02-20 at 18:47 +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Grab the HDR DPCD refresh timeout (time we need to wait after
>> writing the sourc OUI before the HDR DPCD registers are ready)
>> from the VBT.
>>
>> Windows doe
Relatively few places need the DSC and DSS register definitions. Move
them to intel_vdsc_regs.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c| 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
dri
On TGL+ the DSS control registers are at different offsets, and there's
one per pipe. Fix the offsets to fix dual link DSI for TGL+.
There would be helpers for this in the DSC code, but just do the quick
fix now for DSI. Long term, we should probably move all the DSS handling
into intel_vdsc.c, so
On Wed, Mar 01, 2023 at 10:49:26AM +0200, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Remove the bogus csync check and replace it with something that:
> > - triggers for all forms of csync, not just the basic analog variant
> > - actually populat
On Mon, 2023-02-20 at 18:47 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Grab the HDR DPCD refresh timeout (time we need to wait after
> writing the sourc OUI before the HDR DPCD registers are ready)
> from the VBT.
>
> Windows doesn't even seem to have any default value for this,
> whi
> From: Jason Gunthorpe
> Sent: Tuesday, February 28, 2023 10:38 PM
>
> On Tue, Feb 28, 2023 at 02:01:36PM +, Liu, Yi L wrote:
> > > From: Jason Gunthorpe
> > > Sent: Tuesday, February 28, 2023 9:44 PM
> > >
> > > On Tue, Feb 28, 2023 at 01:36:24PM +, Liu, Yi L wrote:
> > > > > From: Jas
> From: Jason Gunthorpe
> Sent: Tuesday, February 28, 2023 8:36 PM
>
> On Tue, Feb 28, 2023 at 06:00:09AM +, Liu, Yi L wrote:
> > > From: Liu, Yi L
> > > Sent: Monday, February 27, 2023 7:12 PM
> > >
> > > group code is not needed for vfio device cdev, so with vfio device cdev
> > > introduc
> From: Jason Gunthorpe
> Sent: Tuesday, February 28, 2023 8:34 PM
>
> On Tue, Feb 28, 2023 at 03:11:34AM +, Liu, Yi L wrote:
> > > From: Jason Gunthorpe
> > > Sent: Tuesday, February 28, 2023 2:52 AM
> > >
> > > On Mon, Feb 27, 2023 at 03:11:30AM -0800, Yi Liu wrote:
> > > > @@ -535,7 +542,
Follow the contemporary naming style. Include some indentation fixes
while at it on the affected statements.
One function needs to keep using dev_priv due to implicit dev_priv usage
in a macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_clock_gating.c | 589 +++---
Observe that intel_pm.[ch] is now purely about clock gating, so rename
them to intel_clock_gating.[ch]. Rename the functions to
intel_clock_gating_*() to follow coding conventions.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/display
As intel_pm.[ch] used to contain much more, intel_pm.h was included in a
lot of places. Many of them are now unnecessary. Remove.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 1 -
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
drivers/gpu/drm
All intel_suspend_hw() does is clear PCH_LP_PARTITION_LEVEL_DISABLE bit
in SOUTH_DSPCLK_GATE_D for LPT LP. intel_suspend_hw() gets called from
i915_drm_suspend().
However, i915_drm_suspend_late() calls
intel_display_power_suspend_late(), which in turn calls hsw_enable_pc8()
on HSW and BDW. The fir
All the init in intel_pm_setup() is related to runtime pm. Move them to
intel_runtime_pm_init_early(), and remove intel_pm_setup().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_driver.c | 1 -
drivers/gpu/drm/i915/intel_pm.c | 6 --
drivers/gpu/drm/i915/intel_pm.h
Remove the leftover from moving and renaming the file from driver top
level.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_wm_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_wm_types.h
b/drivers/gpu/drm/i915/disp
Finish off some of the cleanups done earlier in intel_pm.[ch]
Jani Nikula (6):
drm/i915/wm: remove display/ prefix from include
drm/i915/pm: drop intel_pm_setup()
drm/i915/pm: drop intel_suspend_hw()
drm/i915: remove unnecessary intel_pm.h includes
drm/i915: rename intel_pm.[ch] to intel
Follow the contemporary convention for struct drm_i915_private * naming.
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 166 +++
1 file changed, 81 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
Start preparing for dynamically allocated struct intel_dmc by adding
i915_to_dmc() and dmc->i915, and using them. Take the future NULL dmc
pointer into account already now, and add separate logging for
initialization in the DMC debugfs.
v3:
- Obtain runtime pm reference first (Imre)
v2:
- Don't r
sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
part of struct drm_i915_private, whether they have DMC or not.
Allocate struct intel_dmc dynamically, and hide all the dmc details
behind an opaque pointer in intel_dmc.c.
Care must be taken to take into account all cases: DMC n
This will help in follow-up changes.
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index ab4fdedd4
There's only one reference to the struct intel_dmc members dc_state,
target_dc_state, and allowed_dc_mask within intel_dmc.c, begging the
question why they are under struct intel_dmc to begin with.
Moreover, the only references to i915->display.dmc outside of
intel_dmc.c are to these members.
The
Hi Tejas,
On Tue, Feb 28, 2023 at 10:13:07AM +0530, Tejas Upadhyay wrote:
> From: Tvrtko Ursulin
>
> After the abandonment of i915->kernel_context and since we have started to
> create per-gt engine->kernel_context, these tests need to be updated to
> instantiate the batch buffer VMA in the corr
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/power: move dc state members to
struct i915_power_domains (rev2)
URL : https://patchwork.freedesktop.org/series/114431/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12794_full -> Patchwork_114431v2_full
LGTM
Reviewed-by: Badal Nilawar
On 23-02-2023 15:35, Anshuman Gupta wrote:
While reading the engine timestamps there can be uncontrollable
concurrent mmio access via other i915 child drivers and by GuC,
which is not truly atomic context as expected by this selftest,
which may cause mmio latenc
LGTM
Reviewed-by: Badal Nilawar
On 23-02-2023 15:35, Anshuman Gupta wrote:
Use ktime_get() after accessing the mmio or any driver resource,
while using wall time for various calculation that depends on
the inserted delay in order to account any mmio and resource
access latency.
Cc: Chris Wils
== Series Details ==
Series: drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step
URL : https://patchwork.freedesktop.org/series/114508/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12795 -> Patchwork_114508v1
Summary
---
On 28-02-2023 10:13, Ashutosh Dixit wrote:
The value shown by power1_max_interval in millisec is essentially:
((1.x * power(2,y)) * 1000) >> 10
Where x and y are read from a HW register. On ATSM, x and y are 0 on
power-up so the value shown is 0.
Writes of 0 to power1_max_interval had
The commit 82a149a62b6b5 ('drm/i915/gt: move remaining debugfs
interfaces into gt') moved gt-related debugfs files in the gtX/
directories to operate on individual gt's.
However, the original files were only functioning on the root
tile (tile 0) and have been left in the same location to maintain
To support multi-GT configurations, we need to generate
independent debug files for each GT.
To achieve this create a separate directory for each GT under the
debugfs directory. For instance, in a system with two tiles, the
debugfs structure would look like this:
/sys/kernel/debug/dri
Hi,
These two patches aim to enhance the multi-GT capabilities of the
debugfs.
The first patch reorganizes the file structure, while the second
patch extends the functionality of the original files in the
upper directories to operate on all tiles with a single write,
providing an or'ed value amon
On Wed, 01 Mar 2023, Imre Deak wrote:
> On Mon, Feb 27, 2023 at 07:25:21PM +0200, Jani Nikula wrote:
>> sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
>> part of struct drm_i915_private, whether they have DMC or not.
>>
>> Allocate struct intel_dmc dynamically, and hide all
On Mon, Feb 27, 2023 at 07:25:21PM +0200, Jani Nikula wrote:
> sizeof(struct intel_dmc) > 1024 bytes, allocated on all platforms as
> part of struct drm_i915_private, whether they have DMC or not.
>
> Allocate struct intel_dmc dynamically, and hide all the dmc details
> behind an opaque pointer in
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/power: move dc state members to
struct i915_power_domains (rev2)
URL : https://patchwork.freedesktop.org/series/114431/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12794 -> Patchwork_114431v2
==
Apply Wa_14017073508 for MTL Media step instead of graphics step.
v2: Use Media stepping instead of SoC die stepping (Matt)
Bspec: 66623
Fixes: 8f70f1ec587d ("drm/i915/mtl: Add Wa_14017073508 for SAMedia")
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
dri
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/power: move dc state members to
struct i915_power_domains (rev2)
URL : https://patchwork.freedesktop.org/series/114431/
State : warning
== Summary ==
Error: dim checkpatch failed
4a10ed5e711d drm/i915/power: move dc state mem
> From: Liu, Yi L
> Sent: Monday, February 27, 2023 7:11 PM
>
> Allow the vfio_device file to be in a state where the device FD is
> opened but the device cannot be used by userspace (i.e. its .open_device()
> hasn't been called). This inbetween state is not used when the device
> FD is spawned f
> From: Liu, Yi L
> Sent: Monday, February 27, 2023 7:12 PM
[...]
> +long vfio_device_ioctl_bind_iommufd(struct vfio_device_file *df,
> + unsigned long arg)
> +{
> + struct vfio_device *device = df->device;
> + struct vfio_device_bind_iommufd bind;
> + s
Users reported oopses on list corruptions when using i915 perf with a
number of concurrently running graphics applications. Root cause analysis
pointed at an issue in barrier processing code -- a race among perf open /
close replacing active barriers with perf requests on kernel context and
concur
Dummy cover letter to prevent CI / patchwork from picking up a previous
one with an outdated Test-with: clause.
Janusz Krzysztofik (1):
drm/i915/active: Fix misuse of non-idle barriers as fence trackers
drivers/gpu/drm/i915/i915_active.c | 25 ++---
1 file changed, 14 inser
Hi Tejas,
On Tue, Feb 28, 2023 at 10:13:07AM +0530, Tejas Upadhyay wrote:
> From: Tvrtko Ursulin
>
> After the abandonment of i915->kernel_context and since we have started to
> create per-gt engine->kernel_context, these tests need to be updated to
> instantiate the batch buffer VMA in the corr
Users reported oopses on list corruptions when using i915 perf with a
number of concurrently running graphics applications. Root cause analysis
pointed at an issue in barrier processing code -- a race among perf open /
close replacing active barriers with perf requests on kernel context and
concur
Dummy cover letter to prevent CI / patchwork from picking up a previous
one with an outdated Test-with: clause.
Janusz Krzysztofik (1):
drm/i915/active: Fix misuse of non-idle barriers as fence trackers
drivers/gpu/drm/i915/i915_active.c | 25 ++---
1 file changed, 14 inser
On Tue, 28 Feb 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Remove the bogus csync check and replace it with something that:
> - triggers for all forms of csync, not just the basic analog variant
> - actually populates the mode csync flags so that drivers can
> decide what to do with th
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