> From: Jason Gunthorpe
> Sent: Tuesday, March 7, 2023 8:38 PM
>
> On Tue, Mar 07, 2023 at 06:38:59AM +, Tian, Kevin wrote:
> > > From: Liu, Yi L
> > > Sent: Friday, March 3, 2023 2:58 PM
> > >
> > > > What should we return here anyhow if an access was created?
> > >
> > > iommufd_access->ob
On Tue, Mar 07, 2023 at 06:38:59AM +, Tian, Kevin wrote:
> > From: Liu, Yi L
> > Sent: Friday, March 3, 2023 2:58 PM
> >
> > > What should we return here anyhow if an access was created?
> >
> > iommufd_access->obj.id. should be fine. Is it?
>
> Thinking more I'm not sure whether it's a goo
On Tue, Mar 07, 2023 at 02:31:11AM +, Tian, Kevin wrote:
> > From: Jason Gunthorpe
> > Sent: Monday, March 6, 2023 9:17 PM
> >
> > On Fri, Mar 03, 2023 at 09:55:42AM -0700, Alex Williamson wrote:
> >
> > > I can't think of a reason DPDK couldn't use hot-reset. If we want to
> > > make it a
On Mon, 06 Mar 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the scanline_offset calculation into its own function. Might
> have further use for this later with DSB scanline waits.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/inte
On Mon, 06 Mar 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move intel_crtc_update_active_timings() into intel_vblank.c
> where it more properly belongs.
Wish the function naming could reflect the file name, but hey, if it
declutters intel_display.c it's good!
Reviewed-by: Jani Nikula
== Series Details ==
Series: Waitboost drm syncobj waits (rev4)
URL : https://patchwork.freedesktop.org/series/113846/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12821 -> Patchwork_113846v4
Summary
---
**FAILURE**
On Mon, 06 Mar 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add some (probably overkill) locking to protect the vblank
> timestamping constants updates during seamless M/N fastsets.
>
> As everything should be naturally aligned I think the individual
> pieces should probably end up updati
On Mon, 06 Mar 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> When we change the M/N values seamlessly during a fastset we should
> also update the vblank timestamping stuff to make sure the vblank
> timestamp corrections/guesstimations come out exact.
>
> Note that only crtc_clock and fram
== Series Details ==
Series: series starting with [1/3] drm/i915: Remove redundant check for DG1
URL : https://patchwork.freedesktop.org/series/114735/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12818_full -> Patchwork_114735v1_full
=
On Tue, 07 Mar 2023, "Lisovskiy, Stanislav"
wrote:
> On Tue, Mar 07, 2023 at 12:23:59PM +0200, Jani Nikula wrote:
>> On Tue, 07 Mar 2023, "Lisovskiy, Stanislav"
>> wrote:
>> > On Mon, Mar 06, 2023 at 08:14:35PM +0200, Jani Nikula wrote:
>> >> On Mon, 27 Feb 2023, Stanislav Lisovskiy
>> >> wro
== Series Details ==
Series: drm/i915/mtl: Apply Wa_14017073508 for MTL Media Step (rev2)
URL : https://patchwork.freedesktop.org/series/114508/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12800 -> Patchwork_114508v2
Summ
Hi,
Issue re-reported, https://patchwork.freedesktop.org/series/114199/
Re-reporting got delayed due to Shards Queue in CI.
Thanks,
Y Sai Nandan
-Original Message-
From: Roper, Matthew D
Sent: Thursday, March 2, 2023 5:00 AM
To: intel-gfx@lists.freedesktop.org
Cc: Andrea Righi ; LGCI
On Tue, Mar 07, 2023 at 12:23:59PM +0200, Jani Nikula wrote:
> On Tue, 07 Mar 2023, "Lisovskiy, Stanislav"
> wrote:
> > On Mon, Mar 06, 2023 at 08:14:35PM +0200, Jani Nikula wrote:
> >> On Mon, 27 Feb 2023, Stanislav Lisovskiy
> >> wrote:
> >> > Display to communicate display pipe count/CDCLK/v
From: Tvrtko Ursulin
Userspace waits coming via the drm_syncobj route have so far been
bypassing the waitboost mechanism.
Use the previously added dma-fence wait tracking API and apply the
same waitboosting logic which applies to other entry points.
This should fix the perfomance regressions ex
From: Tvrtko Ursulin
Use the previously added dma-fence tracking of explicit waiters.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/drm_syncobj.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 0c
From: Tvrtko Ursulin
Use the newly added dma-fence API to apply waitboost not only requests
which have been marked with I915_WAIT_PRIORITY by i915, but which may be
waited upon by others (such as for instance buffer sharing in multi-GPU
scenarios).
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu
From: Tvrtko Ursulin
Use the previously added dma-fence API to mark the direct i915 waits as
explicit. This has no significant effect apart from following the new
pattern.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
From: Tvrtko Ursulin
As signaling is enabled on the container fence we need to propagate any
external waiting status to individual fences in order to enable owning
drivers see it.
Signed-off-by: Tvrtko Ursulin
---
drivers/dma-buf/dma-fence-chain.c | 22 --
include/linux/dma
From: Tvrtko Ursulin
Track how many callers are explicity waiting on a fence to signal and
allow querying that via new dma_fence_wait_count() API.
This provides infrastructure on top of which generic "waitboost" concepts
can be implemented by individual drivers. Wait-boosting is any reactive
act
From: Tvrtko Ursulin
...
Signed-off-by: Tvrtko Ursulin
---
drivers/dma-buf/dma-fence.c | 9 +
include/linux/dma-fence.h | 3 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index bdba5a8e21b1..5607acdb6ccf 1
From: Tvrtko Ursulin
As signaling is enabled on the container fence we need to propagate any
external waiting status to individual fences in order to enable owning
drivers see it.
Signed-off-by: Tvrtko Ursulin
---
drivers/dma-buf/dma-fence-array.c | 5 +++--
1 file changed, 3 insertions(+), 2
From: Tvrtko Ursulin
Use the previously added initialization helper to ensure correct operation
of the common code.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_active.c | 2 +-
drivers/gpu/drm/i915/i915_active.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --g
From: Tvrtko Ursulin
Use the previously added initialization helper to ensure correct operation
of the common code.
Signed-off-by: Tvrtko Ursulin
Cc: Zack Rusin
---
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vmwgfx
From: Tvrtko Ursulin
In preparation of adding a new field to struct dma_fence_cb we will need
an initialization helper for those callers who add callbacks by open-
coding. That will ensure they initialize all the fields so common code
does not get confused by potential garbage in some fields.
Si
From: Tvrtko Ursulin
Unhide some i915 helpers which are used for splitting the signalled
check vs notification stages during en masse fence processing.
Signed-off-by: Tvrtko Ursulin
---
drivers/dma-buf/dma-fence.c | 35 +++--
drivers/gpu/drm/i915/gt/intel_breadc
From: Tvrtko Ursulin
In i915 we have this concept of "wait boosting" where we give a priority boost
for instance to fences which are actively waited upon from userspace. This has
it's pros and cons and can certainly be discussed at lenght. However fact is
some workloads really like it.
Problem i
Hi
Am 05.03.23 um 23:10 schrieb Dmitry Osipenko:
Export drm_gem_un/pin() functions. They will be used by VirtIO-GPU driver
for pinning of an active framebuffer, preventing it from swapping out by
memory shrinker.
Please see my reply to [10/11] on why this patch should not be used.
Best regard
Hi
Am 05.03.23 um 23:10 schrieb Dmitry Osipenko:
[...]
*bo_ptr = bo;
diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c
b/drivers/gpu/drm/virtio/virtgpu_plane.c
index 4c09e313bebc..3f21512ff153 100644
--- a/drivers/gpu/drm/virtio/virtgpu_plane.c
+++ b/drivers/gpu/drm/virtio/virtgpu_plane
== Series Details ==
Series: drm/i915: Bump VBT version for expected child dev size check
URL : https://patchwork.freedesktop.org/series/114721/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12818_full -> Patchwork_114721v1_full
On Tue, 07 Mar 2023, "Lisovskiy, Stanislav"
wrote:
> On Mon, Mar 06, 2023 at 08:14:35PM +0200, Jani Nikula wrote:
>> On Mon, 27 Feb 2023, Stanislav Lisovskiy
>> wrote:
>> > Display to communicate display pipe count/CDCLK/voltage configuration
>> > to Pcode for more accurate power accounting for
== Series Details ==
Series: drm/i915/selftest: Remove avoidable init assignment
URL : https://patchwork.freedesktop.org/series/114755/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12820 -> Patchwork_114755v1
Summary
-
Hi Dave, Daniel,
I apparently didn't send my 2023-02-23 pull request or at least don't see it on
dri-devel, so I added both shortlogs here.
Enjoy!
~Maarten
drm-misc-next-2023-03-07:
drm-misc-next for v6.4-rc1:
UAPI Changes:
Cross-subsystem Changes:
- Add Neil Armstrong as linaro maintainer.
Hi GG,
On Tue, Mar 07, 2023 at 09:33:12AM +0200, Gwan-gyeong Mun wrote:
> Hi Andi,
>
> After applying these two patches, deadlock is being detected in the call
> stack below. Please review whether the patch to update the
> intel_context_migrate_copy() part affected the deadlock.
>
> https://inte
We can skip the assignment and i915 variable
altogether and use refernce directly. Also used at
single place only.
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/selftests/i915_request.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/
On Mon, Mar 06, 2023 at 08:14:35PM +0200, Jani Nikula wrote:
> On Mon, 27 Feb 2023, Stanislav Lisovskiy
> wrote:
> > Display to communicate display pipe count/CDCLK/voltage configuration
> > to Pcode for more accurate power accounting for gen >= 12.
> > Existing sequence is only sending the volta
On Tue, 07 Mar 2023, Jani Nikula wrote:
> On Thu, 02 Mar 2023, Arun R Murthy wrote:
>> Enable SDP error detection configuration, this will set CRC16 in
>> 128b/132b link layer.
>> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
>> added to enable/disable SDP CRC applicable fo
On Thu, 02 Mar 2023, Arun R Murthy wrote:
> Enable SDP error detection configuration, this will set CRC16 in
> 128b/132b link layer.
> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
> added to enable/disable SDP CRC applicable for DP2.0 only, but the
> default value of this b
== Series Details ==
Series: drm/i915/display: Set correct voltage level for 480MHz CDCLK
URL : https://patchwork.freedesktop.org/series/114752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12820 -> Patchwork_114752v1
Summ
On Tue, 21 Feb 2023, Imre Deak wrote:
> Move the display debugfs registration later, after initializing steps
> for opregion/acpi/audio. These latter ones don't depend on the debugfs
> entries, OTOH some debugfs entries may depend on the initialized state.
>
> Signed-off-by: Imre Deak
Patches 1-
On Tue, 21 Feb 2023, Imre Deak wrote:
> Call the opregion register/unregister functions during driver
> loading/unloading on !HAS_DISPLAY platforms. These functions will send
> the opregion adapter power state notifications which is required on all
> platforms (similarly how this is sent during ru
Hello,
In past few days Public GFX CI was affected by two major issues:
# Not all BAT machines were able to reboot successfully after several recent
kernel deadlocks. Each such scenario required manual intervention to get
machines back into execution. WIP to rootcause why hard reboot is not pro
According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.
BSpec: 49208
Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++---
1 file chan
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