> -Original Message-
> From: Deak, Imre
> Sent: Friday, March 17, 2023 10:43 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
>
> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915: Use separate "DC off" power
> well
> for ADL-P and DG2
>
> On Thu, M
Thank you for the review. Merged both the workarounds with updated Bspec page.
- Radhakrishna(RK) Sripada
> -Original Message-
> From: Atwood, Matthew S
> Sent: Wednesday, April 19, 2023 2:49 PM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Cc: intel-gfx@lists.freed
I have a number of comments but most are personal preferences and so i labelled
them nits.
I did catch a few minor coding styling issues and am assuming those need to be
enforced as per i915/kernel rules?
That said, since they are so minor (or maybe they are not strict), I'm
providing a conditio
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev8)
URL : https://patchwork.freedesktop.org/series/115980/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13029 -> Patchwork_115980v8
Summary
-
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev8)
URL : https://patchwork.freedesktop.org/series/115980/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 13/04/2023 20:25, Kandpal, Suraj wrote:
Hi,
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Looks Good to me
Reviewed-by: Suraj Kandpal
And gentle reminder for patches 9-12. We would kindly ask to get this
patches reviewed and ready to be merged into drm-intel after -r
> Hi Fei,
>
>> +#define MTL_PPGTT_PTE_PAT3 BIT_ULL(62)
>> #define GEN12_PPGTT_PTE_LM BIT_ULL(11)
>> +#define GEN12_PPGTT_PTE_PAT2BIT_ULL(7)
>> +#define GEN12_PPGTT_PTE_NC BIT_ULL(5)
>> +#define GEN12_PPGTT_PTE_PAT1BIT_ULL(4)
>> +#define GEN12_PPGTT_PTE_PAT0BIT_ULL(3)
>>
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent, ha
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a def
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for L4 cache calls for
a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8. Th
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
The series includes patches needed to enable MTL.
Also add new extension for GEM_CREATE uAPI to let
user space set cache policy for buffer objects.
v2: addressing review comments and checkpatch warnings
v3: make mtl_ggtt_pte_encode static
Fei Yang (7):
drm/i915/mtl: Set has_llc
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by a
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line. CT
From: Fei Yang
PTE encode functions are platform dependent. This patch implements
PTE functions for MTL, and ensures the correct PTE encode function
is used by calling pte_encode function pointer instead of the
hardcoded gen8 version of PTE encode.
Signed-off-by: Fei Yang
Reviewed-by: Andrzej H
From: Fei Yang
On MTL, LLC is not shared between GT and CPU, set has_llc=0.
Signed-off-by: Fei Yang
Reviewed-by: Andi Shyti
Reviewed-by: Andrzej Hajda
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pc
On Wed, 19 Apr 2023 12:40:44 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Tue, Apr 18, 2023 at 10:23:50AM -0700, Dixit, Ashutosh wrote:
> > On Mon, 17 Apr 2023 22:35:58 -0700, Rodrigo Vivi wrote:
> > >
> >
> > Hi Rodrigo,
> >
> > > On Mon, Apr 10, 2023 at 03:35:09PM -0700, Ashutosh Dixit wrote:
On Wed, 19 Apr 2023 06:21:27 -0700, Tvrtko Ursulin wrote:
>
Hi Tvrtko,
> On 10/04/2023 23:35, Ashutosh Dixit wrote:
> > Instead of erroring out when GuC reset is in progress, block waiting for
> > GuC reset to complete which is a more reasonable uapi behavior.
> >
> > v2: Avoid race between wake_
Hi Fei,
On Wed, Apr 19, 2023 at 02:12:19PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> To comply with the design that buffer objects shall have immutable
> cache setting through out their life cycle, {set, get}_caching ioctl's
> are no longer supported from MTL onward. With that change
Hi Fei,
On Wed, Apr 19, 2023 at 02:12:17PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch is a preparation for replacing enum i915_cache_level with PAT
> index. Caching policy for buffer objects is set through the PAT index in
> PTE, the old i915_cache_level is not sufficient t
Hi Fei,
On Wed, Apr 19, 2023 at 10:10:24PM +, Yang, Fei wrote:
> > Hi Fei,
> >
> > On Wed, Apr 19, 2023 at 02:12:12PM -0700, fei.y...@intel.com wrote:
> >> From: Fei Yang
> >>
> >> On MTL, LLC is not shared between GT and CPU, set has_llc=0.
> >>
> >> Signed-off-by: Fei Yang
> >
> > just an
> Hi Fei,
>
> On Wed, Apr 19, 2023 at 02:12:12PM -0700, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> On MTL, LLC is not shared between GT and CPU, set has_llc=0.
>>
>> Signed-off-by: Fei Yang
>
> just an unanswered questino from Nirmoy:
>
> This statement is bit unclear to me. I would say "
Hi Fei,
> Currently the KMD is using enum i915_cache_level to set caching policy for
> buffer objects. This is flaky because the PAT index which really controls
> the caching behavior in PTE has far more levels than what's defined in the
> enum. In addition, the PAT index is platform dependent, ha
Hi Fei,
On Wed, Apr 19, 2023 at 02:12:16PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> The design is to keep Buffer Object's caching policy immutable through
> out its life cycle. This patch ends the support for set caching ioctl
> from MTL onward. While doing that we also set BO's to
Hi Fei,
On Wed, Apr 19, 2023 at 02:12:15PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch implements Wa_22016122933.
>
> In MTL, memory writes initiated by Media tile update the whole
> cache line even for partial writes. This creates a coherency
> problem for cacheable memory
Hi Fei,
> PTE encode functions are platform dependent. This patch implements
> PTE functions for MTL, and ensures the correct PTE encode function
> is used by calling pte_encode function pointer instead of the
> hardcoded gen8 version of PTE encode.
>
> Signed-off-by: Fei Yang
I think nothing o
Hi Fei,
On Wed, Apr 19, 2023 at 02:12:13PM -0700, fei.y...@intel.com wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> On MTL, GT can no longer allocate on LLC - only the CPU can.
> This, along with addition of support for L4 cache calls for
> a MOCS/PAT table update.
> Also the PAT index r
== Series Details ==
Series: drm/i915/wm: remove stale and unused ilk_wm_max_level() declaration
URL : https://patchwork.freedesktop.org/series/116689/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13029_full -> Patchwork_116689v1_full
=
Hi Fei,
On Wed, Apr 19, 2023 at 02:12:12PM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> On MTL, LLC is not shared between GT and CPU, set has_llc=0.
>
> Signed-off-by: Fei Yang
just an unanswered questino from Nirmoy:
This statement is bit unclear to me. I would say "On MTL, LLC
is
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev7)
URL : https://patchwork.freedesktop.org/series/115980/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13029 -> Patchwork_115980v7
Summary
-
On Tue, Apr 18, 2023 at 03:04:46PM -0700, Radhakrishna Sripada wrote:
> From: Haridhar Kalvala
>
> Workaround implementation to clear RDOP clock gating.
>
> Bspec: 33453
A better bspec value here is 53509, you're referencing a non-updating
page
>
With that.
Reviewed-by: Matt Atwood
> Signed-of
Hi Fei,
> +#define MTL_PPGTT_PTE_PAT3 BIT_ULL(62)
> #define GEN12_PPGTT_PTE_LM BIT_ULL(11)
> +#define GEN12_PPGTT_PTE_PAT2 BIT_ULL(7)
> +#define GEN12_PPGTT_PTE_NC BIT_ULL(5)
> +#define GEN12_PPGTT_PTE_PAT1 BIT_ULL(4)
> +#define GEN12_PPGTT_PTE_PAT0 BIT_ULL(3)
>
> -#define GEN12_GGTT_PTE_
On Tue, Apr 18, 2023 at 03:04:45PM -0700, Radhakrishna Sripada wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> Wa_22011802037 was being applied to all graphics_ver 11 & 12. This patch
> updates the if statement to apply the W/A to right platforms and extends
> it to MTL-M:A step.
>
Bspec:
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev7)
URL : https://patchwork.freedesktop.org/series/115980/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev7)
URL : https://patchwork.freedesktop.org/series/115980/
State : warning
== Summary ==
Error: dim checkpatch failed
b549f1a87da9 drm/i915/mtl: Set has_llc=0
2eee4c46f95e drm/i915/mtl: Define MOCS and PAT tables
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line. CT
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent, ha
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a def
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by a
From: Fei Yang
The series includes patches needed to enable MTL.
Also add new extension for GEM_CREATE uAPI to let
user space set cache policy for buffer objects.
v2: addressing review comments and checkpatch warnings
v3: make mtl_ggtt_pte_encode static
Fei Yang (7):
drm/i915/mtl: Set has_llc
From: Fei Yang
On MTL, LLC is not shared between GT and CPU, set has_llc=0.
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d64e074d7457..272a8ba37b64 100644
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for L4 cache calls for
a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8. Th
From: Fei Yang
PTE encode functions are platform dependent. This patch implements
PTE functions for MTL, and ensures the correct PTE encode function
is used by calling pte_encode function pointer instead of the
hardcoded gen8 version of PTE encode.
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i
Hi Fei,
On Wed, Apr 19, 2023 at 11:09:34AM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> The series includes patches needed to enable MTL.
> Also add new extension for GEM_CREATE uAPI to let
> user space set cache policy for buffer objects.
>
> v2: addressing review comments and checkpa
On Tue, Apr 18, 2023 at 10:23:50AM -0700, Dixit, Ashutosh wrote:
> On Mon, 17 Apr 2023 22:35:58 -0700, Rodrigo Vivi wrote:
> >
>
> Hi Rodrigo,
>
> > On Mon, Apr 10, 2023 at 03:35:09PM -0700, Ashutosh Dixit wrote:
> > > Instead of erroring out when GuC reset is in progress, block waiting for
> > >
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev6)
URL : https://patchwork.freedesktop.org/series/115980/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13029 -> Patchwork_115980v6
Summary
-
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> index 1803a633ed64..98e682b7df07 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> @@ -415,12 +415,6 @@ static int ct_write
== Series Details ==
Series: drm/i915/mtl: Define MOCS and PAT tables for MTL (rev6)
URL : https://patchwork.freedesktop.org/series/115980/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out its life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a defau
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent, ha
From: Fei Yang
PTE encode functions are platform dependent. This patch implements
PTE functions for MTL, and ensures the correct PTE encode function
is used by calling pte_encode function pointer instead of the
hardcoded gen8 version of PTE encode.
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i
From: Fei Yang
On MTL, LLC is not shared between GT and CPU, set has_llc=0.
Signed-off-by: Fei Yang
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d64e074d7457..272a8ba37b64 100644
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to different locations within a single cache line. CT
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by a
From: Fei Yang
The series includes patches needed to enable MTL.
Also add new extension for GEM_CREATE uAPI to let
user space set cache policy for buffer objects.
v2: addressing review comments and checkpatch warnings
Fei Yang (7):
drm/i915/mtl: Set has_llc=0
drm/i915/mtl: Add PTE encode fu
From: Madhumitha Tolakanahalli Pradeep
On MTL, GT can no longer allocate on LLC - only the CPU can.
This, along with addition of support for L4 cache calls for
a MOCS/PAT table update.
Also the PAT index registers are multicasted for primary GT,
and there is an address jump from index 7 to 8. Th
== Series Details ==
Series: drm/i915/wm: remove stale and unused ilk_wm_max_level() declaration
URL : https://patchwork.freedesktop.org/series/116689/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13029 -> Patchwork_116689v1
===
== Series Details ==
Series: drm/hdcp: Pull HDCP auth/exchange/check into helpers (rev10)
URL : https://patchwork.freedesktop.org/series/94712/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/94712/revisions/10/mbox/ not
applied
Applying: drm/hdcp:
On 4/19/2023 10:33, Ceraolo Spurio, Daniele wrote:
On 4/19/2023 10:12 AM, John Harrison wrote:
On 4/19/2023 10:02, John Harrison wrote:
On 4/18/2023 16:24, Ceraolo Spurio, Daniele wrote:
Typo doplicate in patch title
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
On 4/19/2023 10:12 AM, John Harrison wrote:
On 4/19/2023 10:02, John Harrison wrote:
On 4/18/2023 16:24, Ceraolo Spurio, Daniele wrote:
Typo doplicate in patch title
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It was noticed that duplicte entries in the fir
On 4/19/2023 10:02, John Harrison wrote:
On 4/18/2023 16:24, Ceraolo Spurio, Daniele wrote:
Typo doplicate in patch title
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It was noticed that duplicte entries in the firmware table could cause
typo duplicte
an inf
On 4/18/2023 16:24, Ceraolo Spurio, Daniele wrote:
Typo doplicate in patch title
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It was noticed that duplicte entries in the firmware table could cause
typo duplicte
an infinite loop in the firmware loading code if
> On 17.04.2023 08:25, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> The design is to keep Buffer Object's caching policy immutable through
>> out its life cycle. This patch ends the support for set caching ioctl
>> from MTL onward. While doing that we also set BO's to be 1-way
>> coherent at
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> index 1803a633ed64..98e682b7df07 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>> @@ -415,12 +415,6 @@ static int ct_write(struc
On Wed, Apr 19, 2023 at 09:30:11AM -0700, Nathan Chancellor wrote:
> On Wed, Apr 19, 2023 at 06:24:37PM +0200, Daniel Vetter wrote:
> > On Tue, Apr 18, 2023 at 07:34:44PM +0100, Mark Brown wrote:
> > > On Sun, Apr 16, 2023 at 09:58:50AM +0200, Daniel Vetter wrote:
> > >
> > > > Note there was a pp
On Wed, Apr 19, 2023 at 06:24:37PM +0200, Daniel Vetter wrote:
> On Tue, Apr 18, 2023 at 07:34:44PM +0100, Mark Brown wrote:
> > On Sun, Apr 16, 2023 at 09:58:50AM +0200, Daniel Vetter wrote:
> >
> > > Note there was a ppc compile fail, which is why we pushed the ttm revert.
> > > That /should/ be
On Tue, Apr 18, 2023 at 07:34:44PM +0100, Mark Brown wrote:
> On Sun, Apr 16, 2023 at 09:58:50AM +0200, Daniel Vetter wrote:
>
> > Note there was a ppc compile fail, which is why we pushed the ttm revert.
> > That /should/ be fixed now, but would be good if you can confirm?
>
> According to Natha
On 4/18/2023 15:46, Ceraolo Spurio, Daniele wrote:
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
When reduced version firmware files were added (matching major
component being the only strict requirement), the minor version was
still tracked and a notification repo
>> On MTL, GT can no longer allocate on LLC - only the CPU can.
>> This, along with addition of support for L4 cache calls a
> s/calls a/calls for a
Will update
>> MOCS/PAT table update.
>> Alos the PAT index registers are multicasted for primary GT,
> s/Alos/Also
>> and there is an address jump
>> void setup_private_pat(struct intel_gt *gt)
>>
>> GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
>>
>> -if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
>> -xehp_setup_private_ppat(gt);
>> -else if (GRAPHICS_VER(i915) >= 12)
>> -tgl_setup_private_ppat(uncore);
>> -els
> Hi Fei,
>
> On Sun, Apr 16, 2023 at 11:24:57PM -0700, fei.y...@intel.com wrote:
>> From: Madhumitha Tolakanahalli Pradeep
>>
>>
>> On MTL, GT can no longer allocate on LLC - only the CPU can.
>> This, along with addition of support for L4 cache calls a MOCS/PAT
>> table update.
>> Alos the PAT i
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pimp the skl+ scaler register bits with REG_BIT()/etc.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 98 ++---
> 1 file changed, 53 insertions
On 4/18/2023 16:14, Ceraolo Spurio, Daniele wrote:
On 4/14/2023 5:57 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The validation of the firmware table was being done inside the code
for scanning the table for the next available firmware blob. Which is
unnecessary. Potentially, it s
From: Sean Paul
Add the register ranges required for HDCP key injection and
HDCP TrustZone interaction as described in the dt-bindings for the
sc7180 dp controller.
Reviewed-by: Douglas Anderson
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes in v3:
-Split off into a new patc
From: Sean Paul
Add HDCP 1.x support to msm DP bridges using the new HDCP
helpers.
Cc: Stephen Boyd
Reviewed-by: Stephen Boyd
Signed-off-by: Sean Paul
Signed-off-by: Mark Yacoub
---
Changes in v2:
-Squash [1] into this patch with the following changes (Stephen)
-Update the sc7180 dtsi fi
From: Sean Paul
Stick all of the setup for HDCP into a dedicated function. No functional
change, but this will facilitate moving HDCP logic into helpers.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Sean Paul
---
Changes in v2:
-None
Changes in v3:
-None
Changes in v4:
-Non
From: Sean Paul
Now that all of the HDCP 1.x logic has been migrated to the central HDCP
helpers, use it in the i915 driver.
The majority of the driver code for HDCP 1.x will live in intel_hdcp.c,
however there are a few helper hooks which are connector-specific and
need to be partially or fully
From: Sean Paul
Add the bindings for the MSM DisplayPort HDCP registers
which are required to write the HDCP key into the display controller as
well as the registers to enable HDCP authentication/key
exchange/encryption.
Cc: Rob Herring
Cc: Stephen Boyd
Reviewed-by: Rob Herring
Reviewed-by: D
From: Sean Paul
Expand upon the HDCP helper library to manage HDCP enable, disable, and check.
Previous to this patch, the majority of the state management and sink
interaction is tucked inside the Intel driver with the understanding
that once a new platform supported HDCP we could make good dec
From: Sean Paul
The shim functions return error codes, but they are discarded in
intel_hdcp.c. This patch plumbs the return codes through so they are
properly handled.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Reviewed-by: Suraj Kandpal
Signed-off-by: Sean Paul
Signed-off-by: Mark Yaco
From: Sean Paul
Instead of forcing a modeset in the hdcp atomic check, rename to
drm_hdcp_has_changed and return true if the content protection value
is changing and let the driver decide whether a modeset is required or not.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Signed-off-by: Sean
From: Sean Paul
Update the connector's property value in 2 cases which were
previously missed:
1- Content type changes. The value should revert back to DESIRED from
ENABLED in case the driver must re-authenticate the link due to the
new content type.
2- Userspace sets value to DESIRED whi
From: Sean Paul
Move the hdcp atomic check from i915 to drm_hdcp so other
drivers can use it. No functional changes, just cleaned up some of the
code when moving it over.
Acked-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Sean Paul
Signed-off-by: Mar
Hi all,
This is v10 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v10.
Main change in v10 is handling the kernel test bot warnings.
Patches 1-4 focus on moving the common HDCP helpers to common DRM.
This introduces a slight change
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Define and use the bitmasks for the x/y components
> of the skl+ scaler window pos/size registers.
This too should mention the change of mask size.
Typo in subject, *skl+
BR,
Jani.
>
> Signed-off-by: Ville Syrjälä
> ---
> d
On 17.04.2023 08:24, fei.y...@intel.com wrote:
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
to d
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Fix a typo in the PS_COEF_INDEX_AUTO_INC define.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 fil
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename the scaler binding bits to match the spec more closely.
> Also call the parameters 'plane_id' to make it a bit more clear
> what to pass in.
>
> v2: Don't break gvt
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Niku
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename the scaler binding bits to match the spec more closely.
> Also call the parameters 'plane_id' to make it a bit more clear
> what to pass in.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gp
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have some duplicated scaler register defines that are
> never used. Remove them.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 12
> 1 file changed, 12 de
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Define and use the bitmasks for the x/y components
> of the ilk+ panel filter window pos/size registers.
This reduces the field sizes by 3-4 bits. Maybe that's what they're in
the spec, but it's at least worth mentioning here.
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> ilk_pfit_enable() is defined before the first use. No need
> for a forwared declaration.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 -
> 1 file changed,
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Polish the ilk+ pfit registers with REG_BIT() & co., and
> also take the opportunity to unify the ivb/hsw vs. not checks
> in ilk_pfit_enable() and ilk_get_pfit_config().
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikul
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Give the PFIT_CONTROL bits a consistent namespace.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_lvds.c| 2 +-
> drivers/gpu/drm/i915/display/intel_overlay.c | 2 +
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Modernize the gmch pfit register definitions using REG_BIT/etc.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 15 +++---
> drivers/gpu/drm/i915/display/intel
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move skl_get_pfit_config() next to the other skl+ scaler code
> and rename it to skl_scaler_get_config() so that it has a consistnet
> namespace.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/
On Tue, 18 Apr 2023, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move intel_atomic_setup_scalers() next to the other scaler
> code in skl_scaler.c.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 256 ---
> d
On 4/17/2023 8:24 AM, fei.y...@intel.com wrote:
From: Fei Yang
This patch implements Wa_22016122933.
In MTL, memory writes initiated by Media tile update the whole
cache line even for partial writes. This creates a coherency
problem for cacheable memory if both CPU and GPU are writing data
t
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