== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev4)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13078 -> Patchwork_116870v4
Summary
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev4)
URL : https://patchwork.freedesktop.org/series/116870/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: use pat_index instead of cache_level (rev2)
URL : https://patchwork.freedesktop.org/series/117082/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13078 -> Patchwork_117082v2
Summary
== Series Details ==
Series: drm/i915: use pat_index instead of cache_level (rev2)
URL : https://patchwork.freedesktop.org/series/117082/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a
From: Fei Yang
PTE encode is platform dependent. After replacing cache_level with
pat_index, the newly introduced mtl_pte_encode is actually generic
for all gen12 platforms, thus rename it to gen12_pte_encode and
apply it to all gen12 platforms.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent,
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
The first three patches in this series are taken from
https://patchwork.freedesktop.org/series/116868/
These patches are included here because the last patch
has dependency on the pat_index refactor.
This series is focusing on uAPI changes,
1. end support for set caching ioctl
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent,
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by
From: Fei Yang
This patch set was posted at
https://patchwork.freedesktop.org/series/116868/
Change title since the PTE patch was merged separately.
These patches are extracted from series
https://patchwork.freedesktop.org/series/115980/
This series refactor the cache policy programming so
From: Fei Yang
PTE encode is platform dependent. After replacing cache_level with
pat_index, the newly introduced mtl_pte_encode is actually generic
for all gen12 platforms, thus rename it to gen12_pte_encode and
apply it to all gen12 platforms.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by:
On Mon, 01 May 2023 12:44:14 -0700, John Harrison wrote:
>
> On 4/26/2023 14:51, Dixit, Ashutosh wrote:
> > On Tue, 25 Apr 2023 13:19:25 -0700, john.c.harri...@intel.com wrote:
> >> @@ -3623,7 +3624,17 @@ decode_3d_965(struct intel_decode *ctx)
> >>return len;
> >>
> >>case 0x7a00:
On 4/26/2023 14:51, Dixit, Ashutosh wrote:
On Tue, 25 Apr 2023 13:19:25 -0700, john.c.harri...@intel.com wrote:
@@ -3623,7 +3624,17 @@ decode_3d_965(struct intel_decode *ctx)
return len;
case 0x7a00:
- if (IS_GEN6(devid) || IS_GEN7(devid)) {
+
On 4/6/23 19:06, Dmitry Osipenko wrote:
> Change locking policy of mmap() callback, making exporters responsible
> for handling dma-buf reservation locking. Previous locking policy stated
> that dma-buf is locked for both importers and exporters by the dma-buf
> core, which caused a deadlock
I can't say anything about the other commits in this series, but
"Document in which order the CTM matrix elements are stored" is
Reviewed-by: Xaver Hugl
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