== Series Details ==
Series: mtl: add support for pmdemand (rev5)
URL : https://patchwork.freedesktop.org/series/116949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13139_full -> Patchwork_116949v5_full
Summary
---
From: Stanislav Lisovskiy
Currently we seem to be using wrong DPCD register for reading compressed bpps,
reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we get
from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD registe
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as
Currently the required dsc output bpp is set to be the largest
compressed bpp supported for max, lane, rate, and bpp.
The helper intel_dp_dsc_get_output_bpp gets the maximum supported
compressed bpp taking into account link configuration, input bpp,
bigjoiner considerations etc.
Similarly, the hel
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 12
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 5 insertio
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not re
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define
and missing SHIFT")
Cc: Anusha Srivatsa
Cc: Manasi Navare
Cc: # v5.0+
Signed-off-by: Ankit Nautiyal
---
include
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +--
drivers/gpu/drm/i915/display/intel_dp_mst.c |
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed l
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
1 file changed, 2 inse
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-3 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 4-5 are from series DSC fixes for Bigjoiner:
https://patchwork.freede
== Series Details ==
Series: drm/i915/gt: Add workaround 14016712196
URL : https://patchwork.freedesktop.org/series/117661/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M] drivers/gpu/drm/i915/gt/gen8_e
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev12)
URL : https://patchwork.freedesktop.org/series/112647/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13139_full -> Patchwork_112647v12_full
Summary
Wa_14016712196 implementation for mtl
Bspec: 72197
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index
> > Hi Sean,
> > After more thoughts, do you think checking KVM internal memslot is
> > necessary?
>
> I don't think it's necessary per se, but I also can't think of any reason to
> allow
> it.
>
> > slot = gfn_to_memslot(kvm, gfn);
> > if (!slot || slot->id >= KVM_USER_MEM_SLOTS) {
> >
== Series Details ==
Series: drm/i915/gt: drop dependency on VLV_DISPLAY_BASE (rev2)
URL : https://patchwork.freedesktop.org/series/117620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13138_full -> Patchwork_117620v2_full
== Series Details ==
Series: drm/i915/pmu: Turn off the timer to sample frequencies when GT is parked
URL : https://patchwork.freedesktop.org/series/117658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13140 -> Patchwork_117658v1
==
== Series Details ==
Series: drm/i915/guc: Fix confused register capture list creation
URL : https://patchwork.freedesktop.org/series/117655/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13140 -> Patchwork_117655v1
Summary
== Series Details ==
Series: drm/i915/guc: Fix confused register capture list creation
URL : https://patchwork.freedesktop.org/series/117655/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Thu, 2023-05-11 at 18:35 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The GuC has a completely separate engine class enum when referring to
> register capture lists, which combines render and compute. The driver
> was using the 'normal' GuC specific engine class enum inste
pmu_needs_timer() keeps the timer running even when GT is parked,
ostensibly to sample requested/actual frequencies. However
frequency_sample() has the following:
/* Report 0/0 (actual/requested) frequency while parked. */
if (!intel_gt_pm_get_if_awake(gt))
return;
From: John Harrison
The GuC has a completely separate engine class enum when referring to
register capture lists, which combines render and compute. The driver
was using the 'normal' GuC specific engine class enum instead. That
meant that it thought it was defining a capture list for compute
engi
On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin
>
> Reserve some bits in the counter config namespace which will carry the
> tile id and prepare the code to handle this.
>
> No per tile counters have been added yet.
>
> v2:
> - Fix checkpatch issues
> - Us
== Series Details ==
Series: mtl: add support for pmdemand (rev5)
URL : https://patchwork.freedesktop.org/series/116949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13139 -> Patchwork_116949v5
Summary
---
**WARNING
Thank you for the patches and the reviews. Pushed.
- Radhakrishna(RK) Sripada
> -Original Message-
> From: dri-devel On Behalf Of Alan
> Previn
> Sent: Thursday, May 11, 2023 4:18 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Teres Alexis, Alan Previn ; Ursulin,
> Tvrtko ; Juston Li ; d
== Series Details ==
Series: mtl: add support for pmdemand (rev5)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: mtl: add support for pmdemand (rev5)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim checkpatch failed
6f074611e692 drm/i915: fix the derating percentage for MTL
25b686634b4a drm/i915: update the QGV point frequency c
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev12)
URL : https://patchwork.freedesktop.org/series/112647/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13139 -> Patchwork_112647v12
Summary
---
**S
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev12)
URL : https://patchwork.freedesktop.org/series/112647/
State : warning
== Summary ==
Error: dim checkpatch failed
74b5aab9a9a7 drm/i915/pxp: Add GSC-CS back-end resource init and cleanup
Traceback (most recent call last):
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev12)
URL : https://patchwork.freedesktop.org/series/112647/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hello
Thanks for the comments. Pls see some inline replies..
On Thu, 2023-04-27 at 17:24 -0300, Gustavo Sousa wrote:
> Quoting Vinod Govindapillai (2023-04-27 12:00:15)
> > From: Mika Kahola
> >
> > Display14 introduces a new way to instruct the PUnit with
> > power and bandwidth requirements o
From: Mika Kahola
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios
While configuring pmdemand parameters, there could be
intel_get_crtc_new_encoder call where encoders could be 0. To avoid
invoking drm_warn in such cases, use a parameter to indicate drm_warn
should be suppressed.
v2: checkpatch warning fixes
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/d
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105 deletions
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
v2: use idx to store index returned
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
v2: use DIV_ROUND_CLOSEST() for the peakBW calculation
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++--
d
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
>From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
v2: use DIV_ROUND_* macro for the calculations (Ville)
Bspec: 64636
Sign
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the debugfs teardown timeouts to align with
new GSC-CS + firmware specs.
Now that we have 3 places that are selecting pxp timeouts
based on tee vs gsccs back-end, let's add a helper.
Signed-off-by: Alan Previn
Reviewed-by:
pmdemand support patches for MTL
SAGV configuration support for MTL
v2: added one missing patch in the previous version
v3: chekcpatch warning fixes
update index handling for the icl/tgl QGV point handling
program pmdemand code simplified
v4: update to debufs and pipe values pmdemand re
Add GSC engine based method for sending PXP firmware packets
to the GSC firmware for MTL (and future) products.
Use the newly added helpers to populate the GSC-CS memory
header and send the message packet to the FW by dispatching
the GSC_HECI_CMD_PKT instruction on the GSC engine.
We use non-priv
Add helper functions into a new file for heci-packet-submission.
The helpers will handle generating the MTL GSC-CS Memory-Header
and submission of the Heci-Cmd-Packet instructions to the engine.
NOTE1: These common functions for heci-packet-submission will be used
by different i915 callers:
1
Add MTL's function for ARB session creation using PXP firmware
version 4.3 ABI structure format.
While relooking at the ARB session creation flow in intel_pxp_start,
let's address missing UAPI documentation. Without actually changing
backward compatible behavior, update i915's drm-uapi comments
th
Because of the additional firmware, component-driver and
initialization depedencies required on MTL platform before a
PXP context can be created, UMD calling for PXP creation as a
way to get-caps can take a long time. An actual real world
customer stack has seen this happen in the 4-to-8 second ran
Add MTL hw-plumbing enabling for KCR operation under PXP
which includes:
1. Updating 'pick-gt' to get the media tile for
KCR interrupt handling
2. Adding MTL's KCR registers for PXP operation
(init, status-checking, etc.).
While doing #2, lets create a separate registers header file for PXP
On legacy platforms, KCR HW enabling is done at the time the mei
component interface is bound. It's also disabled during unbind.
However, for MTL onwards, we don't depend on a tee component
to start sending GSC-CS firmware messages.
Thus, immediately enable (or disable) KCR HW on PXP's init,
fini
This series enables PXP on MTL. On ADL/TGL platforms, we rely on
the mei driver via the i915-mei PXP component interface to establish
a connection to the security firmware via the HECI device interface.
That interface is used to create and teardown the PXP ARB session.
PXP ARB session is created wh
For MTL, the PXP back-end transport uses the GSC engine to submit
HECI packets through the HW to the GSC firmware for PXP arb
session management. This submission uses a non-priveleged
batch buffer, a buffer for the command packet and of course
a context targeting the GSC-CS.
Thus for MTL, we need
On Mon, May 08, 2023, Yan Zhao wrote:
> On Thu, May 04, 2023 at 10:17:20AM +0800, Yan Zhao wrote:
> > On Wed, May 03, 2023 at 04:16:10PM -0700, Sean Christopherson wrote:
> > > Finally getting back to this series...
> > >
> > > On Thu, Mar 23, 2023, Yan Zhao wrote:
> > > > On Fri, Mar 17, 2023 at
== Series Details ==
Series: drm/i915: Init DDI ports based on port_mask
URL : https://patchwork.freedesktop.org/series/117641/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13138 -> Patchwork_117641v1
Summary
---
**
== Series Details ==
Series: drm/i915: Init DDI ports based on port_mask
URL : https://patchwork.freedesktop.org/series/117641/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Init DDI ports based on port_mask
URL : https://patchwork.freedesktop.org/series/117641/
State : warning
== Summary ==
Error: dim checkpatch failed
7fa5a06bde61 drm/i915: Remove bogus DDI-F from hsw/bdw output init
6ce69347aa4f drm/i915: Introduce device
== Series Details ==
Series: drm/i915/gt: drop dependency on VLV_DISPLAY_BASE (rev2)
URL : https://patchwork.freedesktop.org/series/117620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13138 -> Patchwork_117620v2
Summary
-
On Thu, May 11, 2023 at 01:37:14PM +0300, Juha-Pekka Heikkila wrote:
> Add Tile4 ccs modifiers w/ auxbuffer handling
Commit message should include the workarounds implemented
Wa_14017240301.
>
Bspec: 49251, 49252, 49253
with white space revisions, and commit message update:
Reviewed-by: Matt Atw
Hey,
On 2023-05-11 12:14, Tvrtko Ursulin wrote:
>
> On 10/05/2023 19:46, Tejun Heo wrote:
>> Hello,
>>
>> On Wed, May 10, 2023 at 04:59:01PM +0200, Maarten Lankhorst wrote:
>>> The misc controller is not granular enough. A single computer may have any
>>> number of
>>> graphics cards, some of the
On Thu, May 11, 2023 at 01:37:13PM +0300, Juha-Pekka Heikkila wrote:
> Add Tile4 type ccs modifiers with aux buffer needed for MTL
>
Bspec: 49251, 49252, 49253
> Cc: dri-de...@lists.freedesktop.org
> Cc: Jani Nikula
Reviewed-by: Matt Atwood
> Signed-off-by: Juha-Pekka Heikkila
> ---
> include/
On Wed, May 10, 2023 at 01:31:31PM +0300, Imre Deak wrote:
> If the output on a DP-alt link with its sink disconnected is kept
> enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
> will cause havoc on the PCI bus, at least for other GFX devices on it
> which will stop powerin
On Fri, 05 May 2023 17:58:16 -0700, Umesh Nerlige Ramappa wrote:
>
One drive-by comment:
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 12b2f3169abf..284e5c5b97bb 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@
On Wed, 10 May 2023 11:36:06 -0700, Ashutosh Dixit wrote:
>
> Loading i915 on UBSAN enabled kernels (CONFIG_UBSAN/CONFIG_UBSAN_BOOL)
> causes the following warning:
>
> UBSAN: invalid-load in drivers/gpu/drm/i915/gt/uc/intel_uc.c:558:2
> load of value 255 is not a valid value for type '_Bool'
>
On Wed, May 10, 2023 at 05:10:22PM +0300, Imre Deak wrote:
> On Wed, May 10, 2023 at 05:03:17PM +0300, Ville Syrjälä wrote:
> > On Wed, May 10, 2023 at 01:31:30PM +0300, Imre Deak wrote:
> > > Call the TypeC port flush_work and cleanup handlers without the modeset
> > > locks held. These don't requ
== Series Details ==
Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related
ccs modifiers
URL : https://patchwork.freedesktop.org/series/117625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13134_full -> Patchwork_117625v1_full
===
From: Ville Syrjälä
Make HSW/BDW use port_mask for output probing as well.
To achieve that the strap checks are moved into
intel_ddi_init() itself. Or should we move them to the
runtime port_mask init instead? Maybe not since the hardware
is still there, just not connected to anything.
Signed-of
From: Ville Syrjälä
Instead of listing every platform's possible DDI outputs
in intel_setup_outputs() just loop over the new port_mask
to achieve the same thing.
HSW/BDW were left as is since they still look at the straps
as well.
DSI is still a mess. For now just check for the relevant
platfor
From: Ville Syrjälä
The SDVO code already warns when the port in question doesn't
actually support SDVO. Let's make that also bail the encoder
registration like the generic assert_port_valid() we added.
And add a similar thing for g4x HDMI, mainly because on g4x
itsefl port D only supports DP bu
From: Ville Syrjälä
HSW/BDW don't have DDI-F so don't go looking for one.
Seems to have been accidentally left behind when the
skl+ stuff got split out in commit 097d9e902068
("drm/i915/display: remove strap checks from gen 9").
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/in
From: Ville Syrjälä
Sprinkle some asserts to catch any mishaps in the port_mask
vs. output init.
For DDI/DP/HDMI/SDVO I decided that we want to bail out for
an invalid port since those are the encoder types where
we might want consider driving the whole thing from the VBT
child device list, and
From: Ville Syrjälä
Sprinkle in some BUILD_BUG_ON()s to make sure some of
the bitmasks used in the device info have enough bits.
Do we have a better place for this sort of stuff?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_device_info.c | 4
1 file changed, 4 insertions(+
From: Ville Syrjälä
Declare the available DVO/SDVO/HDMI/DP/DDI ports in the
device info. The other outputs (LVDS/TV/DSI/VGA) are left
out since for most of them we don't consider them as "ports".
DSI we should probably perhaps include somehow in the device
info. Just not sure how. Or we just int
From: Ville Syrjälä
Introduce port_mask into the device info and utilize it
it initalize DDI ports instead of hand rolling each
intel_ddi_init() call per platform+port.
This is an intermediate step towards initializing
DDI/DP/HDMI/DSI ports purely based on VBT information.
Ville Syrjälä (7):
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: aabe491169befbe5481144acf575a0260939764a Add linux-next specific
files for 20230511
Warning reports:
https://lore.kernel.org/oe-kbuild-all/202304140707.coh337ux-...@intel.com
Warning
Hi Fei,
Pushed to drm-intel-gt-next.
There was a "pinky" promise that Tvrtko asked you (and I feel
involved, as well) to make. Let's make sure to follow up on that.
Andi
On Tue, May 09, 2023 at 09:51:58AM -0700, fei.y...@intel.com wrote:
> From: Fei Yang
>
> This patch set was posted at
> htt
On Thu, May 11, 2023 at 06:21:53PM +0300, Jani Nikula wrote:
> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
> intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
> display base area.
>
> Add VLV_GUNIT_BASE to drop dependency on VLV_DISPLAY_BASE and thus
CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
display base area.
Add VLV_GUNIT_BASE to drop dependency on VLV_DISPLAY_BASE and thus
display/intel_display_reg_defs.h in intel_gt_regs.h.
v2: Add VLV_GUNI
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev2)
URL : https://patchwork.freedesktop.org/series/117615/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13133_full -> Patchwork_117615v2_full
Summary
--
On Thu, May 11, 2023 at 03:46:14PM +0300, Jani Nikula wrote:
> On Thu, 11 May 2023, Ville Syrjälä wrote:
> > On Thu, May 11, 2023 at 03:31:16PM +0300, Jani Nikula wrote:
> >> On Thu, 11 May 2023, Ville Syrjälä wrote:
> >> > On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
> >> >> CHV_
On Thu, 11 May 2023, "Kandpal, Suraj" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Thursday, May 11, 2023 2:26 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Teres Alexis, Alan Previn
>> ; Kandpal, Suraj
>> ; Shankar, Uma
>> Subject: [PATCH] drm/i915/hdcp:
Quoting Radhakrishna Sripada (2023-05-10 19:35:52)
>MTL reuses the tuning parameters for DG2. Extend the dg2
>performance tuning parameters to MTL.
>
>Bspec: 68331
>Cc: Matt Roper
>Cc: Gustavo Sousa
>Signed-off-by: Radhakrishna Sripada
Commit cebc13de7e70 ("drm/i915: Whitelist COMMON_SLICE_CHIC
Quoting Radhakrishna Sripada (2023-05-10 19:35:51)
>The dg2 workaround which is used for performance tuning
>is needed for Meteorlake.
>
>Bspec: 68331
>Cc: Matt Roper
>Cc: Gustavo Sousa
>Signed-off-by: Radhakrishna Sripada
The workaround for MTL seems to be necessary only prior to B0 steppings.
== Series Details ==
Series: drm/i915/gt: drop dependency on VLV_DISPLAY_BASE
URL : https://patchwork.freedesktop.org/series/117620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133_full -> Patchwork_117620v1_full
Summar
== Series Details ==
Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related
ccs modifiers
URL : https://patchwork.freedesktop.org/series/117625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13134 -> Patchwork_117625v1
=
== Series Details ==
Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related
ccs modifiers
URL : https://patchwork.freedesktop.org/series/117625/
State : warning
== Summary ==
Error: dim checkpatch failed
1e7c30956aac drm/fourcc: define Intel Meteorlake related ccs modi
== Series Details ==
Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related
ccs modifiers
URL : https://patchwork.freedesktop.org/series/117625/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked s
On Thu, 11 May 2023, Ville Syrjälä wrote:
> On Thu, May 11, 2023 at 03:31:16PM +0300, Jani Nikula wrote:
>> On Thu, 11 May 2023, Ville Syrjälä wrote:
>> > On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
>> >> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
>> >>
On Thu, 2023-05-11 at 14:54 +0300, Ville Syrjälä wrote:
> On Thu, May 11, 2023 at 10:29:01AM +0300, Luca Coelho wrote:
> > On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > To avoid annoying spec lookups let's define more PS_CTRL
> > > bits in the heade
== Series Details ==
Series: drm/i915/hdcp: drop display/ prefix from include
URL : https://patchwork.freedesktop.org/series/117619/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133_full -> Patchwork_117619v1_full
Summar
On Thu, May 11, 2023 at 03:31:16PM +0300, Jani Nikula wrote:
> On Thu, 11 May 2023, Ville Syrjälä wrote:
> > On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
> >> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
> >> intel_gt_regs.h, is in the gcfgmmio unit, but is
On Thu, 11 May 2023, Ville Syrjälä wrote:
> On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
>> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
>> intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
>> display base area.
>>
>> Use the 0x182168
On Thu, May 11, 2023 at 12:04:27PM +0300, Jani Nikula wrote:
> CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
> intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
> display base area.
>
> Use the 0x182168 MMIO address directly to drop dependency on
> VLV
Hi Dave & Daniel,
Here goes drm-intel-fixes for v6.4-rc2.
Important fix to taint kernel when force_probe is used, two display
fixes (null deref/div-by-zero) and a GuC error capture register list
correction.
Regards, Joonas
PS. Again had to remove one commit with incorrect Fixes: tag so check CI
On 09/05/2023 18:12, Yang, Fei wrote:
> On 09/05/2023 00:48, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> Currently the KMD is using enum i915_cache_level to set caching
policy for
>> buffer objects. This is flaky because the PAT index which really
controls
>> the caching behavior
On Thu, May 11, 2023 at 10:29:01AM +0300, Luca Coelho wrote:
> On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > To avoid annoying spec lookups let's define more PS_CTRL
> > bits in the header.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/d
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev2)
URL : https://patchwork.freedesktop.org/series/117615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133 -> Patchwork_117615v2
Summary
---
*
== Series Details ==
Series: Fix modeset locking issue in HDCP MST (rev2)
URL : https://patchwork.freedesktop.org/series/117615/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops
== Series Details ==
Series: drm/i915/gt: drop dependency on VLV_DISPLAY_BASE
URL : https://patchwork.freedesktop.org/series/117620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13133 -> Patchwork_117620v1
Summary
---
== Series Details ==
Series: drm/i915: implement internal workqueues
URL : https://patchwork.freedesktop.org/series/117618/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13132_full -> Patchwork_117618v1_full
Summary
---
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