[Intel-gfx] [PATCH v4 0/6] Add MTL PMU support for multi-gt

With MTL, frequency and rc6 counters are specific to a gt. Export these counters via gt-specific events to the user space. v2: Remove aggregation support from kernel v3: Review comments (Ashutosh, Tvrtko) v4: - Include R-b for 6/6 - Add Test-with - Fix versioning info in cover letter Signed-off-b

[Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based

From: Tvrtko Ursulin Trivial prep work for full multi-tile enablement later. Signed-off-by: Tvrtko Ursulin Signed-off-by: Vinay Belgaumkar Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++-- drivers/gpu/drm/i915/i915_p

[Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

From: Tvrtko Ursulin We do not want to have timers per tile and waste CPU cycles and energy via multiple wake-up sources, for a relatively un-important task of PMU sampling, so keeping a single timer works well. But we also do not want the first GT which goes idle to turn off the timer. Add some

[Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles

From: Tvrtko Ursulin Start exporting frequency and RC6 counters from all tiles. Existing counters keep their names and config values and new one use the namespace added in the previous patch, with the "-gtN" added to their names. Interrupts counter is an odd one off. Because it is the global de

[Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in non-engine counters. Drop FIXME. - Set MAX GTs to 4. Drop FIXM

[Intel-gfx] [PATCH 2/6] drm/i915/pmu: Skip sampling engines with no enabled counters

From: Tvrtko Ursulin As we have more and more engines do not waste time sampling the ones no- one is monitoring. Signed-off-by: Tvrtko Ursulin Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_pmu.c | 3 +++ 1 file changed, 3 insertions(+)

[Intel-gfx] [PATCH 1/6] drm/i915/pmu: Support PMU for all engines

From: Tvrtko Ursulin Given how the metrics are already exported, we also need to run sampling over engines from all GTs. Problem of GT frequencies is left for later. Signed-off-by: Tvrtko Ursulin Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i91

[Intel-gfx] ✗ Fi.CI.BAT: failure for Fix modeset locking issue in HDCP MST (rev3)

== Series Details == Series: Fix modeset locking issue in HDCP MST (rev3) URL : https://patchwork.freedesktop.org/series/117615/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117615v3 Summary --- *

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, May 12, 2023 at 09:41:56PM -0700, Dixit, Ashutosh wrote: On Fri, 12 May 2023 18:55:44 -0700, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev3)

== Series Details == Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev3) URL : https://patchwork.freedesktop.org/series/117729/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117729v3_full

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix modeset locking issue in HDCP MST (rev3)

== Series Details == Series: Fix modeset locking issue in HDCP MST (rev3) URL : https://patchwork.freedesktop.org/series/117615/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops

[Intel-gfx] [PATCH v3 3/4] drm/i915/hdcp: Fix modeset locking issue in hdcp mst

Since topology state is being added to drm_atomic_state now all drm_modeset_lock required are being taken from core. This raises an issue when we try to loop over connector and assign vcpi id to our streams as we did not have atomic state to derive acquire_ctx from. We fill in stream info if dpmst

[Intel-gfx] [PATCH v3 4/4] drm/i915/hdcp: Fill hdcp2_streamid_type and k in appropriate places

stream_id and k(no of streams) should be set in intel_hdcp_set_content_streams. stream_type should be set in intel_hdcp_required_content_stream. Cc: Ankit Nautiyal Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_hdcp.c | 10 -- 1 file changed, 4 insertions(+), 6 dele

[Intel-gfx] [PATCH v3 2/4] drm/i915/hdcp: Remove enforce_type0 check outside loop

Remove enforce_type0 check outside the loop since it does not make sense to keep it there as we use the same digport and continue checking it again and again Cc: Ankit Nautiyal Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_hdcp.c | 6 +++--- 1 file changed, 3 insertions(+)

[Intel-gfx] [PATCH v3 1/4] drm/i915/hdcp: add intel_atomic_state argument to hdcp_enable function

Pass all the parameter in intel_encoder->enable() to intel_hdcp_enable as we need intel_atomic_state later down to get acquire_ctx. Cc: Jani Nikula Cc: Ankit Nautiyal Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_ddi.c| 4 +--- drivers/gpu/drm/i915/display/intel_dp_m

[Intel-gfx] [PATCH v3 0/4] Fix modeset locking issue in HDCP MST

HDCP MST scenario sees modeset locking issue ever since topology_state was added to drm_atomic_state and all modeset locks were being taken for us causing a locking issue to occur when we iterate over connectors to assign vcpi id, the fix being to pass acquire_ctx to drm_modeset_lock. --v2 -call

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev3)

== Series Details == Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev3) URL : https://patchwork.freedesktop.org/series/117729/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117729v3 ==

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev3)

== Series Details == Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev3) URL : https://patchwork.freedesktop.org/series/117729/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be ch

[Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree

Hi all, Today's linux-next merge of the drm-misc tree got a conflict in: drivers/video/fbdev/stifb.c between commit: 8000425739dc ("fbdev: stifb: Remove trailing whitespaces") from Linus' tree and commit: 0d556f1f0e01 ("video: Remove trailing whitespaces") from the drm-misc tree. I fi

[Intel-gfx] linux-next: manual merge of the amdgpu tree with the drm-misc tree

Hi all, Today's linux-next merge of the amdgpu tree got a conflict in: include/drm/display/drm_dp.h between commit: 55b24786b748 ("drm/display: Add missing OLED Vesa brightnesses definitions") from the drm-misc tree and commit: 4d5f872dbc75 ("drm/amd/display: Adding support for VESA SCR

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev2)

== Series Details == Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev2) URL : https://patchwork.freedesktop.org/series/117729/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117729v2 ==

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev2)

== Series Details == Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers (rev2) URL : https://patchwork.freedesktop.org/series/117729/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be ch

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers

== Series Details == Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers URL : https://patchwork.freedesktop.org/series/117729/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117729v1_full ===

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers

== Series Details == Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers URL : https://patchwork.freedesktop.org/series/117729/ State : success == Summary == CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117729v1 =

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers

== Series Details == Series: series starting with [1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers URL : https://patchwork.freedesktop.org/series/117729/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked s

[Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add handling for MTL ccs modifiers

Add Tile4 ccs modifiers w/ auxbuffer handling Implement Wa_14017240301 Bspec: 49251, 49252, 49253 Signed-off-by: Juha-Pekka Heikkila Reviewed-by: Matt Atwood Reviewed-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_fb.c | 42 ++- .../drm/i915/display/skl_universal

[Intel-gfx] [PATCH 1/2] drm/fourcc: define Intel Meteorlake related ccs modifiers

Add Tile4 type ccs modifiers with aux buffer needed for MTL Bspec: 49251, 49252, 49253 Cc: dri-de...@lists.freedesktop.org Cc: Jani Nikula Signed-off-by: Juha-Pekka Heikkila Reviewed-by: Matt Atwood --- include/uapi/drm/drm_fourcc.h | 43 +++ 1 file changed, 43

Re: [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add handling for MTL ccs modifiers

On 11.5.2023 23.13, Matt Atwood wrote: On Thu, May 11, 2023 at 01:37:14PM +0300, Juha-Pekka Heikkila wrote: Add Tile4 ccs modifiers w/ auxbuffer handling Commit message should include the workarounds implemented Wa_14017240301. Bspec: 49251, 49252, 49253 with white space revisions, and commi

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: Add MTL performance tuning changes

On 5/13/2023 7:44 AM, Radhakrishna Sripada wrote: MTL reuses the tuning parameters for DG2. Extend the dg2 performance tuning parameters to MTL. v2: Add DRAW_WATERMARK tuning parameter. Bspec: 68331 Cc: Haridhar Kalvala Cc: Matt Roper Cc: Gustavo Sousa Signed-off-by: Radhakrishna Sripada

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step

On 5/13/2023 7:44 AM, Radhakrishna Sripada wrote: The dg2 workaround which is used for performance tuning is needed for Meteorlake A-step. v2: Limit the WA for A-step Bspec: 68331 Cc: Haridhar Kalvala Cc: Matt Roper Cc: Gustavo Sousa Signed-off-by: Radhakrishna Sripada --- drivers/gpu/d