Hi Uwe,
On Wed 12 Jul 23, 11:46, Uwe Kleine-König wrote:
> Hello,
>
> while I debugged an issue in the imx-lcdc driver I was constantly
> irritated about struct drm_device pointer variables being named "dev"
> because with that name I usually expect a struct device pointer.
Well personally I usu
Hey everyone,
This simplifies the eventfd_signal() and eventfd_signal_mask() helpers
by removing the count argument which is effectively unused.
---
---
base-commit: 6be357f00aad4189130147fdc6f568cf776a4909
change-id: 20230713-vfs-eventfd-signal-0b0d167ad6ec
Hi Jani,
On Thu, Jul 13, 2023 at 11:03 AM Jani Nikula wrote:
> On Wed, 12 Jul 2023, Uwe Kleine-König wrote:
> > On Wed, Jul 12, 2023 at 05:34:28PM +0300, Jani Nikula wrote:
> >> On Wed, 12 Jul 2023, Uwe Kleine-König
> >> wrote:
> >> > while I debugged an issue in the imx-lcdc driver I was cons
On 12.07.2023 13:07, Julia Lawall wrote:
On Wed, 12 Jul 2023, Uwe Kleine-König wrote:
On Wed, Jul 12, 2023 at 12:46:33PM +0200, Christian König wrote:
Am 12.07.23 um 11:46 schrieb Uwe Kleine-König:
Hello,
while I debugged an issue in the imx-lcdc driver I was constantly
irritated about s
Hi
Am 12.07.23 um 20:31 schrieb Sean Paul:
On Wed, Jul 12, 2023 at 10:52 AM Jani Nikula wrote:
On Wed, 12 Jul 2023, Uwe Kleine-König wrote:
Hello,
while I debugged an issue in the imx-lcdc driver I was constantly
irritated about struct drm_device pointer variables being named "dev"
because
On Wed, Jul 12, 2023 at 03:38:03PM +0200, Uwe Kleine-König wrote:
> Hello Maxime,
>
> On Wed, Jul 12, 2023 at 02:52:38PM +0200, Maxime Ripard wrote:
> > On Wed, Jul 12, 2023 at 01:02:53PM +0200, Uwe Kleine-König wrote:
> > > > Background is that this makes merge conflicts easier to handle and
> >
On Thu, 13 Jul 2023, Suraj Kandpal wrote:
> Add function to read any PPS register based on the
> intel_dsc_pps enum provided. Add a function which will call the
> new pps read function and place it in crtc state. Only PPS0 and
> PPS1 are readout the rest of the registers will be read in upcoming
>
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Thursday, July 13, 2023 5:55 PM
> To: Bhadane, Dnyaneshwar ; Jani Nikula
> ; intel-gfx@lists.freedesktop.org; Ursulin,
> Tvrtko
> Cc: Srivatsa, Anusha ; Shankar, Uma
>
> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
On Thu, 13 Jul 2023, Jani Nikula wrote:
> On Thu, 13 Jul 2023, Suraj Kandpal wrote:
>> Add function to read any PPS register based on the
>> intel_dsc_pps enum provided. Add a function which will call the
>> new pps read function and place it in crtc state. Only PPS0 and
>> PPS1 are readout the r
On Thu, 13 Jul 2023, Suraj Kandpal wrote:
> Add function to read any PPS register based on the
> intel_dsc_pps enum provided. Add a function which will call the
> new pps read function and place it in crtc state. Only PPS0 and
> PPS1 are readout the rest of the registers will be read in upcoming
>
Hi Nirmoy and Jonathan,
> > > > @@ -202,6 +202,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq,
> > > > u32 mode)
> > > >{
> > > > struct intel_engine_cs *engine = rq->engine;
> > > > + /*
> > > > +* Aux invalidations on Aux CCS platforms require
> > > > +
== Series Details ==
Series: Add DSC PPS readout (rev2)
URL : https://patchwork.freedesktop.org/series/120456/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13380_full -> Patchwork_120456v2_full
Summary
---
**FAILURE
On Thu, 13 Jul 2023, Suraj Kandpal wrote:
> In intel_vdsc_get_config we only read the primary dsc engine register
> and not take into account if the other dsc engine is in use and if
> both registers have the same value or not this patche fixes that by
> adding a check.
>
> Signed-off-by: Suraj Ka
On 13/07/2023 13:12, Bhadane, Dnyaneshwar wrote:
-Original Message-
From: Tvrtko Ursulin
Sent: Thursday, July 13, 2023 5:26 PM
To: Jani Nikula ; Bhadane, Dnyaneshwar
; intel-gfx@lists.freedesktop.org;
Ursulin, Tvrtko
Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
On 13/07/2023 12:59, Andrzej Hajda wrote:
On 13.07.2023 10:56, Tvrtko Ursulin wrote:
On 13/07/2023 08:39, Tvrtko Ursulin wrote:
On 12/07/2023 19:54, John Harrison wrote:
On 7/12/2023 09:27, Andrzej Hajda wrote:
On 12.07.2023 14:35, Tvrtko Ursulin wrote:
On 12/07/2023 13:18, Andrzej Hajda
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Thursday, July 13, 2023 5:26 PM
> To: Jani Nikula ; Bhadane, Dnyaneshwar
> ; intel-gfx@lists.freedesktop.org;
> Ursulin, Tvrtko
> Subject: Re: [Intel-gfx] [v3] drm/i915/mtl: s/MTL/METEORLAKE for
> platform/subplatform defines
>
>
> O
On 13/07/2023 12:09, Andrzej Hajda wrote:
Hi,
On 13.07.2023 09:39, Tvrtko Ursulin wrote:
On 12/07/2023 19:54, John Harrison wrote:
On 7/12/2023 09:27, Andrzej Hajda wrote:
On 12.07.2023 14:35, Tvrtko Ursulin wrote:
On 12/07/2023 13:18, Andrzej Hajda wrote:
On 11.07.2023 17:27, Tvrtko Urs
== Series Details ==
Series: DSC misc fixes (rev4)
URL : https://patchwork.freedesktop.org/series/117662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13380 -> Patchwork_117662v4
Summary
---
**SUCCESS**
No regres
On 13/07/2023 02:34, Matt Atwood wrote:
Wa_14011274333 applies to RKL, ADL-S, ADL-P and TGL. ALlocate buffer
pinned to GGTT and add WA to restore impacted registers.
v2: use correct lineage number, more generically apply workarounds for
all registers impacted, move workaround to gt/intel_workaro
On 13.07.2023 10:56, Tvrtko Ursulin wrote:
On 13/07/2023 08:39, Tvrtko Ursulin wrote:
On 12/07/2023 19:54, John Harrison wrote:
On 7/12/2023 09:27, Andrzej Hajda wrote:
On 12.07.2023 14:35, Tvrtko Ursulin wrote:
On 12/07/2023 13:18, Andrzej Hajda wrote:
On 11.07.2023 17:27, Tvrtko Ursulin
== Series Details ==
Series: DSC misc fixes (rev4)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 13/07/2023 10:39, Jani Nikula wrote:
On Thu, 13 Jul 2023, Tvrtko Ursulin wrote:
On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
-Original Message-
From: Bhadane, Dnyaneshwar
Sent: Monday, July 10, 2023 4:28 PM
To: intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko ; jani.nik...
Hi,
On 13.07.2023 09:39, Tvrtko Ursulin wrote:
On 12/07/2023 19:54, John Harrison wrote:
On 7/12/2023 09:27, Andrzej Hajda wrote:
On 12.07.2023 14:35, Tvrtko Ursulin wrote:
On 12/07/2023 13:18, Andrzej Hajda wrote:
On 11.07.2023 17:27, Tvrtko Ursulin wrote:
On 11/07/2023 14:58, Andrzej Haj
From: Stanislav Lisovskiy
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
registe
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 49 ++---
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_d
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 191 +++
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal
-
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
drivers/gpu/drm/i915/display/intel_dp.
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not re
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++--
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/dis
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define
and missing SHIFT")
Cc: Anusha Srivatsa
Cc: Manasi Navare
Cc: # v5.0+
Signed-off-by: Ankit Nautiyal
---
include
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal
---
drivers/gp
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed l
Currently we assume 2 Pixels Per Clock (PPC) while computing
plane cdclk and min_cdlck. In cases where DSC single engine
is used the throughput is 1 PPC.
So account for the above case, while computing cdclk.
v2: Use helper to get the adjusted pixel rate.
Signed-off-by: Ankit Nautiyal
---
drive
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Ville Syrjälä
---
dri
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-3 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 4-5 are from series DSC fixes for Bigjoiner:
https://patchwork.freede
== Series Details ==
Series: Add DSC PPS readout (rev2)
URL : https://patchwork.freedesktop.org/series/120456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13380 -> Patchwork_120456v2
Summary
---
**SUCCESS**
No r
On Thu, 13 Jul 2023, Tvrtko Ursulin wrote:
> On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
>>> -Original Message-
>>> From: Bhadane, Dnyaneshwar
>>> Sent: Monday, July 10, 2023 4:28 PM
>>> To: intel-gfx@lists.freedesktop.org
>>> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
>>> Sr
== Series Details ==
Series: Add DSC PPS readout (rev2)
URL : https://patchwork.freedesktop.org/series/120456/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning:
== Series Details ==
Series: Add DSC PPS readout (rev2)
URL : https://patchwork.freedesktop.org/series/120456/
State : warning
== Summary ==
Error: dim checkpatch failed
522b07084859 drm/i915/vdsc: Refactor dsc register field macro
-:174: WARNING:LONG_LINE: line length of 101 exceeds 100 colum
On 7/12/2023 5:39 PM, Cavitt, Jonathan wrote:
-Original Message-
From: Nirmoy Das
Sent: Wednesday, July 12, 2023 7:18 AM
To: Andi Shyti ; Cavitt, Jonathan
Cc: Intel GFX ; Roper, Matthew D
; Chris Wilson ; Mika Kuoppala
Subject: Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Ensure me
Hi Dave and Daniel,
this is the main pull request for drm-misc-next for what will become
Linux v6.6. Some noteworthy changes are:
* GEM got execution contexts that help with locking multiple GEM
objects at once.
* All DRM drivers can now self-import their own dma-bufs by default.
This en
On 13/07/2023 08:39, Tvrtko Ursulin wrote:
On 12/07/2023 19:54, John Harrison wrote:
On 7/12/2023 09:27, Andrzej Hajda wrote:
On 12.07.2023 14:35, Tvrtko Ursulin wrote:
On 12/07/2023 13:18, Andrzej Hajda wrote:
On 11.07.2023 17:27, Tvrtko Ursulin wrote:
On 11/07/2023 14:58, Andrzej Hajda
On 10/07/2023 14:44, Bhadane, Dnyaneshwar wrote:
-Original Message-
From: Bhadane, Dnyaneshwar
Sent: Monday, July 10, 2023 4:28 PM
To: intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
Srivatsa, Anusha ; Bhadane, Dnyaneshwar
Subject: [v3] drm/i915/mtl:
Hi,
Sending again because I had to send it by hand and forgot to add all the
recipients in Cc.
Here's this week drm-misc-fixes PR, plus last week as well that got
dropped for some reason.
Thanks!
Maxime
The following changes since commit 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5:
Linux 6.5-rc
On 12/07/2023 18:49, Teres Alexis, Alan Previn wrote:
On Wed, 2023-07-12 at 10:19 +0100, Tvrtko Ursulin wrote:
On 11/07/2023 23:02, Alan Previn wrote:
On MTL, if the GSC Proxy init flows haven't completed, submissions to the
GSC engine will fail. Those init flows are dependent on the mei's
gs
On 12/07/2023 19:54, John Harrison wrote:
On 7/12/2023 09:27, Andrzej Hajda wrote:
On 12.07.2023 14:35, Tvrtko Ursulin wrote:
On 12/07/2023 13:18, Andrzej Hajda wrote:
On 11.07.2023 17:27, Tvrtko Ursulin wrote:
On 11/07/2023 14:58, Andrzej Hajda wrote:
On 11.07.2023 13:34, Andi Shyti wrote
Hi Dave, Daniel,
Just a few small fixes for the 6.5 RC this week - one functional fixup for
reading of perf/OA buffers and some code cleanups elsewhere.
Regards,
Tvrtko
drm-intel-fixes-2023-07-13:
- Don't preserve dpll_hw_state for slave crtc in Bigjoiner (Stanislav Lisovskiy)
- Consider OA buf
101 - 155 of 155 matches
Mail list logo
