== Series Details ==
Series: drm: Refactor plane size calculation by core helper functions
URL : https://patchwork.freedesktop.org/series/121012/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13396_full -> Patchwork_121012v1_full
== Series Details ==
Series: drm: Refactor plane size calculation by core helper functions
URL : https://patchwork.freedesktop.org/series/121012/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13396 -> Patchwork_121012v1
== Series Details ==
Series: drm: Refactor plane size calculation by core helper functions
URL : https://patchwork.freedesktop.org/series/121012/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm: Refactor plane size calculation by core helper functions
URL : https://patchwork.freedesktop.org/series/121012/
State : warning
== Summary ==
Error: dim checkpatch failed
a5fc4b7c1a46 drm: Remove plane hsub/vsub alignment requirement for core helpers
-:16:
The functions drm_framebuffer_plane_{width,height} and
fb_plane_{width,height} do exactly the same job of its
equivalents drm_format_info_plane_{width,height} from drm_fourcc.
The only reason to have these functions on drm_framebuffer
would be if they would added a abstraction layer to call it
The drm_format_info_plane_{height,width} functions was implemented using
regular division for the plane size calculation, which cause issues [1][2]
when used on contexts where the dimensions are misaligned with relation
to the subsampling factors. So, replace the regular division by the
There's duplicated functions on drm that do the same job of calculating
the size of planes from a drm_format_info and the size of its first
plane. So this patchset throw away the more specific version intended
to be used from a given framebuffer and make the generic version way
more portable
On Wed, Jul 19, 2023 at 05:07:15PM -0700, Yang, Fei wrote:
> [snip]
> >> @@ -27,15 +28,8 @@ static bool gpu_write_needs_clflush(struct
> >> drm_i915_gem_object *obj)
> >
> > The code change here looks accurate, but while we're here, I have a side
> > question about this function in general...it
[snip]
>> @@ -27,15 +28,8 @@ static bool gpu_write_needs_clflush(struct
>> drm_i915_gem_object *obj)
>
> The code change here looks accurate, but while we're here, I have a side
> question about this function in general...it was originally introduced
> in commit 48004881f693 ("drm/i915: Mark CPU
On Wed, Jul 19, 2023 at 08:28:12AM -0700, Matt Roper wrote:
> On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
> >
> > On 18/07/2023 23:27, Matt Roper wrote:
> > > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > > of these workarounds are actually tied to
On 2023/7/20 03:32, Bjorn Helgaas wrote:
but I think it's just confusing to
mention this in the commit log, so I would just remove it.
Ok, will be done at the next version.
On 2023/7/20 06:32, suijingfeng wrote:
it will be works no matter CONFIG_DRM_AST=m or CONFIG_DRM_AST=y
It will be works regardless of CONFIG_DRM_AST=m or CONFIG_DRM_AST=y.
When vgaarb call to the device driver, device driver already loaded
successfully.
and the PCI(e) device emulation
Hi,
On 2023/7/20 03:32, Bjorn Helgaas wrote:
[+cc linux-pci (please cc in the future since the bulk of this patch
is in drivers/pci/)]
On Wed, Jul 12, 2023 at 12:43:05AM +0800, Sui Jingfeng wrote:
From: Sui Jingfeng
Currently, the strategy of selecting the default boot on a multiple video
On Wed, Jul 19, 2023 at 01:37:30PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Commit 9275277d5324 ("drm/i915: use pat_index instead of cache_level") has
> introduced PAT indices to i915 internal APIs, partially replacing the
> usage of driver internal cache_level, but has also added
Hi,
On 2023/7/20 04:43, Bjorn Helgaas wrote:
[+cc linux-pci; I don't apply or ack PCI patches unless they appear there]
On Wed, Jul 12, 2023 at 12:43:04AM +0800, Sui Jingfeng wrote:
From: Sui Jingfeng
The observation behind this is that we should avoid accessing the global
screen_info
This is a unified version of the 3 separate PRs that I've sent in the
last week. If there are no CI issues, this version will be sent to
linux-firmware instead of the other 3.
The following changes since commit d3f66064cf43bd7338a79174bd0ff60c4ecbdf6d:
Partially revert "amdgpu: DMCUB updates
Hi,
On 2023/7/20 04:43, Bjorn Helgaas wrote:
On Wed, Jul 12, 2023 at 12:43:02AM +0800, Sui Jingfeng wrote:
From: Sui Jingfeng
This patch adds the aperture_contain_firmware_fb() function to do the
determination. Unfortunately, due to the fact that the apertures list
will be freed
> On 18/07/2023 23:51, Radhakrishna Sripada wrote:
>> Dpt objects that are created from internal get evicted when there is
>> memory pressure and do not get restored when pinned during scanout.
>> The pinned page table entries look corrupted and programming the
>> display engine with the incorrect
On Wed, Jul 12, 2023 at 12:43:02AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> This patch adds the aperture_contain_firmware_fb() function to do the
> determination. Unfortunately, due to the fact that the apertures list
> will be freed dynamically, the location and size information of
[+cc linux-pci; I don't apply or ack PCI patches unless they appear there]
On Wed, Jul 12, 2023 at 12:43:04AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> The observation behind this is that we should avoid accessing the global
> screen_info directly. Call the
On Wed, Jul 12, 2023 at 4:47 AM Tvrtko Ursulin
wrote:
>
> drm.memory.stat
> A nested file containing cumulative memory statistics for the whole
> sub-hierarchy, broken down into separate GPUs and separate memory
> regions supported by the latter.
>
> For
Quoting Gustavo Sousa (2023-07-19 16:39:25-03:00)
>Quoting Matt Roper (2023-07-18 19:28:01-03:00)
>>Most of the IS_METEORLAKE checks in the display code shouldn't actually
>>be tied to MTL as a platform, but rather to the Xe_LPD+ display IP
>>(which is used in MTL, but may show up again in future
Quoting Matt Roper (2023-07-18 19:28:01-03:00)
>Most of the IS_METEORLAKE checks in the display code shouldn't actually
>be tied to MTL as a platform, but rather to the Xe_LPD+ display IP
>(which is used in MTL, but may show up again in future platforms). In
>cases where we're trying to match
[+cc linux-pci]
On Wed, Jul 12, 2023 at 12:43:01AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> Currently, the default VGA device selection is not perfect. Potential
> problems are:
>
> 1) This function is a no-op on non-x86 architectures.
> 2) It does not take the PCI Bar may get
[+cc linux-pci (please cc in the future since the bulk of this patch
is in drivers/pci/)]
On Wed, Jul 12, 2023 at 12:43:05AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> Currently, the strategy of selecting the default boot on a multiple video
> card coexistence system is not perfect.
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests
URL : https://patchwork.freedesktop.org/series/120991/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13396 -> Patchwork_120991v1
Summary
---
Quoting Matt Roper (2023-07-18 19:28:00-03:00)
>Now that we properly match the Xe_LPG IP versions associated with
>various workarounds, there's no longer any need to define separate MTL
>subplatform in the driver. Nothing in the code is conditional on MTL-M
>or MTL-P base platforms. Furthermore,
Quoting Matt Roper (2023-07-18 19:27:59-03:00)
>Stepping-specific display behavior shouldn't be tied to MTL as a
>platform, but rather specifically to the Xe_LPM+ IP. Future non-MTL
s/Xe_LPD+/Xe_LPDM+/ ?
The changes for this and the previous two patches look correct to me,
but I would also be
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests
URL : https://patchwork.freedesktop.org/series/120991/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests
URL : https://patchwork.freedesktop.org/series/120991/
State : warning
== Summary ==
Error: dim checkpatch failed
98626971c431 drm/i915: use direct alias for i915 in requests
-:122: WARNING:AVOID_BUG: Do not crash
== Series Details ==
Series: Revert "Revert "drm/i915: Hold reference to intel_context over life of
i915_request""
URL : https://patchwork.freedesktop.org/series/120990/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13396 -> Patchwork_120990v1
== Series Details ==
Series: drm/i915/tv: avoid possible division by zero (rev2)
URL : https://patchwork.freedesktop.org/series/120851/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13396_full -> Patchwork_120851v2_full
== Series Details ==
Series: Revert "Revert "drm/i915: Hold reference to intel_context over life of
i915_request""
URL : https://patchwork.freedesktop.org/series/120990/
State : warning
== Summary ==
Error: dim checkpatch failed
08ce05640e8f Revert "Revert "drm/i915: Hold reference to
Quoting Matt Roper (2023-07-18 19:27:56-03:00)
>Although some of our Xe_LPG workarounds were already being applied based
>on IP version correctly, others were matching on MTL as a base platform,
>which is incorrect. Although MTL is the only platform right now that
>uses Xe_LPG IP, this may not
> -Original Message-
> From: Roper, Matthew D
> Sent: Wednesday, July 19, 2023 3:58 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D
> Subject: [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms
>
> Now that we properly match the Xe_LPG IP versions associated
Quoting Matt Roper (2023-07-18 19:27:55-03:00)
>The workaround bounds for Wa_22011802037 are somewhat complex and are
>replicated in several places throughout the code. Pull the condition
>out to a helper function to prevent mistakes if this condition needs to
>change again in the future.
>
== Series Details ==
Series: drm/i915/tv: avoid possible division by zero (rev2)
URL : https://patchwork.freedesktop.org/series/120851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13396 -> Patchwork_120851v2
Summary
== Series Details ==
Series: drm/i915/tc: some clean-ups in max lane count handling code
URL : https://patchwork.freedesktop.org/series/120980/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M]
== Series Details ==
Series: drm/i915: Start using plane scale factor for relative data rate (rev3)
URL : https://patchwork.freedesktop.org/series/120767/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13395_full -> Patchwork_120767v3_full
Hi Luca,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Luca-Coelho/drm-i915-tc-rename-mtl_tc_port_get_pin_assignment_mask/20230719-213204
base: git://anongit.freedesktop.org/drm/drm-tip
On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
>
> On 18/07/2023 23:27, Matt Roper wrote:
> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > of these workarounds are actually tied to MTL as a platform; they only
> > relate to the Xe_LPG graphics IP,
On Wed, Jul 19, 2023 at 08:57:15AM +0100, Tvrtko Ursulin wrote:
>
> On 18/07/2023 23:28, Matt Roper wrote:
> > Many of the IS_METEORLAKE conditions throughout the driver are supposed
> > to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
> > specifically. Update those checks to
i915_request contains direct alias to i915, there is no point to go via
rq->engine->i915.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18
Hi Luca,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Luca-Coelho/drm-i915-tc-rename-mtl_tc_port_get_pin_assignment_mask/20230719-213204
base: git://anongit.freedesktop.org/drm/drm-tip
This reverts commit bcb9aa45d5a0e11ef91245330c53cde214d15e8d.
The problem with this patch is that it makes rq->engine dangling pointer
after context removal. At least two places were located where it ends
with errors:
- i915_fence_release: intel_engine_is_virtual(rq->engine),
-
== Series Details ==
Series: drm/i915: Refactor PAT/object cache handling (rev2)
URL : https://patchwork.freedesktop.org/series/120924/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13395 -> Patchwork_120924v2
Summary
== Series Details ==
Series: drm/i915: Refactor PAT/object cache handling (rev2)
URL : https://patchwork.freedesktop.org/series/120924/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Refactor PAT/object cache handling (rev2)
URL : https://patchwork.freedesktop.org/series/120924/
State : warning
== Summary ==
Error: dim checkpatch failed
17d1cb1da24d drm/i915: Refactor PAT/object cache handling
Traceback (most recent call last):
On 2023/7/18 19:28, Andrzej Hajda wrote:
On 18.07.2023 12:10, Su Hui wrote:
On 2023/7/18 13:39, Dan Carpenter wrote:
On Mon, Jul 17, 2023 at 04:52:51PM +0200, Andrzej Hajda wrote:
On 17.07.2023 08:22, Su Hui wrote:
Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
line 991, column 22
On 2023/7/18 13:39, Dan Carpenter wrote:
On Mon, Jul 17, 2023 at 04:52:51PM +0200, Andrzej Hajda wrote:
On 17.07.2023 08:22, Su Hui wrote:
Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
line 991, column 22 Division by zero.
Assuming tv_mode->oversample=1 and
Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
line 991, column 22 Division by zero.
Assuming tv_mode->oversample=1 and (!tv_mode->progressive)=1,
then division by zero will happen.
Fixes: 1bba5543e4fe ("drm/i915: Fix TV encoder clock computation")
Signed-off-by: Su Hui
---
On 2023/7/17 22:52, Andrzej Hajda wrote:
On 17.07.2023 08:22, Su Hui wrote:
Clang warning: drivers/gpu/drm/i915/display/intel_tv.c:
line 991, column 22 Division by zero.
Assuming tv_mode->oversample=1 and (!tv_mode->progressive)=1,
then division by zero will happen.
Fixes: 1bba5543e4fe
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Avoid endless HPD poll detect
loop via runtime suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/120931/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13395 -> Patchwork_120931v2
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Avoid endless HPD poll detect
loop via runtime suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/120931/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Avoid endless HPD poll detect
loop via runtime suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/120931/
State : warning
== Summary ==
Error: dim checkpatch failed
eef2b2d4e3b7 drm/i915: Avoid endless HPD
== Series Details ==
Series: Update AUX invalidation sequence (rev6)
URL : https://patchwork.freedesktop.org/series/119798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13395 -> Patchwork_119798v6
Summary
---
On 18/07/2023 23:51, Radhakrishna Sripada wrote:
Dpt objects that are created from internal get evicted when there is
memory pressure and do not get restored when pinned during scanout. The
pinned page table entries look corrupted and programming the display
engine with the incorrect pte's
This function is only used locally, so make it static and remove the
definition from the header file.
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git
It is irrelevant for the caller that the max lane count is being
derived from a FIA register, so having "fia" in the function name is
irrelevant. Rename the function accordingly.
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
This makes the code a bit more symmetric and readable, especially when
we start adding more display version-specific alternatives.
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_tc.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git
This function doesn't really return the pin assigment mask, but the
max lane count derived from that. So rename the function to
mtl_tc_port_get_max_lane_count() to better reflect what it really does.
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_tc.c | 4 ++--
1 file
Hi,
Here are four patches with some clean-ups in the code that handles the
max lane count of Type-C connections.
This is done mostly in preparation for a new way to read the pin
assignments and lane count in future devices.
Please review.
Cheers,
Luca.
Luca Coelho (4):
drm/i915/tc: rename
== Series Details ==
Series: Update AUX invalidation sequence (rev6)
URL : https://patchwork.freedesktop.org/series/119798/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Update AUX invalidation sequence (rev6)
URL : https://patchwork.freedesktop.org/series/119798/
State : warning
== Summary ==
Error: dim checkpatch failed
501b25e131de drm/i915/gt: Cleanup aux invalidation registers
cab2ff5e8756 drm/i915: Add the has_aux_ccs device
== Series Details ==
Series: drm/i915: Start using plane scale factor for relative data rate (rev3)
URL : https://patchwork.freedesktop.org/series/120767/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13395 -> Patchwork_120767v3
On 19/07/2023 11:41, Andrzej Hajda wrote:
On 18.07.2023 17:48, Tvrtko Ursulin wrote:
On 17/07/2023 19:03, John Harrison wrote:
On 7/13/2023 05:11, Tvrtko Ursulin wrote:
On 13/07/2023 12:09, Andrzej Hajda wrote:
Hi,
On 13.07.2023 09:39, Tvrtko Ursulin wrote:
On 12/07/2023 19:54, John
From: Tvrtko Ursulin
Commit 9275277d5324 ("drm/i915: use pat_index instead of cache_level") has
introduced PAT indices to i915 internal APIs, partially replacing the
usage of driver internal cache_level, but has also added a few
questionable design decisions which this patch tries to improve
The issue fixed in
commit a8ddac7c9f06 ("drm/i915: Avoid HPD poll detect triggering a new detect
cycle")
on VLV, CHV is still present on platforms where the display hotplug
detection functionality is available whenever the device is in D0 state
(hence these platforms switch to HPD polling only
Perform some refactoring with the purpose of keeping in one
single place all the operations around the aux table
invalidation.
With this refactoring add more engines where the invalidation
should be performed.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
From: Jonathan Cavitt
For platforms that use Aux CCS, wait for aux invalidation to
complete by checking the aux invalidation register bit is
cleared.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc:
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112). The VE and BCS engines need to add the flush
part in their command streamer.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all
Commit af9e423a8aae ("drm/i915/gt: Ensure memory quiesced before
invalidation") has made sure that the memory is quiesced before
invalidating the AUX CCS table. Do it for all the other engines
and not just RCS.
Signed-off-by: Andi Shyti
Cc: Jonathan Cavitt
Cc: Matt Roper
---
Just a trivial refactoring for reducing the number of code
duplicate. This will come at handy in the next commits.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 44 +---
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git
Fix the 'NV' definition postfix that is supposed to be INV.
Take the chance to also order properly the registers based on
their address and call the GEN12_GFX_CCS_AUX_INV address as
GEN12_CCS_AUX_INV like all the other similar registers.
Remove also VD1, VD3 and VE1 registers that don't exist
In preparation of the next patch align with the datasheet (BSPEC
47112) with the naming of the pipe control set of flag values.
The variable "flags" in gen12_emit_flush_rcs() is applied as a
set of flags called Bit Group 1.
Define also the Bit Group 0 as bit_group_0 where currently only
From: Jonathan Cavitt
All memory traffic must be quiesced before requesting
an aux invalidation on platforms that use Aux CCS.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Jonathan Cavitt
Signed-off-by: Andi Shyti
Cc: # v5.8+
Reviewed-by:
We always assumed that a device might either have AUX or FLAT
CCS, but this is an approximation that is not always true as it
requires some further per device checks.
Add the "has_aux_ccs" flag in the intel_device_info structure in
order to have a per device flag indicating of the AUX CCS.
Hi,
as there are new hardware directives, we need a little adaptation
for the AUX invalidation sequence.
In this version we support all the engines affected by this
change.
The stable backport has some challenges because the original
patch that this series fixes has had more changes in between.
> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Wednesday, July 19, 2023 4:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav ; Saarinen, Jani
> ; Garg, Nemesa
> Subject: [PATCH] drm/i915: Start using plane scale factor for relative data
> rate
>
> BSpec
BSpec clearly instructs us to use plane scale factor when calculating
relative data rate to be used when allocating DDB blocks for each plane.
For some reason we use scale factor for data_rate calculation, which is
used for BW calculations, however we are not using it for DDB calculations.
So lets
On 18.07.2023 17:48, Tvrtko Ursulin wrote:
On 17/07/2023 19:03, John Harrison wrote:
On 7/13/2023 05:11, Tvrtko Ursulin wrote:
On 13/07/2023 12:09, Andrzej Hajda wrote:
Hi,
On 13.07.2023 09:39, Tvrtko Ursulin wrote:
On 12/07/2023 19:54, John Harrison wrote:
On 7/12/2023 09:27, Andrzej
> -Original Message-
> From: Intel-gfx On Behalf Of intel-
> gfx-requ...@lists.freedesktop.org
> Sent: Friday, July 14, 2023 7:10 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: Intel-gfx Digest, Vol 186, Issue 211
>
> Send Intel-gfx mailing list submissions to
>
On 18/07/2023 19:37, Dixit, Ashutosh wrote:
On Tue, 18 Jul 2023 01:40:41 -0700, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Feature test also needs adjusting after sysfs helper API changes...
Signed-off-by: Tvrtko Ursulin
Fixes: d86ca7e17b58 ("tests/i915_pm_rps: Exercise sysfs
On 18/07/2023 23:27, Matt Roper wrote:
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
of these workarounds are actually tied to MTL as a platform; they only
relate to the Xe_LPG graphics IP, regardless of what platform it appears
in. At the moment MTL is the only
On 18/07/2023 23:28, Matt Roper wrote:
Many of the IS_METEORLAKE conditions throughout the driver are supposed
to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
specifically. Update those checks to ensure that the code will still
operate properly if/when these IP versions
Hi,
On Mon, Jul 17, 2023 at 04:04:43PM -0300, Carlos wrote:
> On 7/12/23 20:30, André Almeida wrote:
> > Hi Carlos,
> >
> > Em 27/06/2023 15:22, Carlos Eduardo Gallo Filho escreveu:
> > [...]
> > >
> > > So, replace each drm_framebuffer_plane_{width,height} and
> > > fb_plane_{width,height}
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