> Subject: [Intel-gfx] [PATCH 2/3] drm: Add Wrapper Functions for ELD SAD
> Extraction
>
> Add wrapper functions to facilitate extracting Short Audio Descriptor (SAD)
> information from EDID-Like Data (ELD) pointers with different constness
> requirements.
>
> 1. `drm_eld_sad`: This function retu
Am 04.09.23 um 21:57 schrieb Sui Jingfeng:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which one
is primary at boot time.
Question is why is that useful? Should we give users the ability to
control that?
I don't see an use case for this.
Regards,
C
On Mon, Sep 04, 2023 at 02:08:38PM +0300, Imre Deak wrote:
> On Mon, Sep 04, 2023 at 06:48:25AM +0300, Ville Syrjälä wrote:
> > On Thu, Aug 24, 2023 at 11:04:59AM +0300, Imre Deak wrote:
> > > In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
> > > range, while in DSC mode it
== Series Details ==
Series: PCI/VGA: Allowing the user to select the primary video adapter at boot
time
URL : https://patchwork.freedesktop.org/series/123258/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13594_full -> Patchwork_123258v1_full
== Series Details ==
Series: PCI/VGA: Allowing the user to select the primary video adapter at boot
time
URL : https://patchwork.freedesktop.org/series/123258/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13594 -> Patchwork_123258v1
==
== Series Details ==
Series: PCI/VGA: Allowing the user to select the primary video adapter at boot
time
URL : https://patchwork.freedesktop.org/series/123258/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately
From: Sui Jingfeng
Becasuse the display controller in the ASpeed BMC chip is a VGA-compatible
device, the software programming guide of AST2400 say that it is fully
IBM VGA compliant. Thus, it should also participate in the arbitration.
Cc: Thomas Zimmermann
Cc: Jocelyn Falempe
Signed-off-by:
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which one
is primary at boot time. This patch tries to solve the mentioned problem by
implementing the .be_primary() callback. Pass radeon.modeset=10 on the
kernel cmd line if you really want the device bound by
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
problem by introduced the ->be_primary() function stub. The specific
device drivers can provide an implementation to hook up with this
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which
one is primary at boot time. This series tries to solve above mentioned
problem by introduced the ->be_primary() function stub. The specific
device drivers can provide an implementation to hook up with this
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which one
is primary at boot time. This patch tries to solve the mentioned problem by
implementing the .be_primary() callback. Pass amdgpu.modeset=10 on the
kernel cmd line if you really want the device bound by
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which one
is primary at boot time. This patch tries to solve the mentioned problem by
implementing the .be_primary() callback. Pass loongson.modeset=10 on the
kernel cmd line if you really want the device bound b
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which one
is primary at boot time. This patch tries to solve the mentioned problem by
implementing the .be_primary() callback. Pass i915.modeset=10 on the kernel
cmd line if you really want the device bound by i9
From: Sui Jingfeng
Because the display controller in the Hibmc chip is a VGA compatible
display controller. Because ARM64 doesn't need the VGA console. It does not
need to worry about the side effects that come with the VGA compatible.
However, the real problem is that some ARM64 PCs and servers
From: Sui Jingfeng
On a machine with multiple GPUs, a Linux user has no control over which one
is primary at boot time. This patch tries to solve the mentioned problem by
implementing the .be_primary() callback. VGAARB will call back to Nouveau
when the drm/nouveau gets loaded successfully.
Pass
From: Sui Jingfeng
Because the display controller in N2000/D2000 series can be VGA-compatible,
so let's register gma500 as a VGA client, despite the firmware may alter
the PCI class code of IGD on a multiple GPU co-exist configuration. But
this commit no crime, because VGAARB only cares about VGA
== Series Details ==
Series: fbc on any planes (rev2)
URL : https://patchwork.freedesktop.org/series/123180/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13593_full -> Patchwork_123180v2_full
Summary
---
**FAILURE**
== Series Details ==
Series: fbc on any planes (rev2)
URL : https://patchwork.freedesktop.org/series/123180/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13593 -> Patchwork_123180v2
Summary
---
**SUCCESS**
No reg
> -Original Message-
> From: Sebastian Wick
> Sent: Thursday, August 31, 2023 2:46 AM
> To: Shankar, Uma
> Cc: Harry Wentland ; intel-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; wayland-
> de...@lists.freedesktop.org; Ville Syrjala ;
> Pekka
> Paalanen ; Simon Ser ;
== Series Details ==
Series: fbc on any planes (rev2)
URL : https://patchwork.freedesktop.org/series/123180/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: u
== Series Details ==
Series: fbc on any planes (rev2)
URL : https://patchwork.freedesktop.org/series/123180/
State : warning
== Summary ==
Error: dim checkpatch failed
e9836d242d2b drm/i915/lnl: possibility to enable FBC on first three planes
-:74: WARNING:LONG_LINE: line length of 103 exceeds
> -Original Message-
> From: dri-devel On Behalf Of Pekka
> Paalanen
> Sent: Wednesday, August 30, 2023 6:30 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; dri-de...@lists.freedesktop.org; wayland-
> de...@lists.freedesktop.org
> Subject: Re: [R
> -Original Message-
> From: dri-devel On Behalf Of Pekka
> Paalanen
> Sent: Wednesday, August 30, 2023 5:59 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; dri-de...@lists.freedesktop.org; wayland-
> de...@lists.freedesktop.org
> Subject: Re: [RF
In LNL onwards, FBC can be associated to the first three planes.
FBC will be enabled on planes first come first served basis
until the userspace can select one of these FBC capable planes
explicitly.
v2:
- avoid fbc->state.plane check in intel_fbc_check_plane (Ville)
- simplify plane binding reg
For LNL onwards, FBC can be supported on planes with per
pixel alpha
Bspec: 69560
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915
FBC can be supported in first three planes in lnl
Vinod Govindapillai (2):
drm/i915/lnl: possibility to enable FBC on first three planes
drm/i915/lnl: FBC is supported with per pixel alpha
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
drivers/gpu/drm/i915/display/skl_univers
On Mon, Sep 04, 2023 at 06:48:25AM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:04:59AM +0300, Imre Deak wrote:
> > In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
> > range, while in DSC mode it can be set in 1/16 bpp steps to any value
> > up to the maximum pi
On Fri, 01 Sep 2023, Alex Deucher wrote:
> On Thu, Aug 24, 2023 at 9:46 AM Jani Nikula wrote:
>>
>> Checking edid->input & DRM_EDID_INPUT_DIGITAL is common enough to
>> deserve a helper that also lets us abstract the raw EDID a bit better.
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Alex D
On Mon, Sep 04, 2023 at 06:19:04AM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:04:56AM +0300, Imre Deak wrote:
> > Factor out helpers that DP / DP_MST encoders can use to compute the link
> > rate/lane count and bpp limits. A follow-up patch will call these to
> > recalculate the limit
On Mon, Sep 04, 2023 at 05:53:11AM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:05:04AM +0300, Imre Deak wrote:
> > For fractional bpp values passed to the function in a .4 fixed point
> > format, the fractional part is currently ignored due to scaling bpp too
> > early. Fix this by sca
On Fri, 2023-09-01 at 14:09 +0300, Ville Syrjälä wrote:
> On Fri, Sep 01, 2023 at 12:34:56PM +0300, Jouni Högander wrote:
> > Currently i915 dirtyfb ioctl is not taking dma fences into
> > account. This works with features like FBC, PSR, DRRS because our
> > gem
> > code is triggering flush again w
On Mon, 2023-09-04 at 08:40 +, Hogander, Jouni wrote:
> On Mon, 2023-09-04 at 07:25 +, Coelho, Luciano wrote:
> > Hi Jouni,
> >
> > On Fri, 2023-09-01 at 12:34 +0300, Jouni Högander wrote:
> > > We are planning to move flush performed from work queue. This
> > > means it is possible to hav
Thanks for the comment.
I will revise this patch, so the change is only removing POST overriding.
In addition, the patch for removing TRAIL was submitted as
https://patchwork.kernel.org/project/intel-gfx/patch/20211217100903.32599-1-william.ts...@intel.com/.
Can you help to review as well?
-O
On Mon, 2023-09-04 at 07:25 +, Coelho, Luciano wrote:
> Hi Jouni,
>
> On Fri, 2023-09-01 at 12:34 +0300, Jouni Högander wrote:
> > We are planning to move flush performed from work queue. This
> > means it is possible to have invalidate -> flip -> flush sequence.
> > Handle this by clearing po
On Sat, 2 Sep 2023 22:43:02 +0300
Dmitry Osipenko wrote:
> On 8/29/23 10:29, Boris Brezillon wrote:
> > On Tue, 29 Aug 2023 05:34:23 +0300
> > Dmitry Osipenko wrote:
> >
> >> On 8/28/23 13:12, Boris Brezillon wrote:
> >>> On Sun, 27 Aug 2023 20:54:43 +0300
> >>> Dmitry Osipenko wrote:
> >>
On Sat, 2 Sep 2023 21:15:39 +0300
Dmitry Osipenko wrote:
> On 8/28/23 14:16, Boris Brezillon wrote:
> > On Sun, 27 Aug 2023 20:54:27 +0300
> > Dmitry Osipenko wrote:
> >
> >> Freeing drm-shmem GEM right after creating it using
> >> drm_gem_shmem_prime_import_sg_table() frees SGT of the import
On Fri, 1 Sept 2023 at 21:00, Alex Deucher wrote:
>
> On Thu, Aug 31, 2023 at 6:01 PM Alex Hung wrote:
> >
> >
> >
> > On 2023-08-30 01:29, Jani Nikula wrote:
> > > On Tue, 29 Aug 2023, Alex Hung wrote:
> > >> On 2023-08-29 11:03, Jani Nikula wrote:
> > >>> On Tue, 29 Aug 2023, Jani Nikula wrot
On Sat, 2 Sep 2023 21:28:21 +0300
Dmitry Osipenko wrote:
> On 8/28/23 13:55, Boris Brezillon wrote:
> > On Sun, 27 Aug 2023 20:54:28 +0300
> > Dmitry Osipenko wrote:
> >
> >> Use separate flag for tracking page count bumped by shmem->sgt to avoid
> >> imbalanced page counter during of drm_gem
Hi Jouni,
On Fri, 2023-09-01 at 12:34 +0300, Jouni Högander wrote:
> We are planning to move flush performed from work queue. This
> means it is possible to have invalidate -> flip -> flush sequence.
> Handle this by clearing possible busy bits on flip.
>
> Signed-off-by: Ville Syrjälä
> Signed-
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev3)
URL : https://patchwork.freedesktop.org/series/122589/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/122589/revisions/3/mbox/ not
applied
Applying: drm/i9
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