> -Original Message-
> From: Intel-gfx On Behalf Of Maarten
> Lankhorst
> Sent: Thursday, November 9, 2023 9:05 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Use vblank worker to unpin old
> legacy
> cursor fb safely
>
> From: Ville Syrjälä
>
>
== Series Details ==
Series: drm/i915/display: Remove dead code around
intel_atomic_helper->free_list (rev6)
URL : https://patchwork.freedesktop.org/series/126250/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13882 -> Patchwork_126250v6
==
== Series Details ==
Series: drm/i915/display: Remove dead code around
intel_atomic_helper->free_list (rev6)
URL : https://patchwork.freedesktop.org/series/126250/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separa
== Series Details ==
Series: Test MTL DMC v2.19 (rev3)
URL : https://patchwork.freedesktop.org/series/126497/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13882 -> Patchwork_126497v3
Summary
---
**FAILURE**
Serio
> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, November 15, 2023 7:56 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp_mst: Fix PBN / MTP_TU size
> calculation for UHBR rates
>
> On Wed, Nov 15, 2023 at 03:41:
== Series Details ==
Series: drm/i915: Also check for VGA converter in eDP probe (rev2)
URL : https://patchwork.freedesktop.org/series/126404/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13882 -> Patchwork_126404v2
Summar
> -Original Message-
> From: Intel-gfx On Behalf Of Maarten
> Lankhorst
> Sent: Thursday, November 9, 2023 9:05 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/3] drm: Add drm_vblank_work_flush_all().
Drop the "."
Looks good to me.
Reviewed-by: Uma Shankar
>
NOT TO BE REVIEWED/MERGED
Hardcode path to DMC firmware for CI purposes only.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/in
The following changes since commit 44a9510c94ac0334931b6c89dd240ffe5bf1e5fa:
i915: Add GuC v70.13.1 for DG2, TGL, ADL-P and MTL (2023-10-13 11:34:26 -0700)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware
817619ea70a74598b4216dd25c0f49f61b09309b
for yo
The following changes since commit 44a9510c94ac0334931b6c89dd240ffe5bf1e5fa:
i915: Add GuC v70.13.1 for DG2, TGL, ADL-P and MTL (2023-10-13 11:34:26 -0700)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware
817619ea70a74598b4216dd25c0f49f61b09309b
for yo
== Series Details ==
Series: drm/i915/dg2: Wa_18028616096 now applies to all DG2
URL : https://patchwork.freedesktop.org/series/126488/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13881 -> Patchwork_126488v1
Summary
-
== Series Details ==
Series: Implement CMRR Support (rev3)
URL : https://patchwork.freedesktop.org/series/126443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13881 -> Patchwork_126443v3
Summary
---
**SUCCESS**
N
== Series Details ==
Series: Implement CMRR Support (rev3)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Implement CMRR Support (rev3)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
932e33a4e513 drm/i915: Define and compute Transcoder CMRR registers
-:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'na
== Series Details ==
Series: Prepare intel_fbdev for Xe (rev2)
URL : https://patchwork.freedesktop.org/series/126446/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13881 -> Patchwork_126446v2
Summary
---
**SUCCESS**
== Series Details ==
Series: Prepare intel_fbdev for Xe (rev2)
URL : https://patchwork.freedesktop.org/series/126446/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: w
== Series Details ==
Series: Prepare intel_fbdev for Xe (rev2)
URL : https://patchwork.freedesktop.org/series/126446/
State : warning
== Summary ==
Error: dim checkpatch failed
dd5a5c4a1d68 drm/i915/display: split i915 specific code from intel_fbdev
Traceback (most recent call last):
File "s
== Series Details ==
Series: ALSA: hda: i915: Alays handle -EPROBE_DEFER
URL : https://patchwork.freedesktop.org/series/126462/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13881 -> Patchwork_126462v1
Summary
---
**
== Series Details ==
Series: ALSA: hda: i915: Alays handle -EPROBE_DEFER
URL : https://patchwork.freedesktop.org/series/126462/
State : warning
== Summary ==
Error: dim checkpatch failed
769a176100d3 ALSA: hda: i915: Alays handle -EPROBE_DEFER
-:15: WARNING:BAD_REPORTED_BY_LINK: Reported-by: s
== Series Details ==
Series: drm/i915/gt: add missing new-line to GT_TRACE
URL : https://patchwork.freedesktop.org/series/126460/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13881 -> Patchwork_126460v1
Summary
---
== Series Details ==
Series: drm/i915/gsc: Mark internal GSC engine with reserved uabi class
URL : https://patchwork.freedesktop.org/series/126455/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13881 -> Patchwork_126455v1
S
== Series Details ==
Series: drm/i915/gsc: Mark internal GSC engine with reserved uabi class
URL : https://patchwork.freedesktop.org/series/126455/
State : warning
== Summary ==
Error: dim checkpatch failed
58cf74c214fb drm/i915/gsc: Mark internal GSC engine with reserved uabi class
-:76: WARN
== Series Details ==
Series: drm/i915/display: keep struct intel_display members sorted (rev2)
URL : https://patchwork.freedesktop.org/series/126413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13881 -> Patchwork_126413v2
On Mon, Nov 13, 2023 at 11:37:37AM +0200, Mika Kahola wrote:
> At least one TGL had regression when using u8 types
> for entry setup frames calculation. So, let's switch
> to use ints instead.
>
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
> 1 file ch
== Series Details ==
Series: drm/i915/display: keep struct intel_display members sorted (rev2)
URL : https://patchwork.freedesktop.org/series/126413/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: do not clean GT table on error path (rev3)
URL : https://patchwork.freedesktop.org/series/126385/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13881 -> Patchwork_126385v3
Summary
On Tue, Nov 14, 2023 at 03:41:41PM +0200, Jouni Högander wrote:
> After switching to directly using dma_fence instead of i915_sw_fence we
> have left some dead code around intel_atomic_helper->free_list. Remove that
> dead code.
>
> v2: Remove intel_atomic_state->freed as well
>
> Signed-off-by:
== Series Details ==
Series: drm/i915: do not clean GT table on error path (rev3)
URL : https://patchwork.freedesktop.org/series/126385/
State : warning
== Summary ==
Error: dim checkpatch failed
aa0259a7e573 drm/i915: do not clean GT table on error path
-:14: WARNING:COMMIT_LOG_LONG_LINE: Pre
On 11/9/2023 4:54 PM, john.c.harri...@intel.com wrote:
From: John Harrison
If a context is blocked, unblocked and subitted repeatedly in rapid
succession, the driver can end up trying to enable the context while
the previous enable request is still in flight. This can lead to much
confusion
On Wed, Nov 15, 2023 at 10:30:11PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 15, 2023 at 07:13:26PM +0530, Mitul Golani wrote:
> > Compute Fixed Average Vtotal/CMRR with resepect to
> > userspace VRR enablement. Also calculate required
> > parameters in case of CMRR is enabled. During
> > intel_vr
On Tue, Nov 14, 2023 at 06:40:26PM +, Winkler, Tomas wrote:
>
>
> > -Original Message-
> > From: Teres Alexis, Alan Previn
> > Sent: Tuesday, November 14, 2023 5:32 PM
> > To: ville.syrj...@linux.intel.com; Winkler, Tomas
> > Cc: gre...@linuxfoundation.org; Usyskin, Alexander
> > ;
On Wed, Nov 15, 2023 at 01:36:25PM +0100, Maarten Lankhorst wrote:
> It turns out that even if the comment says that the driver can load
> fine, it's not really the case and no codecs are detected.
> Specifically for -EPROBE_DEFER, always fail the probe.
>
> This fixes a regression when HDA-intel
On Wed, Nov 15, 2023 at 07:13:26PM +0530, Mitul Golani wrote:
> Compute Fixed Average Vtotal/CMRR with resepect to
> userspace VRR enablement. Also calculate required
> parameters in case of CMRR is enabled. During
> intel_vrr_compute_config, CMRR is getting enabled
> based on userspace has enable
Hi Vinay,
> -Original Message-
> From: dri-devel On Behalf Of
> Belgaumkar, Vinay
> Sent: Thursday, November 9, 2023 5:02 PM
> To: Ville Syrjälä
> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Read a shadowed mmio regist
On 11/15/2023 3:02 AM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
The GSC CS is not exposed to the user, so we skipped assigning a uabi
class number for it. However, the trace logs use the uabi class and
instance to identify the engine, so leaving uabi class unset makes the
GSC CS show up as
The workaround database was just updated to extend this workaround to
DG2-G11 (whereas previously it applied only to G10 and G12).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm
On Tue, Nov 14, 2023 at 09:50:37PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Fix fractional bpp handling in intel_link_bw_reduce_bpp()
> URL : https://patchwork.freedesktop.org/series/126403/
> State : success
I didn't receive any CI shards results and I can't see the
Hi Tvrtko,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-intel/for-linux-next-fixes]
[also build test WARNING on drm-tip/drm-tip drm/drm-next
drm-exynos/exynos-drm-next drm-misc/drm-misc-next linus/master v6.7-rc1
next-20231115]
[cannot apply to drm
*/
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
---
base-commit: 1489bab52c281a869295414031a56506a375b036
change-id: 20231115-eols-20f9f52cf338
Best regards,
On 11/15/2023 11:54 AM, Andrzej Hajda wrote:
The only task of intel_gt_release_all is to zero gt table. Calling
it on error path prevents intel_gt_driver_late_release_all (called from
i915_driver_late_release) to cleanup GTs, causing leakage.
After i915_driver_late_release GT array is not used
On Wed, 2023-11-15 at 13:31 +, Tvrtko Ursulin wrote:
> On 14/11/2023 15:31, Teres Alexis, Alan Previn wrote:
> > On Tue, 2023-11-14 at 16:00 +0200, Ville Syrjälä wrote:
> > > On Wed, Oct 11, 2023 at 02:01:56PM +0300, Tomas Winkler wrote:
> > >
>
> Regardless of the mei_pxp_send_message being
Add CMRR/Fixed Average Vtotal mode enable and disable
functions based on change in VRR mode of operation.
When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal
mode is disabled and vice versa. With this commit setting
the stage for subsequent CMRR enablement.
--v2:
- Check pipe active state i
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Adaptive Sync Vtotal
mode (Legacy VRR) or not.
--v2:
- Update is_cmrr
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based o
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame dro
On Wed, Nov 15, 2023 at 03:41:08PM +0200, Murthy, Arun R wrote:
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of Imre
> > Deak
> > Sent: Wednesday, November 15, 2023 7:08 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp_mst: Fix P
On Wed, 15 Nov 2023, Mitul Golani wrote:
> Add CMRR/Fixed Average Vtotal mode enable and disable
> functions based on change in VRR mode of operation.
> When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal
> mode is disabled and vice versa. With this commit setting
> the stage for subsequent
Thanks @Ville Syrjälä
Addressed review comment.
Regards,
Mitul
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, November 15, 2023 12:28 PM
> To: Golani, Mitulkumar Ajitkumar
> Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville
> Subject: Re: [Intel-gfx] [RFC 3/3] drm/i91
Thanks @Jani Nikula
Addressed all review comments.
Regards,
Mitul
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, November 15, 2023 2:25 PM
> To: Golani, Mitulkumar Ajitkumar ;
> intel-gfx@lists.freedesktop.org
> Cc: Syrjala, Ville
> Subject: Re: [Intel-gfx] [RFC 2/3] drm/i
Thanks @Jani Nikula
Addressed all review comments.
Regards,
Mitul
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, November 15, 2023 2:17 PM
> To: Golani, Mitulkumar Ajitkumar ;
> intel-gfx@lists.freedesktop.org
> Cc: Syrjala, Ville
> Subject: Re: [Intel-gfx] [RFC 1/3] drm/i
Thanks @Jani Nikula
Addressed all review comments.
Regards,
Mitul
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, November 15, 2023 2:44 PM
> To: Golani, Mitulkumar Ajitkumar ;
> intel-gfx@lists.freedesktop.org
> Cc: Syrjala, Ville
> Subject: Re: [Intel-gfx] [RFC 3/3] drm/i
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Adaptive Sync Vtotal
mode (Legacy VRR) or not.
Signed-off-by: Mitul G
Add CMRR/Fixed Average Vtotal mode enable and disable
functions based on change in VRR mode of operation.
When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal
mode is disabled and vice versa. With this commit setting
the stage for subsequent CMRR enablement.
Signed-off-by: Mitul Golani
---
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame dro
On Tue, Nov 14, 2023 at 03:07:52PM +0200, Imre Deak wrote:
> On Tue, Nov 14, 2023 at 11:00:49AM +0200, Jani Nikula wrote:
> > On Mon, 13 Nov 2023, Imre Deak wrote:
> > > Apply the correct BW allocation overhead and channel coding efficiency
> > > on UHBR link rates, similarly to DP1.4 link rates.
> -Original Message-
> From: Intel-gfx On Behalf Of Imre
> Deak
> Sent: Wednesday, November 15, 2023 7:08 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp_mst: Fix PBN / MTP_TU size
> calculation for UHBR rates
>
> On Mon, Nov 13, 2023 at 10:1
On Mon, Nov 13, 2023 at 10:11:09PM +0200, Imre Deak wrote:
> Atm the allocated MST PBN value is calculated from the TU size (number
> of allocated MTP slots) as
>
> PBN = TU * pbn_div
>
> pbn_div being the link BW for each MTP slot. For DP 1.4 link rates this
> worked, as pbn_div there is gurar
On 14/11/2023 15:31, Teres Alexis, Alan Previn wrote:
On Tue, 2023-11-14 at 16:00 +0200, Ville Syrjälä wrote:
On Wed, Oct 11, 2023 at 02:01:56PM +0300, Tomas Winkler wrote:
From: Alexander Usyskin
Disable and enable mei-pxp client on errors to clean the internal state.
This broke i915 on
> -Original Message-
> From: Deak, Imre
> Sent: Tuesday, November 14, 2023 1:13 PM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915/dp: Fix UHBR link M/N values
>
> On Tue, Nov 14, 2023 at 05:29:35AM +0200, Murthy, Arun R wrote:
Am 02.11.23 um 14:08 schrieb Thomas Zimmermann:
Do not acquire a reference on the module that provides a client's
callback functions in drm_client_init(). The additional reference
prevents the user from unloading the callback functions' module and
thus creating dangling pointers.
This is only
== Series Details ==
Series: Prepare intel_fbdev for Xe
URL : https://patchwork.freedesktop.org/series/126446/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13877 -> Patchwork_126446v1
Summary
---
**FAILURE**
Seri
On Wed, 15 Nov 2023 13:36:25 +0100,
Maarten Lankhorst wrote:
>
> It turns out that even if the comment says that the driver can load
> fine, it's not really the case and no codecs are detected.
> Specifically for -EPROBE_DEFER, always fail the probe.
>
> This fixes a regression when HDA-intel is
", str_yes_no(force));
>
> /* Use a raw wakeref to avoid calling intel_display_power_get early */
> wakeref = intel_runtime_pm_get(gt->uncore->rpm);
>
> ---
> base-commit: 1489bab52c281a869295414031a56506a375b036
> change-id: 20231115-eols-20f9f52cf338
>
> Best regards,
>
It turns out that even if the comment says that the driver can load
fine, it's not really the case and no codecs are detected.
Specifically for -EPROBE_DEFER, always fail the probe.
This fixes a regression when HDA-intel is loaded before i915.
Reported-by: Ville Syrjälä
Signed-off-by: Maarten La
On 25.10.2023 23:39, Andrzej Hajda wrote:
After spinlock release object can be modified/freed by concurrent thread.
Using it in such case is error prone, even for printing object state.
To avoid such situation local copy of the object is created if necessary.
Sample buggy scenario:
1. Thread tri
== Series Details ==
Series: series starting with [1/3] drm: Add drm_vblank_work_flush_all().
URL : https://patchwork.freedesktop.org/series/126202/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13856 -> Patchwork_126202v1
== Series Details ==
Series: Prepare intel_fbdev for Xe
URL : https://patchwork.freedesktop.org/series/126446/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning:
== Series Details ==
Series: Prepare intel_fbdev for Xe
URL : https://patchwork.freedesktop.org/series/126446/
State : warning
== Summary ==
Error: dim checkpatch failed
9df37f0b7675 drm/i915/display: split i915 specific code from intel_fbdev
Traceback (most recent call last):
File "scripts/
>rpm);
---
base-commit: 1489bab52c281a869295414031a56506a375b036
change-id: 20231115-eols-20f9f52cf338
Best regards,
--
Andrzej Hajda
== Series Details ==
Series: drm/i915/display: Remove dead code around
intel_atomic_helper->free_list (rev5)
URL : https://patchwork.freedesktop.org/series/126250/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13877 -> Patchwork_126250v5
==
== Series Details ==
Series: drm/i915/display: Remove dead code around
intel_atomic_helper->free_list (rev5)
URL : https://patchwork.freedesktop.org/series/126250/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separa
On 15/11/2023 10:54, Andrzej Hajda wrote:
The only task of intel_gt_release_all is to zero gt table. Calling
it on error path prevents intel_gt_driver_late_release_all (called from
i915_driver_late_release) to cleanup GTs, causing leakage.
After i915_driver_late_release GT array is not used any
From: Tvrtko Ursulin
The GSC CS is not exposed to the user, so we skipped assigning a uabi
class number for it. However, the trace logs use the uabi class and
instance to identify the engine, so leaving uabi class unset makes the
GSC CS show up as the RCS in those logs.
Given that the engine is
The only task of intel_gt_release_all is to zero gt table. Calling
it on error path prevents intel_gt_driver_late_release_all (called from
i915_driver_late_release) to cleanup GTs, causing leakage.
After i915_driver_late_release GT array is not used anymore so
it does not need cleaning at all.
Sam
== Series Details ==
Series: Implement CMRR Support
URL : https://patchwork.freedesktop.org/series/126443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13876 -> Patchwork_126443v1
Summary
---
**SUCCESS**
No regre
On Wed, 15 Nov 2023, Mitul Golani wrote:
> Compute Fixed Average Vtotal/CMRR with resepect to
> userspace VRR enablement. Also calculate required
> parameters in case of CMRR is enabled. During
> intel_vrr_compute_config, CMRR is getting enabled
> based on userspace has enabled Adaptive Sync Vtot
We are preparing for Xe driver. I915 and Xe object implementation are
differing. Do not use i915_gem_object->base directly. Instead use
intel_bo_to_drm_bo.
Signed-off-by: Jouni Högander
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 4 ++--
1 file changed, 2
Intel_fbdev buffer allocation and it's backing object handling differs
a lot between i915 and Xe. This patch set is splitting i915 specific
code into it's own source file. Similar source files will be
introduced for Xe as well.
Also use intel_bo_to_drm_bo instead of directly referring
i915_gem_obj
Split out code from intel_fbdev that can not be share between i915 and
xe. Create new i915 specific source/header file intel_fbdev_fb.[ch] which
contains this code.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/display/intel_fbdev.
== Series Details ==
Series: Implement CMRR Support
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Implement CMRR Support
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
235ee232c969 drm/i915: Define and compute Transcoder CMRR registers
-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - p
On 14/11/2023 09:48, Andrzej Hajda wrote:
The only task of intel_gt_release_all is to zero gt table. Calling
it on error path prevents intel_gt_driver_late_release_all (called from
i915_driver_late_release) to cleanup GTs, causing leakage.
After i915_driver_late_release GT array is not used any
On 11/9/2023 12:19 PM, Kandpal, Suraj wrote:
-Original Message-
From: Intel-gfx On Behalf Of Ankit
Nautiyal
Sent: Tuesday, November 7, 2023 9:48 AM
To: intel-gfx@lists.freedesktop.org
Cc: Nikula, Jani
Subject: [Intel-gfx] [PATCH 4/4] drm/i915/dp: Ignore max_requested_bpc if its
too
On Wed, 15 Nov 2023, Mitul Golani wrote:
> Add CMRR/Fixed Average Vtotal mode enable and disable
> functions based on change in VRR mode of operation.
> When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal
> mode is disabled and vice versa. With this commit setting
> the stage for subsequent
On Wed, 15 Nov 2023, Mitul Golani wrote:
> Add register definitions for Transcoder Fixed Average
> Vtotal mode/CMRR function, with the necessary bitfields.
> Compute these registers when CMRR is enabled, extending
> Adaptive refresh rate capabilities.
>
> Signed-off-by: Mitul Golani
> ---
> driv
On Wed, 15 Nov 2023, Ville Syrjälä wrote:
> After further thought it won't work because we do stuff like
> is_enabling(...) || other_conditions
>
> So we need the crtc_state->hw.active check to catch both sides
> of the OR.
Ah, true.
--
Jani Nikula, Intel
On Tue, Nov 14, 2023 at 10:57:29AM +0200, Ville Syrjälä wrote:
> On Mon, Nov 13, 2023 at 05:49:32PM +0200, Jani Nikula wrote:
> > On Mon, 06 Nov 2023, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Relocate the audio enable/disable from the full modeset hooks into
> > > the common pre
Hi,
On Tue, 14 Nov 2023, Takashi Iwai wrote:
> On Tue, 14 Nov 2023 14:31:25 +0100, Saarinen, Jani wrote:
> > Was this series tested on CI ever as Ville saying no? How this got merged?
>
> Hm, I somehow believed that patches have been tested by intel people,
> as they came from intel. (Also th
== Series Details ==
Series: drm/i915/dsb: DSB code refactoring (rev7)
URL : https://patchwork.freedesktop.org/series/124141/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13876 -> Patchwork_124141v7
Summary
---
**SU
== Series Details ==
Series: drm/i915/dsb: DSB code refactoring (rev7)
URL : https://patchwork.freedesktop.org/series/124141/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13876 -> Patchwork_124141v7
Summary
---
**SU
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