== Series Details ==
Series: Revert "debugfs: annotate debugfs handlers vs. removal with lockdep"
(rev2)
URL : https://patchwork.freedesktop.org/series/127359/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13983 -> Patchwork_127359v2
== Series Details ==
Series: Revert "debugfs: annotate debugfs handlers vs. removal with lockdep"
(rev2)
URL : https://patchwork.freedesktop.org/series/127359/
State : warning
== Summary ==
Error: dim checkpatch failed
75765522921d Revert "debugfs: annotate debugfs handlers vs. removal with
From: Johannes Berg
This reverts commit f4acfcd4deb1 ("debugfs: annotate debugfs handlers
vs. removal with lockdep"), it appears to have false positives and
really shouldn't have been in the -rc series with the fixes anyway.
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 0f5f12ac05f36f117e793656c3f560625e927f1b Add linux-next specific
files for 20231205
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202312051416.yirwcymp-...@intel.com
https
== Series Details ==
Series: drm/i915: Fix remapped stride with CCS on ADL+
URL : https://patchwork.freedesktop.org/series/127375/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13983_full -> Patchwork_127375v1_full
Summary
On 12/1/2023 4:21 AM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Commit 503579448db9 ("drm/i915/gsc: Mark internal GSC engine with reserved uabi
class")
made the GSC0 engine not have a valid uabi class and so broke the engine
reset counting, which in turn was made class based in
== Series Details ==
Series: Implement CMRR Support (rev6)
URL : https://patchwork.freedesktop.org/series/126443/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13983 -> Patchwork_126443v6
Summary
---
**FAILURE**
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Thursday, September 28, 2023 8:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Drop irqsave/restore for
> flip_done_handler()
>
> From: Ville Syrjälä
>
> Since
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjälä
> Sent: Tuesday, November 21, 2023 7:21 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Stop accessing crtc->state from
> the flip done irq
>
> On Thu, Sep 28, 2023 at
== Series Details ==
Series: Implement CMRR Support (rev6)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Implement CMRR Support (rev6)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
9e724d645676 drm/i915: Define and compute Transcoder CMRR registers
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse
== Series Details ==
Series: drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
(rev2)
URL : https://patchwork.freedesktop.org/series/127194/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13983 -> Patchwork_127194v2
== Series Details ==
Series: drm/i915: Fix remapped stride with CCS on ADL+
URL : https://patchwork.freedesktop.org/series/127375/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13983 -> Patchwork_127375v1
Summary
---
On Tue, Dec 05, 2023 at 02:41:05PM +0530, Haridhar Kalvala wrote:
> Enable Force Dispatch Ends Collection for DG2.
>
> BSpec: 46001
>
> Signed-off-by: Haridhar Kalvala
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> 2 files
== Series Details ==
Series: drm/i915/gem: Atomically invalidate userptr on mmu-notifier (rev5)
URL : https://patchwork.freedesktop.org/series/126998/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13983 -> Patchwork_126998v5
On 12/5/2023 02:39, Nirmoy Das wrote:
Hi John,
On 12/5/2023 10:10 AM, John Harrison wrote:
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Convert the log
== Series Details ==
Series: drm/i915/gem: Atomically invalidate userptr on mmu-notifier (rev5)
URL : https://patchwork.freedesktop.org/series/126998/
State : warning
== Summary ==
Error: dim checkpatch failed
6cb73f2c84ee drm/i915/gem: Atomically invalidate userptr on mmu-notifier
-:117:
== Series Details ==
Series: drm/i915/gem: Atomically invalidate userptr on mmu-notifier (rev5)
URL : https://patchwork.freedesktop.org/series/126998/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Add CMRR/Fixed Average Vtotal mode enable and disable
functions based on change in VRR mode of operation.
When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal
mode is disabled and vice versa. With this commit setting
the stage for subsequent CMRR enablement.
--v2:
- Check pipe active state
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Adaptive Sync Vtotal
mode (Legacy VRR) or not.
--v2:
- Update
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame
Hi Mika,
> -Original Message-
> From: Kahola, Mika
> Sent: Tuesday, December 5, 2023 12:28 AM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 2/3] drm/i915/display: Convert link bitrate to
> corresponding PLL clock
>
> > -Original
The eDP 1.5 spec adds a clarification for eDP 1.4x:
> For eDP v1.4x, if the Source device chooses the Main-Link rate by way
> of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as
== Series Details ==
Series: series starting with [1/3] drm/i915: use intel_connector in
intel_connector_debugfs_add()
URL : https://patchwork.freedesktop.org/series/127362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13982 -> Patchwork_127362v1
From: Ville Syrjälä
On ADL+ the hardware automagically calculates the CCS AUX surface
stride from the main surface stride, so when remapping we can't
really play a lot of tricks with the main surface stride, or else
the AUX surface stride would get miscalculated and no longer
match the actual
== Series Details ==
Series: Revert "debugfs: annotate debugfs handlers vs. removal with lockdep"
URL : https://patchwork.freedesktop.org/series/127359/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13982 -> Patchwork_127359v1
== Series Details ==
Series: Revert "debugfs: annotate debugfs handlers vs. removal with lockdep"
URL : https://patchwork.freedesktop.org/series/127359/
State : warning
== Summary ==
Error: dim checkpatch failed
de1bce6845d1 Revert "debugfs: annotate debugfs handlers vs. removal with
== Series Details ==
Series: drm/i915/selftests: wait for active idle event in
i915_active_unlock_wait (rev3)
URL : https://patchwork.freedesktop.org/series/126978/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13982 -> Patchwork_126978v3
On Tue, Dec 05, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> Prefer struct intel_connector over struct drm_connector.
>
> Signed-off-by: Jani Nikula
Series is
Reviewed-by: Ville Syrjälä
--
Ville Syrjälä
Intel
On Tue, Dec 05, 2023 at 02:50:57PM +0200, Jani Nikula wrote:
> On Tue, 05 Dec 2023, "Shankar, Uma" wrote:
> >> Yeah, writing 0 is done with an intention to disable it but that’s not the
> >> way to
> >> have this option disabled. Infact there is no reason to write to it for
> >> DP1.4+ if sink
On Mon, Dec 04, 2023 at 05:46:28PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjälä (2023-12-04 17:05:46-03:00)
> >On Fri, Dec 01, 2023 at 05:13:38PM -0300, Gustavo Sousa wrote:
> >> Quoting Ville Syrjala (2023-11-28 08:51:33-03:00)
> >> >From: Ville Syrjälä
> >> >
> >> >Currently we have a
On Thu, 30 Nov 2023 at 11:18, Maxime Ripard wrote:
>
> Hi,
>
> On Thu, Nov 30, 2023 at 10:52:17AM +0200, Jani Nikula wrote:
> > On Wed, 29 Nov 2023, Hamza Mahfooz wrote:
> > > Cc: Nathan Chancellor
> > >
> > > On 11/29/23 13:12, Jani Nikula wrote:
> > >> At least the i915 and amd drivers enable
== Series Details ==
Series: drm/i915/rpm: add rpm_to_i915() helper around container_of()
URL : https://patchwork.freedesktop.org/series/127353/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13981 -> Patchwork_127353v1
Hi,
I'm agree with you.
On 2023/11/30 02:12, Jani Nikula wrote:
At least the i915 and amd drivers enable a bunch more compiler warnings
than the kernel defaults.
Extend the W=1 warnings to the entire drm subsystem by default. Use the
copy-pasted warnings from scripts/Makefile.extrawarn with
I tried a bit if I can break something with ccs but it seemed everything
work as expected with this fix.
Reviewed-by: Juha-Pekka Heikkila
On 4.12.2023 22.24, Ville Syrjala wrote:
From: Ville Syrjälä
plane_view_scanout_stride() currently assumes that we had to pad the
mapping stride with
On Mon, 2023-12-04 at 16:09 +0200, Kai Vehmanen wrote:
> Hi,
>
> I'll send this first to intel-gfx to verify the i915 CI results. If
> all ok, I'll send this series to ALSA/sound upstream.
>
> This seriers is to address kms_hdmi_inject@inject-audio failures
> reported in:
>
== Series Details ==
Series: drm/i915: Add Wa_14019877138
URL : https://patchwork.freedesktop.org/series/127346/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13981 -> Patchwork_127346v1
Summary
---
**FAILURE**
On Tue, 05 Dec 2023, Chaitanya Kumar Borah
wrote:
> From: Johannes Berg
>
> This reverts commit f4acfcd4deb1 ("debugfs: annotate debugfs handlers
> vs. removal with lockdep"), it appears to have false positives and
> really shouldn't have been in the -rc series with the fixes anyway.
>
>
Octal permissions are preferred over the symbolics ones.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
Prefer struct intel_connector over struct drm_connector, and unify the
declarations in the fops.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_debugfs.c | 134 +-
1 file changed, 66 insertions(+), 68 deletions(-)
diff --git
Prefer struct intel_connector over struct drm_connector.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_debugfs.c | 53 +--
1 file changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
On Thu, 30 Nov 2023, Khaled Almahallawy wrote:
> Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.
A CTS connected to an older platform leads to invalid values being
written to the registers in question. In some cases probably also
invalid registers on the platform.
I
On Tue, Dec 05, 2023 at 02:15:45PM +0200, Jani Nikula wrote:
> Reduce the duplication.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 24 ++--
> 1 file changed, 10 insertions(+), 14 deletions(-)
>
> diff --git
From: Johannes Berg
This reverts commit f4acfcd4deb1 ("debugfs: annotate debugfs handlers
vs. removal with lockdep"), it appears to have false positives and
really shouldn't have been in the -rc series with the fixes anyway.
topic/core-for-CI note: cherry-picked from
On Thu, 30 Nov 2023, Khaled Almahallawy wrote:
> Starting from DP2.0 specs, DPCD 248h is renamed
> LINK_QUAL_PATTERN_SELECT and it has the same values of registers
> DPCD 10Bh-10Eh.
> Use the PHY pattern names defined for DPCD 10Bh-10Eh in order to add
> CP2520 Pattern 3 (TPS4) phy pattern
== Series Details ==
Series: drm/i915/gt: Convert reset prepare failure log to trace
URL : https://patchwork.freedesktop.org/series/127344/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13981 -> Patchwork_127344v1
Summary
After i915_active_unlock_wait i915_active can be still non-idle due
to barrier async handling in signal_irq_work. As a result one can observe
following errors:
bcs0: heartbeat pulse did not flush idle tasks
*ERROR* pulse active pulse_active [i915]:pulse_retire [i915]
*ERROR* pulsecount: 0
On Tue, 05 Dec 2023, "Shankar, Uma" wrote:
>> Yeah, writing 0 is done with an intention to disable it but that’s not the
>> way to
>> have this option disabled. Infact there is no reason to write to it for
>> DP1.4+ if sink
>> is compliant.
>
> The change looks ok and aligns with spec, its
>
Reduce the duplication.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, December 4, 2023 10:23 PM
> To: Nikula, Jani ; Ville Syrjälä
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET
> when using rate select
>
>
>
> >
Hi,
> -Original Message-
> From: Saarinen, Jani
> Sent: Monday, December 4, 2023 4:26 PM
> To: Kai Vehmanen ; intel-
> g...@lists.freedesktop.org; Nikula, Jani
> Subject: RE: [Intel-gfx] [PATCH 0/3] ALSA: hda/hdmi: add SKL/KBL connect-all
> quirks
>
> Hi,
>
> > -Original
On 05/12/2023 10:44, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 11:05 AM, Tvrtko Ursulin wrote:
On 05/12/2023 08:50, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
Hi Tvrtko,
On 12/5/2023 11:05 AM, Tvrtko Ursulin wrote:
On 05/12/2023 08:50, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some
Hi John,
On 12/5/2023 10:10 AM, John Harrison wrote:
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Convert the log to a trace log for debugging without
On Mon, Dec 04, 2023 at 10:24:43PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> plane_view_scanout_stride() currently assumes that we had to pad the
> mapping stride with dummy pages in order to align it. But that is not
> the case if the original fb stride exceeds the aligned stride
On 05/12/2023 08:50, Nirmoy Das wrote:
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the
On Mon, 2023-12-04 at 14:49 +0100, Maarten Lankhorst wrote:
> Works better for xe like that. obj is no longer const.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 6 --
> 1 file changed, 4 insertions(+), 2
Enable Force Dispatch Ends Collection for DG2.
BSpec: 46001
Signed-off-by: Haridhar Kalvala
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
On 12/5/2023 00:52, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Convert the log to a trace log for debugging without triggering
unnecessary concerns in CI or for end-users
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Convert the log to a trace log for debugging without triggering
unnecessary concerns in CI or for end-users during non-fatal scenarios.
v2: Improve
Hi Tvrtko,
On 12/5/2023 9:34 AM, Tvrtko Ursulin wrote:
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare()
On 01/12/2023 15:44, Nirmoy Das wrote:
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare() decide if a
failure in gen8_engine_reset_prepare is an error
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Tuesday, December 5, 2023 3:36 AM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 2/3] drm/i915/display: Convert link bitrate
> to corresponding PLL clock
>
> Hi Mika,
>
> > -Original
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