Document nested struct members with full names as described in
Documentation/doc-guide/kernel-doc.rst.
i915_perf_types.h:341: warning: Excess struct member 'ptr_lock' description in
'i915_perf_stream'
i915_perf_types.h:341: warning: Excess struct member 'head' description in
'i915_perf_stream'
Document nested struct members with full names as described in
Documentation/doc-guide/kernel-doc.rst.
intel_guc.h:305: warning: Excess struct member 'lock' description in 'intel_guc'
intel_guc.h:305: warning: Excess struct member 'guc_ids' description in
'intel_guc'
intel_guc.h:305: warning:
Document nested struct members with full names as described in
Documentation/doc-guide/kernel-doc.rst.
i915_gem_context_types.h:420: warning: Excess struct member 'lock' description
in 'i915_gem_context'
Signed-off-by: Randy Dunlap
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc:
Document nested struct members with full names as described in
Documentation/doc-guide/kernel-doc.rst.
intel_gsc.h:34: warning: Excess struct member 'gem_obj' description in
'intel_gsc'
Also add missing field member descriptions.
Signed-off-by: Randy Dunlap
Cc: Jani Nikula
Cc: Joonas
From: John Harrison
Use the new w/a KLV support to enable a MTL w/a. Note, this w/a is a
super-set of Wa_16019325821, so requires turning that one as well as
setting the new flag for Wa_14019159160 itself.
Signed-off-by: John Harrison
Reviewed-by: Vinay Belgaumkar
---
From: John Harrison
Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.
Signed-off-by: John Harrison
Reviewed-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 19
From: John Harrison
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
Signed-off-by: John Harrison
Reviewed-by: Vinay Belgaumkar
---
.../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
From: John Harrison
Enable Wa_14019159160 and Wa_16019325821 for MTL
RCS/CCS workarounds for MTL.
v2: Fix bug in WA KLV implementation (offset not being reset to start
of list). Add better comment to prep patch about how KLVs can be added.
Add a module parameter override and disable the w/a
On Wed, Dec 20, 2023 at 12:39:51PM +, Shuicheng Lin wrote:
> Some of the wa registers are MCR register, and EU_PERF_CNTL registers
> are MCR register.
> MCR register needs extra process for read/write.
> As normal MMIO register also could work with the MCR register process,
> change all wa
Hi John,
On Tue, Dec 19, 2023 at 11:59:57AM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Avoid the following lockdep complaint:
> <4> [298.856498] ==
> <4> [298.856500] WARNING: possible circular locking dependency
On Wed, 2023-12-13 at 16:23 -0500, Vivi, Rodrigo wrote:
> On Tue, Dec 12, 2023 at 08:57:16AM -0800, Alan Previn wrote:
> > If we are at the end of suspend or very early in resume
> > its possible an async fence signal (via rcu_call) is triggered
> > to free_engines which could lead us to the
Hi Jani,
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, December 20, 2023 1:38 AM
> To: Ville Syrjälä ; Sripada, Radhakrishna
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915: Piggyback opregion vbt to store vbt read from
> flash/oprom
>
> On Wed, 20
This patch introduces phy version of intel_encoder_port_data_lookup.
Port based variant is dependent on vbt child data extraction and
conversion to port data to be used further. Port data is not immediately
available and is difficult to be determined from phy info.
Signed-off-by: Radhakrishna
Vbt structures will be used during mode config cleanup. Move
the vbt structures cleanup to later time to accommodate cleaner
mode config removal.
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_display_driver.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
We are relying on end-less if-else ladders for a type-c phy
capabilities check. Though it made sense when platforms supported
legacy type-c support, modern platforms rely on the information
passed by vbt. This cleanup restricts the if-else ladder to the
platforms supporting legacy type-c phys and
intel_bios_encoder_data_lookup takes enum port as an argument. A variant
based out of phy based lookup is required to be used out of vbt code which
will be introduced in a later patch. Hence indicate the current variant as
intel_bios_encoder_port_data_lookup.
Signed-off-by: Radhakrishna Sripada
Starting MTL and DG2 if a phy is not marked as USB-typeC or TBT capable
by vbt we should not consider it as a Legacy type-c phy.
The concept of Legacy-tc existed in platforms from Icelake to Alder lake
where an external FIA can be routed to one of the phy's thus making the phy
tc capable without
On Wed, Dec 20, 2023 at 12:22:33AM +0530, Haridhar Kalvala wrote:
> Correct the implementation trying to detect MTL PCH with
> the MTL fake PCH id.
>
> On MTL, both the North Display (NDE) and South Display (SDE) functionality
> reside on the same die (the SoC die in this case), unlike many past
On Wed, Dec 13, 2023 at 04:07:26PM -0800, Matt Roper wrote:
> On Mon, Dec 04, 2023 at 11:13:52AM -0300, Gustavo Sousa wrote:
> > Quoting Gustavo Sousa (2023-12-04 11:04:20-03:00)
> > >Quoting Matt Roper (2023-12-01 20:07:48-03:00)
> > >>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä
On Tue, Dec 19, 2023 at 04:57:10AM +, Patchwork wrote:
Patch Details
Series: drm/i915/perf: Update handling of MMIO triggered reports
URL: [1]https://patchwork.freedesktop.org/series/127946/
State: failure
Details:
On Wed, Dec 20, 2023 at 11:45:44AM +, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Shankar, Uma
> > Sent: Wednesday, December 20, 2023 5:11 PM
> > To: Ville Syrjala ;
> > intel-gfx@lists.freedesktop.org
> > Subject: RE: [PATCH 8/9] drm/i915: Perform vblank evasion around
Some of the wa registers are MCR register, and EU_PERF_CNTL registers
are MCR register.
MCR register needs extra process for read/write.
As normal MMIO register also could work with the MCR register process,
change all wa registers to MCR type for code simplicity.
Signed-off-by: Shuicheng Lin
Ville Syrjala writes:
> From: Ville Syrjälä
>
> Sprinkle some extra WARNs around so that we might catch
> premature framebuffer destruction more readily.
>
> Signed-off-by: Ville Syrjälä
> ---
Acked-by: Javier Martinez Canillas
--
Best regards,
Javier Martinez Canillas
Core Platforms
Red
Ville Syrjala writes:
Hello Ville,
> From: Ville Syrjälä
>
> If we get a deadlock after the fb lookup in drm_mode_page_flip_ioctl()
> we proceed to unref the fb and then retry the whole thing from the top.
> But we forget to reset the fb pointer back to NULL, and so if we then
> get another
> -Original Message-
> From: Roper, Matthew D
> Sent: Wednesday, December 20, 2023 1:49 AM
> To: Lin, Shuicheng
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/guc: Add MCR type check for wa registers
>
> On Mon, Dec 18, 2023 at 11:46:44AM +, Shuicheng Lin
> -Original Message-
> From: Shankar, Uma
> Sent: Wednesday, December 20, 2023 5:11 PM
> To: Ville Syrjala ;
> intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 8/9] drm/i915: Perform vblank evasion around legacy cursor
> updates
>
>
>
> > -Original Message-
> > From:
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, December 13, 2023 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 8/9] drm/i915: Perform vblank evasion around legacy cursor
> updates
>
> From: Ville Syrjälä
>
> Our legacy cursor
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, December 13, 2023 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 7/9] drm/i915: Move intel_vblank_evade() & co. into
> intel_vblank.c
>
> From: Ville Syrjälä
>
> intel_vblank.c
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, December 13, 2023 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 6/9] drm/i915: Move the min/max scanline sanity check into
> intel_vblank_evade()
>
> From: Ville Syrjälä
>
> There
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, December 13, 2023 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 5/9] drm/i915: Extract intel_vblank_evade()
>
> From: Ville Syrjälä
>
> Pull the core vblank evasion loop into its
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, December 13, 2023 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 4/9] drm/i915: Include need_vlv_dsi_wa in
> intel_vblank_evade_ctx
>
> From: Ville Syrjälä
>
> Pull the
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, December 13, 2023 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 3/9] drm/i915: Introduce struct intel_vblank_evade_ctx
>
> From: Ville Syrjälä
>
> Collect the information needed
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, December 13, 2023 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 2/9] drm/i915: Reorder drm_vblank_put() vs. need_vlv_dsi_wa
>
> From: Ville Syrjälä
>
> Drop the vblank reference
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, December 13, 2023 3:55 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 1/9] drm/i915: Decouple intel_crtc_vblank_evade_scanlines()
> from atomic commits
>
> From: Ville Syrjälä
>
> We'll
We need to configure VSC Select field in video dip ctl if we want to have
e.g. colorimetry date in our VSC SDP.
Reported-by: Shawn Lee
Signed-off-by: Jouni Högander
Acked-by: Rodrigo Vivi
Tested-by: Shawn Lee
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 8
VSC SDP sending is taken care by PSR HW and it's not enabled in
VIDEO_DIP_CTL when PSR is enabled. Readback of VSC SDP is depending on
VSC_SDP being set in intel_crtc_state->infoframes.enabled. In case of PSR
setting this flag is taken care by PSR code -> read back PSR configuration
before reading
Pipe config check is currently ignoring vsc sdp changes completely
if psr is enabled. We want to ignore only PSR part of it as there
might be changes in colorimetry data. Also read back vsc_sdp when psr is
used.
Signed-off-by: Jouni Högander
Reviewed-by: Rodrigo Vivi
Tested-by: Shawn Lee
---
There is no specific reason to prepare VSC SDP for PSR case somehow
differently. Unify PSR and non-PSR preparation.
Signed-off-by: Jouni Högander
Reviewed-by: Rodrigo Vivi
Tested-by: Shawn Lee
---
drivers/gpu/drm/i915/display/intel_dp.c | 43
Currently colorimetry data is not added for psr1 or non-psr case.
Fix this by adding it as needed.
Reported-by: Shawn Lee
Signed-off-by: Jouni Högander
Reviewed-by: Rodrigo Vivi
Tested-by: Shawn Lee
---
drivers/gpu/drm/i915/display/intel_dp.c | 48 ++---
1 file changed,
Colorimetry support is not really a PSR specific thing. Move it to intel_dp
struct and use it also when preparing vsc sdp for non-PSR case.
Signed-off-by: Jouni Högander
Reviewed-by: Rodrigo Vivi
Tested-by: Shawn Lee
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
There is no really need to have separate vsc for psr usage. Use
intel_crtc_state->infoframes.vsc instead.
Signed-off-by: Jouni Högander
Reviewed-by: Rodrigo Vivi
Tested-by: Shawn Lee
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
drivers/gpu/drm/i915/display/intel_psr.c
Current VSC SDP configuration code is broken:
1. Driver configured header and data is not used at all
2. Colorimetry data is not added into VSC SDP if PSR1 is used
This patch set fixes these problems and makes VSC SDP configuration a
bit more simpler by unifying PSR and non-PSR cases.
v2:
On Wed, 20 Dec 2023, Ville Syrjälä wrote:
> On Tue, Dec 19, 2023 at 05:49:52PM -0800, Radhakrishna Sripada wrote:
>> Discrete cards do not have ACPI opregion. The vbt is stored in a special
>> flash accessible by the display controller. In order to access the vbt
>> in such cases, re-use the vbt,
> -Original Message-
> From: Jani Nikula
> Sent: Friday, December 15, 2023 5:10 PM
> To: Kahola, Mika ; Deak, Imre ;
> intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915/display: C20 clock state verification
>
> On Fri, 15 Dec 2023, "Kahola, Mika" wrote:
> >> -Original
> -Original Message-
> From: Intel-gfx On Behalf Of
> Rodrigo Vivi
> Sent: Friday, December 15, 2023 7:26 PM
> To: Hogander, Jouni
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 7/7] drm/i915/display: Take care of VSC select field in
> video dip ctl register
>
> On Thu,
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