Check return value for drmm_mutex_init as it can fail and return on
failure.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/d
On Thu, Mar 21, 2024 at 05:04:51AM +, Murthy, Arun R wrote:
-Original Message-
From: De Marchi, Lucas
Sent: Wednesday, March 20, 2024 6:06 AM
To: Murthy, Arun R
Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
Subject: Re: [PATCH] drm/xe/display: check for erro
== Series Details ==
Series: drm/i915/display: Fixed a screen flickering when turning on display
from off (rev6)
URL : https://patchwork.freedesktop.org/series/130780/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14459 -> Patchwork_130780v6
==
> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, March 20, 2024 6:06 AM
> To: Murthy, Arun R
> Cc: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: Re: [PATCH] drm/xe/display: check for error on drmm_mutex_init
>
> On Tue, Mar 19, 2024 at 08:3
From: Gareth Yu
Turn on the panel from zero brightness of the last state, the panel was
set a maximum PWM in the flow. Once the panel initialization is completed,
the backlight is restored to xero brightness. There is a flckering
generated. This flicker happens in "Screen dimming and power off" o
> If we provide the total GTT size we will have one page that will be contended
> between kernel and userspace and, if userspace is unaware that the page
> belongs to the > kernel, we might step on each other toe.
That's fine, Compute needs to know total GTT size.
Not available GTT size.
LGTM.
Reviewed-by: Ankit Nautiyal
On 3/20/2024 10:30 AM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Upda
== Series Details ==
Series: drm/i915: Do not print 'pxp init failed with 0' when it succeed
URL : https://patchwork.freedesktop.org/series/131389/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131389v1
S
== Series Details ==
Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
URL : https://patchwork.freedesktop.org/series/131386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131386v1
Summary
---
== Series Details ==
Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
URL : https://patchwork.freedesktop.org/series/131386/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix
URL : https://patchwork.freedesktop.org/series/131386/
State : warning
== Summary ==
Error: dim checkpatch failed
9183ac6af689 drm/i915/dp: Fix DSC line buffer depth programming
ca44bf249961 drm/i915/dp_mst: Fix symbo
== Series Details ==
Series: drm/i915: Allow the first async flip to change modifier
URL : https://patchwork.freedesktop.org/series/131379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131379v1
Summary
-
== Series Details ==
Series: drm/i915: Allow the first async flip to change modifier
URL : https://patchwork.freedesktop.org/series/131379/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include
== Series Details ==
Series: series starting with [1/2] drm/i915/de: register wait function renames
URL : https://patchwork.freedesktop.org/series/131378/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131378v1
== Series Details ==
Series: series starting with [1/2] drm/i915/de: register wait function renames
URL : https://patchwork.freedesktop.org/series/131378/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./a
== Series Details ==
Series: drm/i915: pass encoder around more for port/phy checks (rev2)
URL : https://patchwork.freedesktop.org/series/131031/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14459 -> Patchwork_131031v2
Sum
== Series Details ==
Series: drm/i915: pass encoder around more for port/phy checks (rev2)
URL : https://patchwork.freedesktop.org/series/131031/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/i
== Series Details ==
Series: drm/i915: pass encoder around more for port/phy checks (rev2)
URL : https://patchwork.freedesktop.org/series/131031/
State : warning
== Summary ==
Error: dim checkpatch failed
f421cc680f3a drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin()
2eb685bfa6e8
Thank You for the fixes
Tested-by: Khaled Almahallawy
On Wed, 2024-03-20 at 22:11 +0200, Imre Deak wrote:
> This patchset fixes a few MTL/DSC 1.2 related issues and adds a
> workaround for the native 5k@60Hz uncompressed mode on a
> MediaTek/Dell
> UHBR monitor, force-enabling DSC on it as requi
Hi Stan
On Tue, 2024-02-20 at 11:31 +0200, Stanislav Lisovskiy wrote:
> Problem is that on some platforms, we do get QGV point mask in wrong
> state on boot. However driver assumes it is set to 0
> (i.e all points allowed), however in reality we might get them all restricted,
> causing issues.
>
Hi Stan.
On Tue, 2024-02-20 at 11:31 +0200, Stanislav Lisovskiy wrote:
> We need that in order to force disable SAGV in next patch.
> Also it is beneficial to separate that code, as in majority cases,
> when SAGV is enabled, we don't even need those calculations.
> Also we probably need to determ
== Series Details ==
Series: Bigjoiner refactoring (rev14)
URL : https://patchwork.freedesktop.org/series/128311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14458 -> Patchwork_128311v14
Summary
---
**SUCCESS**
== Series Details ==
Series: Bigjoiner refactoring (rev14)
URL : https://patchwork.freedesktop.org/series/128311/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warni
== Series Details ==
Series: Bigjoiner refactoring (rev14)
URL : https://patchwork.freedesktop.org/series/128311/
State : warning
== Summary ==
Error: dim checkpatch failed
ab1e39980e9f drm/i915: Add a small helper to compute the set of pipes for crtc
921ae16a87ff drm/i915: Extract intel_ddi_p
It is misleading, if the intention was to also print something
in case it succeed it should have a different string.
Cc: Alan Previn
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_driver.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
Factor out a function to check for UHBR channel coding support used by a
follow-up patch in the patchset.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
include/drm/display/drm_dp_helper.h | 6 ++
2 files changed, 7 insert
The DPCD OUI of the logical port on a Dell UHBR monitor - on which the
AUX device is used to enable DSC - is all 0. To detect if the HBLANK
expansion quirk is required for this monitor use the OUI of the port's
parent instead.
Since in the above case the DPCD of both the logical port and the paren
Factor out a function to check if an MST port is logical, used by a
follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 6 +++---
include/drm/display/drm_dp_mst_helper.h | 7 +
Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA
monitor results in a blank screen, at least on MTL platforms on UHBR
link rates with some (<30) uncompressed bpp values. Enabling compression
fixes the problem, so do that for now. Windows enables DSC always if the
sink supports i
Add a function to get the AUX device of the parent of an MST port, used
by a follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 16
1 file changed, 16 insertions(+
Instead of checking each compressed bpp value against the maximum
DSC/DPT bpp, simplify things by calculating the maximum bpp upfront and
limiting the range of bpps looped over using this maximum.
While at it add a comment about the origin of the DSC/DPT bpp limit.
Bspec: 49259, 68912
Signed-off
The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
do so.
Bspec: 49259
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm
The DSC DPT interface BW limit check should take into account the link
clock's (aka DDI clock in bspec) channel coding efficiency overhead.
Bspec doesn't mention this, however this matches how the link BW limit
is checked (that is the BW limit on wire as opposed to the above DPT
limit) for which Bs
The expected link symbol clock unit when calculating the DSC DPT bpp
limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit
based on the crtc clock. As opposed to this port_clock is used - which
has a 10 kbits/sec unit - with the resulting symbol clock in 10
kSymbols/sec units (disreg
The DSC DPT bpp limit check should only fail if the available DPT BW is
less than the required BW, fix the check accordingly.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/
Fix the calculation of the DSC line buffer depth. This is limited both
by the source's and sink's maximum line buffer depth, but the former one
was not taken into account. On all Intel platform's the source's maximum
buffer depth is 13, so the overall limit is simply the minimum of the
source/sink'
This patchset fixes a few MTL/DSC 1.2 related issues and adds a
workaround for the native 5k@60Hz uncompressed mode on a MediaTek/Dell
UHBR monitor, force-enabling DSC on it as required, similarly to the
existing HBLANK expansion quirk for Synaptics hubs.
Imre Deak (11):
drm/i915/dp: Fix DSC lin
Hi Andi,
On Wednesday, 20 March 2024 15:29:58 CET Andi Shyti wrote:
> Hi Janusz,
>
> ...
>
> > Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/10154
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > Signed-off-by:
Hi Michal,
On Mon, Mar 18, 2024 at 05:21:54AM +, Mrozek, Michal wrote:
> > > Lionel, Michal, thoughts?
> Compute UMD needs to know exact GTT total size.
the problem is that we cannot apply the workaround without
reserving one page from the GTT total size and we need to apply
the workaround.
Hi Tvrtko,
On Wed, Mar 20, 2024 at 03:40:18PM +, Tvrtko Ursulin wrote:
> On 20/03/2024 15:06, Andi Shyti wrote:
> > Ping! Any thoughts here?
>
> I only casually observed the discussion after I saw Matt suggested further
> simplifications. As I understood it, you will bring back the uabi engin
Hi Stan
On Tue, 2024-02-20 at 11:31 +0200, Stanislav Lisovskiy wrote:
> For debug purposes we need those - error path won't flood the log,
> however there has been already numerous cases, when due to lack
> of debugs, we couldn't immediately tell what was the problem on
> customer machine, which s
On Wed, 20 Mar 2024, Jani Nikula wrote:
> On Wed, 20 Mar 2024, Julia Lawall wrote:
> > On Wed, 20 Mar 2024, Jani Nikula wrote:
> >> Okay, I have another one wrt macros. :)
> >>
> >> I'm trying to add a completely new variadic macro, but it fails at
> >> "...". I've tried all sorts of things, b
From: Ville Syrjälä
Pull the ilk/snb/ivb LP watermark disable checks into a separate
function similar to the gmch counterpart (i9xx_must_disable_cxsr()).
Reduces the clutter in intel_plane_atomic_calc_changes() significantly.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atom
From: Ville Syrjälä
Rename need_async_flip_disable_wa to need_async_flip_toggle_wa to
better reflect the fact that we need to deal with the bad
PLANE_CTL_ASYNC_FLIP double buffering behaviour going both
ways.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c |
From: Ville Syrjälä
On bdw-glk the sync->async flip change takes an extra frame due to
the double buffering behaviour of the async flip plane control bit.
Since on skl+ we are now explicitly converting the first async flip
to a sync flip (in order to allow changing the modifier and/or
ddb/waterm
From: Ville Syrjälä
With Xorg+modesetting on skl+ we see the following behaviour:
1. root pixmap is X-tiled
2. client submitted buffers can be Y-tiled (w/ 'Option "dmabuf_capable"')
3. we try to switch from the X-tiled buffer to the Y-tiled buffer
using an async flip (when vsync is disabled).
From: Ville Syrjälä
DDB/watermarks are always double buffered on the vblank, so we
can't safely change them during async flips. Currently this never
happens, but we'll be making changing between sync and async
flips a bit more flexible, in which case we can actually end up
here.
Signed-off-by: V
From: Ville Syrjälä
On ADL async flips apparently generate DMAR and GGTT faults
(with accompanying visual glitches) unless PLANE_SURF is
aligned to at least 16k. Bump up the alignment to 16k.
TODO: analyze things better to figure out what is really
going on here
Signed-off-by: Ville Syrjä
From: Ville Syrjälä
Xorg/modesetting expects to be able to change the modifier already
when submitting the first async flip. Let's convert the first async
flip to a sync flip so that we can accommodate it. For now I limit
this behaviour to skl+ since earlier platforms don't support async
flips wi
Prefer the intel_de_wait*() functions over the uncore interface.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 7 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 6 +++---
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915
Do some renames on the register wait functions for clarity and brevity:
intel_de_wait_for_register -> intel_de_wait
intel_de_wait_for_register_fw -> intel_de_wait_fw
__intel_de_wait_for_register-> intel_de_wait_custom
In particular, it seemed odd to have a double-underscored function b
look all ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 18.3.2024 22.44, Ville Syrjala wrote:
From: Ville Syrjälä
Advertize more suitable cursor sizes via the new SIZE_HINTS
plane property.
We can't really enumerate all supported cursor sizes on
the platforms where the cursor height can vary
On Wed, 20 Mar 2024, Julia Lawall wrote:
> On Wed, 20 Mar 2024, Jani Nikula wrote:
>> Okay, I have another one wrt macros. :)
>>
>> I'm trying to add a completely new variadic macro, but it fails at
>> "...". I've tried all sorts of things, but can't seem to be able to add
>> a literal "...".
>>
>
On Wed, 20 Mar 2024, Ville Syrjälä wrote:
> I have basically that same patch sitting in some branch.
I would expect no less. ;D
> With commit messages polished the series is
> Reviewed-by: Ville Syrjälä
Thanks, fixed up the commit messages and posted v1 for CI.
BR,
Jani.
--
Jani Nikula, I
The encoder is a much more useful thing to pass around than the i915 and
port combo. Also drive-by clean up some cases where both i915 and
encoder are passed; only the latter is needed.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 258
The intel_is_c10phy() is now unused. Remove.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 --
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 --
2 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/
Pass encoder to intel_wait_ddi_buf_active(). The encoder will be more
helpful than just port in the subsequent changes.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --gi
Pass encoder to the _port_to_ddc_pin() functions, and rename to
_encoder_to_ddc_pin(). The encoder will be more helpful than just port
in the subsequent changes.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 60 ++-
1 f
Wherever possible, replace the port/phy based functions with the encoder
based functions:
intel_is_c10phy() -> intel_encoder_is_c10phy()
intel_phy_is_combo()-> intel_encoder_is_combo()
intel_phy_is_tc() -> intel_encoder_is_tc()
intel_port_to_phy() -> intel_encoder_to_phy()
inte
Add a number of encoder based functions to check if the port/phy of the
encoder is of a certain type, or to convert to phy or tc_port. Initially
these are just wrappers around the existing functions, but they can be
improved to use VBT data or use some cached info in the future.
Reviewed-by: Ville
Pass encoder to intel_snps_phy_update_psr_power_state(). The encoder
will be more helpful than just port in the subsequent changes.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 ++-
drivers/gpu/drm/i915/display/intel_snps_phy.c
v1 after the reviewed RFC [1].
BR,
Jani.
[1] https://lore.kernel.org/r/cover.1710253533.git.jani.nik...@intel.com
Jani Nikula (7):
drm/hdmi: convert *_port_to_ddc_pin() to *_encoder_to_ddc_pin()
drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active()
drm/i915/snps: pass encoder to intel
== Series Details ==
Series: Disable automatic load CCS load balancing (rev11)
URL : https://patchwork.freedesktop.org/series/129951/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/b
== Series Details ==
Series: Disable automatic load CCS load balancing (rev11)
URL : https://patchwork.freedesktop.org/series/129951/
State : warning
== Summary ==
Error: dim checkpatch failed
5cc9ec8ba58f drm/i915/gt: Disable HW load balancing for CCS
4f9767936687 drm/i915/gt: Do not generate
== Series Details ==
Series: Disable automatic load CCS load balancing (rev11)
URL : https://patchwork.freedesktop.org/series/129951/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14455 -> Patchwork_129951v11
Summary
--
On 20/03/2024 15:06, Andi Shyti wrote:
Ping! Any thoughts here?
I only casually observed the discussion after I saw Matt suggested
further simplifications. As I understood it, you will bring back the
uabi engine games when adding the dynamic behaviour and that is fine by me.
Regards,
Tvr
== Series Details ==
Series: drm/i915/gt: Reset queue_priority_hint on parking (rev2)
URL : https://patchwork.freedesktop.org/series/131268/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14455 -> Patchwork_131268v2
Summary
On Tue, Mar 12, 2024 at 04:28:55PM +0200, Jani Nikula wrote:
> Based on my ideas at [1], pass the encoder around more instead of i915,
> port pair. Look up phy and TC port based on encoder.
>
> This could be later extended to e.g. cache the info to encoder and/or
> look up data from encoder->devda
Handle only bigjoiner masters in skl_commit_modeset_enables/disables,
slave crtcs should be handled by master hooks. Same for encoders.
That way we can also remove a bunch of checks like
intel_crtc_is_bigjoiner_slave.
v2: - Moved skl_pfit_enable, intel_dsc_enable, intel_crtc_vblank_on to
intel_e
Ping! Any thoughts here?
Andi
On Wed, Mar 13, 2024 at 09:19:48PM +0100, Andi Shyti wrote:
> Hi,
>
> this series does basically two things:
>
> 1. Disables automatic load balancing as adviced by the hardware
>workaround.
>
> 2. Assigns all the CCS slices to one single user engine. The user
== Series Details ==
Series: drm/i915/gt: Reset queue_priority_hint on parking (rev2)
URL : https://patchwork.freedesktop.org/series/131268/
State : warning
== Summary ==
Error: dim checkpatch failed
8dae724cae08 drm/i915/gt: Reset queue_priority_hint on parking
-:19: WARNING:COMMIT_LOG_LONG_L
On Wed, 20 Mar 2024, Jani Nikula wrote:
> On Wed, 20 Mar 2024, Ville Syrjälä wrote:
> > On Wed, Mar 20, 2024 at 02:24:08PM +0100, Julia Lawall wrote:
> >>
> >>
> >> On Wed, 20 Mar 2024, Ville Syrjälä wrote:
> >>
> >> > Hi Julia et al,
> >> >
> >> > In Linux drm/i915 driver (drivers/gpu/drm/i915
Hi Janusz,
...
> Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/10154
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Signed-off-by: Janusz Krzysztofik
> Cc: Chris Wilson
> Cc: # v5.4+
this tag list is a bit confusin
== Series Details ==
Series: series starting with [1/2] drm/i915/bios: Tolerate devdata==NULL in
intel_bios_encoder_supports_dp_dual_mode() (rev2)
URL : https://patchwork.freedesktop.org/series/131316/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14455 -> Patchwork_131316v2
On Wed, 20 Mar 2024, Ville Syrjälä wrote:
> On Wed, Mar 20, 2024 at 02:24:08PM +0100, Julia Lawall wrote:
>>
>>
>> On Wed, 20 Mar 2024, Ville Syrjälä wrote:
>>
>> > Hi Julia et al,
>> >
>> > In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch])
>> > we have a magic macro like t
On Wed, Mar 20, 2024 at 02:24:08PM +0100, Julia Lawall wrote:
>
>
> On Wed, 20 Mar 2024, Ville Syrjälä wrote:
>
> > Hi Julia et al,
> >
> > In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch])
> > we have a magic macro like this:
> >
> > #define with_intel_pps_lock(dp, wf) \
>
On Wed, 20 Mar 2024, Ville Syrjälä wrote:
> Hi Julia et al,
>
> In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch])
> we have a magic macro like this:
>
> #define with_intel_pps_lock(dp, wf) \
Did you try declaring:
iterator name with_intel_pps_lock;
up with the metavariabl
Hi Julia et al,
In Linux drm/i915 driver (drivers/gpu/drm/i915/display/intel_pps.[ch])
we have a magic macro like this:
#define with_intel_pps_lock(dp, wf) \
for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp),
(wf)))
which we can then use like so:
...
with_intel_pps_loc
On Tue, 19 Mar 2024, Luca Coelho wrote:
> On Tue, 2024-03-19 at 17:06 +0200, Jani Nikula wrote:
>> On Tue, 19 Mar 2024, Lucas De Marchi wrote:
>> > On Thu, Mar 14, 2024 at 08:52:21AM +0200, Luca Coelho wrote:
>> > > Some of the backported intel_uncore_read*() functions used the wrong
>> > > types
== Series Details ==
Series: Wa_16021440873 and early transport fixes (rev2)
URL : https://patchwork.freedesktop.org/series/131324/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14453 -> Patchwork_131324v2
Summary
---
== Series Details ==
Series: Wa_16021440873 and early transport fixes (rev2)
URL : https://patchwork.freedesktop.org/series/131324/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bit
== Series Details ==
Series: drm/i915: cleanup dead code
URL : https://patchwork.freedesktop.org/series/131354/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14453 -> Patchwork_131354v1
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915: cleanup dead code
URL : https://patchwork.freedesktop.org/series/131354/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: cleanup dead code
URL : https://patchwork.freedesktop.org/series/131354/
State : warning
== Summary ==
Error: dim checkpatch failed
8f73eff2311a drm/i915: Drop dead code for xehpsdv
-:918: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#
On 3/15/2024 1:56 PM, Ville Syrjälä wrote:
On Wed, Mar 13, 2024 at 08:08:25PM +0530, Ankit Nautiyal wrote:
For Earlier platforms, the Pipe source size is 12-bits so
max pipe source width and height is 4096. For newer platforms it is
13-bits so theoretically max width/height is 8192. For few of
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