== Series Details ==
Series: drm/i915: skl+ plane register stuff (rev6)
URL : https://patchwork.freedesktop.org/series/133458/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14756_full -> Patchwork_133458v6_full
Summary
== Series Details ==
Series: drm/edid: remove drm_do_get_edid()
URL : https://patchwork.freedesktop.org/series/133569/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14757 -> Patchwork_133569v1
Summary
---
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Having the plane WM/DDB regitster write functions in skl_watermarks.c
> is rather annoying when trying to implement DSB based plane updates.
> Move them into the respective files that handle all other plane
> register writes.
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
> just call intel_de_write_fw() directly.
>
> This is prep work towards DSB based plane updates where these
> wrappers are more of a hinderance.
>
> Done with cocci
On Mon, 13 May 2024, Jani Nikula wrote:
> On Mon, 13 May 2024, Ville Syrjala wrote:
>> From: Ville Syrjälä
>>
>> Currentluy every skl+ plane register defines some intermediate
*Currently
>> macros to calculate the final register offset. Pull all of that
>> into common macros, simplifying the
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract helpers to calculate the final wm/ddb register
> values for skl+. Will allow me to more cleanly remove the
> register write wrappers for these registers.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
>
On Mon, 13 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currentluy every skl+ plane register defines some intermediate
> macros to calculate the final register offset. Pull all of that
> into common macros, simplifying the final register offset stuff
> into just five defines:
> - raw
On Mon, 13 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rearrange the plane skl+ universal plane register definitions:
> - keep everything related to the same register in one place
> - sort based on register offset
> - unify the whitespace/etc a bit
>
> v2: Define register contents
All users of drm_do_get_edid() have been converted to
drm_edid_read_custom(). Remove the unused function to prevent new users
from creeping in.
Signed-off-by: Jani Nikula
---
Cc: Robert Foss
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
---
drivers/gpu/drm/drm_edid.c | 28
On Mon, 13 May 2024, Lucas De Marchi wrote:
> On Mon, May 13, 2024 at 03:10:29PM GMT, Jani Nikula wrote:
>>On Fri, 10 May 2024, Jani Nikula wrote:
>>> The xe->enabled_irq_mask member has never been used for anything.
>>>
>>> Signed-off-by: Jani Nikula
>>
>>Lucas, ack for merging these two via
On Mon, 13 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Export drm_plane_has_format() so that drivers can use it.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_crtc_internal.h | 2 --
> drivers/gpu/drm/drm_plane.c | 1 +
>
On Mon, 13 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename drm_plane_check_pixel_format() to drm_plane_has_format()
> and change the return type accordingly. Allows one to write
> more natural code.
>
> Also matches drm_any_plane_has_format() better.
>
> Signed-off-by: Ville
== Series Details ==
Series: drm/i915: Polish plane surface alignment handling
URL : https://patchwork.freedesktop.org/series/133564/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14756 -> Patchwork_133564v1
Summary
== Series Details ==
Series: drm/i915: Polish plane surface alignment handling
URL : https://patchwork.freedesktop.org/series/133564/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: skl+ plane register stuff (rev6)
URL : https://patchwork.freedesktop.org/series/133458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14756 -> Patchwork_133458v6
Summary
---
== Series Details ==
Series: drm/i915: skl+ plane register stuff (rev6)
URL : https://patchwork.freedesktop.org/series/133458/
State : warning
== Summary ==
Error: dim checkpatch failed
6783d48ac30b drm/i915: Nuke _MMIO_PLANE_GAMC()
6d5c913cfe2c drm/i915: Extract skl_universal_plane_regs.h
== Series Details ==
Series: drm/i915: skl+ plane register stuff (rev6)
URL : https://patchwork.freedesktop.org/series/133458/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Ville Syrjälä
I don't think the display hardware really has such chroma
plane tile row alignment requirements as outlined in
commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
UV plane is tile row size aligned")
Bspec had the same exact thing to say about earlier hardware
as well,
From: Ville Syrjälä
Currently we still use the SKL+ PLANE_SURF alignment even
for TGL+ even though the hardware no longer needs it.
Introduce a separate tgl_plane_min_alignment() and update
it to more accurately reflect the hardware requirements.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Now that all pre-skl platforms have their own .min_alignment()
functions the remainder of intel_surf_alignment() can be hoisted
into skl_univerals_plane.c (and renamed appropriately).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb.c | 77
From: Ville Syrjälä
Extract the necessary chunks from intel_surf_alignment()
into per-platform variants for all pre-skl primary/sprite
planes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 69 -
drivers/gpu/drm/i915/display/intel_fb.c |
From: Ville Syrjälä
Split intel_cursor_alignment() into per-platform variants.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++--
drivers/gpu/drm/i915/display/intel_fb.c | 16 -
drivers/gpu/drm/i915/display/intel_fb.h | 3
From: Ville Syrjälä
Different planes could have different alignment requirements
even for the same format/modifier. Collect the alignment
requirements across all planes capable of scanning out the
fb such that the alignment used when pinning the normal ggtt
view is satisfactory to all those
From: Ville Syrjälä
Different hardware generations have different scanout alignment
requirements. Introduce a new vfunc that will allow us to
make that distinction without horrible if-ladders.
For now we directly plug in the existing intel_surf_alignment()
and intel_cursor_alignment()
From: Ville Syrjälä
Rename drm_plane_check_pixel_format() to drm_plane_has_format()
and change the return type accordingly. Allows one to write
more natural code.
Also matches drm_any_plane_has_format() better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c| 7 ++-
From: Ville Syrjälä
Export drm_plane_has_format() so that drivers can use it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_crtc_internal.h | 2 --
drivers/gpu/drm/drm_plane.c | 1 +
include/drm/drm_plane.h | 2 ++
3 files changed, 3 insertions(+), 2 deletions(-)
From: Ville Syrjälä
intel_surf_alignment() in particular has devolved into
a complete mess. Redesign the code so that we can handle
alignment restrictions in a nicer. Also adjust alignment
for TGL+ to actually match the hardware requirements.
Ville Syrjälä (9):
drm: Rename
On Fri, May 10, 2024 at 5:09 PM Jani Nikula wrote:
>
> amdgpu_connector_edid() copies the EDID from edid_blob_ptr as a side
> effect if amdgpu_connector->edid isn't initialized. However, everywhere
> that the returned EDID is used, the EDID should have been set
> beforehands.
>
> Only the drm
From: Ville Syrjälä
Currentluy every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and
From: Ville Syrjälä
A few extra tabs have snuck into the skl+ plane register bit
definitions. Remove them.
v2: Rebase
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
From: Ville Syrjälä
A couple of PLANE_WM bits were still using the hand
rolled (1<
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On Fri, May 10, 2024 at 5:08 PM Jani Nikula wrote:
>
> radeon_connector_edid() copies the EDID from edid_blob_ptr as a side
> effect if radeon_connector->edid isn't initialized. However, everywhere
> that the returned EDID is used, the EDID should have been set
> beforehands.
>
> Only the drm
From: Ville Syrjälä
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit
v2: Define register contents after all offsets (Jani)
Cc: Jani Nikula
Signed-off-by:
From: Ville Syrjälä
We only need register defines for the first two planes
on the first two pipes. Nuke everything else.
v2: Drop a few more that snuck through
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
.../i915/display/skl_universal_plane_regs.h | 19
On Fri, May 10, 2024 at 5:08 PM Jani Nikula wrote:
>
> Prefer the parsed results for is_hdmi and has_audio in display info over
> calling drm_detect_hdmi_monitor() and drm_detect_monitor_audio(),
> respectively.
>
> Cc: Alex Deucher
> Cc: Christian König
> Cc: Pan, Xinhui
> Cc:
On Mon, May 13, 2024 at 02:28:11PM +0300, Jani Nikula wrote:
> On Fri, 10 May 2024, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Rearrange the plane skl+ universal plane register definitions:
> > - keep everything related to the same register in one place
> > - sort based on register
On Mon, May 13, 2024 at 02:14:51AM -0400, Deming Wang wrote:
> The mapings should be replaced by mappings.
>
> Signed-off-by: Deming Wang
Reviewed-by: Rodrigo Vivi
and pushed to drm-intel-gt-next
thanks for the patch
> ---
> drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +-
> 1 file
> -Original Message-
> From: Shankar, Uma
> Sent: Thursday, May 9, 2024 11:05 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ;
> jani.nik...@linux.intel.com; Roper, Matthew D ;
> Shankar, Uma
> Subject: [v4] drm/i915: Implement
On Mon, May 13, 2024 at 03:10:29PM GMT, Jani Nikula wrote:
On Fri, 10 May 2024, Jani Nikula wrote:
The xe->enabled_irq_mask member has never been used for anything.
Signed-off-by: Jani Nikula
Lucas, ack for merging these two via drm-intel-next? Even though these
touch struct xe_device, I
== Series Details ==
Series: drm/i915/gem/i915_gem_ttm_move: Fix typo
URL : https://patchwork.freedesktop.org/series/133540/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14754 -> Patchwork_133540v1
Summary
---
The WA should be extended to cover VDBOX engine. We found that
28-channels 1080p VP9 encoding may hit this issue.
Signed-off-by: Chen, Angus
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
== Series Details ==
Series: drm/i915: Correct error handler (rev4)
URL : https://patchwork.freedesktop.org/series/133538/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/133538/revisions/4/mbox/ not
applied
Applying: drm/i915: Correct error
On Mon, May 13, 2024 at 8:20 AM Jani Nikula wrote:
>
> On Fri, 10 May 2024, Alex Deucher wrote:
> > On Fri, May 10, 2024 at 11:17 AM Jani Nikula wrote:
> >>
> >> I've sent this some moths ago, let's try again...
> >>
> >> BR,
> >> Jani.
> >>
> >> Jani Nikula (6):
> >> drm/nouveau: convert to
Maybe the format is incorrect. I would like to use
"jiashengjiangc...@outlook.com" to resend my patch.
-Jiasheng
From: Jiasheng Jiang
Sent: Saturday, May 11, 2024 3:40
To: jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com;
Replace "slab_priorities" with "slab_dependencies" in the error handler
to avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Jiasheng Jiang
Replace "slab_priorities" with "slab_dependencies" in the error handler
to avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1
The mapings should be replaced by mappings.
Signed-off-by: Deming Wang
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index
Replace "slab_priorities" with "slab_dependencies" in the error handler to
avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Replace "slab_priorities" with "slab_dependencies" in the error handler
to avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Angus Chen
Applying it to VDBOX after recent performance data on MTL
Signed-off-by: Angus Chen
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
On Fri, 10 May 2024, Alex Deucher wrote:
> On Fri, May 10, 2024 at 11:17 AM Jani Nikula wrote:
>>
>> I've sent this some moths ago, let's try again...
>>
>> BR,
>> Jani.
>>
>> Jani Nikula (6):
>> drm/nouveau: convert to using is_hdmi and has_audio from display info
>> drm/radeon: convert to
On Fri, 10 May 2024, Lyude Paul wrote:
> Reviewed-by: Lyude Paul
Thanks, how do you want to handle merging this?
BR,
Jani.
>
> On Fri, 2024-05-10 at 18:08 +0300, Jani Nikula wrote:
>> Prefer the parsed results for is_hdmi and has_audio in display info
>> over
>> calling
On Fri, 10 May 2024, Jani Nikula wrote:
> The xe->enabled_irq_mask member has never been used for anything.
>
> Signed-off-by: Jani Nikula
Lucas, ack for merging these two via drm-intel-next? Even though these
touch struct xe_device, I presume any further cleanups touching the
surrounding
== Series Details ==
Series: drm/i915/fbc: Add sizes to info message about reducing fb size
URL : https://patchwork.freedesktop.org/series/133534/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14752 -> Patchwork_133534v1
== Series Details ==
Series: drm/i915/fbc: Add sizes to info message about reducing fb size
URL : https://patchwork.freedesktop.org/series/133534/
State : warning
== Summary ==
Error: dim checkpatch failed
f707833392ee drm/i915/fbc: Add sizes to info message about reducing fb size
-:10:
On Mon, 13 May 2024, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Mitul
>> Golani
>> Sent: Thursday, May 9, 2024 1:28 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Shankar, Uma ; Nikula, Jani
>>
>> Subject: [PATCH v8 1/7] drm/i915: Define and compute
On Thu, 09 May 2024, Mitul Golani wrote:
> Add register definitions for Transcoder Fixed Average
> Vtotal mode/CMRR function, with the necessary bitfields.
> Compute these registers when CMRR is enabled, extending
> Adaptive refresh rate capabilities.
>
> --v2:
> - Use intel_de_read64_2x32 in
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rearrange the plane skl+ universal plane register definitions:
> - keep everything related to the same register in one place
> - sort based on register offset
> - unify the whitespace/etc a bit
>
> Signed-off-by: Ville Syrjälä
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 13, 2024 1:02 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v4 4/6] drm/i915/alpm: Add compute config for lobf
>
> -Original Message-
> From: Intel-xe On Behalf Of
> Gustavo Sousa
> Sent: Friday, May 10, 2024 7:36 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: [PATCH] drm/i915/bmg: Load DMC
>
> Load Battlemage's DMC. We re-use XELPDP_DMC_MAX_FW_SIZE since
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, May 9, 2024 1:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
>
> Subject: [PATCH v8 2/7] drm/i915: Add Enable/Disable for CMRR based on VRR
> state
>
> Add CMRR/Fixed
The info message currently does not contain any information, how much
the stolen memory size should be increased.
[drm] Reducing the compressed framebuffer size. This may lead to less power
savings than a non-reduced-size. Try to increase stolen memory size if
available in BIOS.
To be more
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> A few extra tabs have snuck into the skl+ plane register bit
> definitions. Remove them.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++---
>
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> A couple of PLANE_WM bits were still using the hand
> rolled (1<
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++--
> 1 file changed, 2
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We only need register defines for the first two planes
> on the first two pipes. Nuke everything else.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> .../gpu/drm/i915/display/skl_universal_plane_regs.h |
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane
> and just use the real thing.
>
> Cc: Zhenyu Wang
> CC: Zhi Wang
> Signed-off-by: Ville Syrjälä
The original is a baffling mix.
Reviewed-by: Jani Nikula
>
> -Original Message-
> From: Kandpal, Suraj
> Sent: Tuesday, May 7, 2024 9:34 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Kandpal, Suraj
>
> Subject: [PATCH 0/7] Enable Aux Based EDP HDR
>
> This
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop hand rolling PLANE_KEY*() register defines and just
> use the real thing.
>
> Cc: Zhenyu Wang
> CC: Zhi Wang
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.
>
> Cc: Zhenyu Wang
> CC: Zhi Wang
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 24
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Stop hand rolling PLANE_AUX_DIST() and just use the real thing.
>
> Cc: Zhenyu Wang
> CC: Zhi Wang
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 24
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On SKL+ the watermark/DDB registers are proper per-plane
> registers. Move the definitons to their respective files.
>
> Cc: Zhenyu Wang
> CC: Zhi Wang
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
>
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move most cursor register definitions into their own file.
> Declutters i915_reg.h a bit more.
>
> Cc: Zhenyu Wang
> CC: Zhi Wang
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
>
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move most of the SKL+ universal plane register definitions
> into their own file. Declutters i915_reg.h a bit more.
>
> Cc: Zhenyu Wang
> CC: Zhi Wang
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
>
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> _MMIO_PLANE_GAMC() is some leftover macro that is never used.
> Get rid of it.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 --
> 1 file changed, 2 deletions(-)
>
>
On Friday, 10 May 2024 08:12:02 GMT+2 Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev4)
> URL : https://patchwork.freedesktop.org/series/132786/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
Hi,
There is no way that the tests that are failing in the shards have
anything to do with the small documentation change that is in my patch.
Can you please re-report?
Thanks!
--
Cheers,
Luca.
On Sat, 2024-05-11 at 01:02 +, Patchwork wrote:
> Patch Details
> Series:Documentation/i915:
On Thu, 2024-05-09 at 11:01 +0530, Animesh Manna wrote:
> Link Off Between Active Frames, is a new feature for eDP
> that allows the panel to go to lower power state after
> transmission of data. This is a feature on top of ALPM, AS SDP.
> Add compute config during atomic-check phase.
>
> v1: RFC
On 5/11/2024 5:48 PM, Jiasheng Jiang wrote:
Replace "slab_priorities" with "slab_dependencies" in the error handler to
avoid memory leak.
Nice catch. I would make the subject more like:
drm/i915: Fix memory leak by correcting cache object name in error handler
Fixes: 32eb6bcfdda9
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, May 9, 2024 1:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
>
> Subject: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR
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