Re: [PATCH v2 2/6] drm/ci: generate testlist from build

Hi Dmitry, On 20/05/24 16:30, Dmitry Baryshkov wrote: On Fri, May 17, 2024 at 02:54:58PM +0530, Vignesh Raman wrote: Stop vendoring the testlist into the kernel. Instead, use the testlist from the IGT build to ensure we do not miss renamed or newly added tests. Signed-off-by: Vignesh Raman --

✗ Fi.CI.IGT: failure for drm/xe: Cleanup xe_mmio.h

== Series Details == Series: drm/xe: Cleanup xe_mmio.h URL : https://patchwork.freedesktop.org/series/133825/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14785_full -> Patchwork_133825v1_full Summary --- **FAILURE*

Re: [PATCH 4/5] drm/i915: Compute config and mode valid changes for ultrajoiner

Hi Stanislav, kernel test robot noticed the following build warnings: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip linus/master next-20240520] [cannot apply to drm-intel/for-linux-next-fixes v6.9] [If your patch is applied to the wrong git

✓ Fi.CI.BAT: success for drm/i915/dp_mst: Enable link training fallback (rev3)

== Series Details == Series: drm/i915/dp_mst: Enable link training fallback (rev3) URL : https://patchwork.freedesktop.org/series/133624/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133624v3 Summary ---

✗ Fi.CI.SPARSE: warning for drm/i915/dp_mst: Enable link training fallback (rev3)

== Series Details == Series: drm/i915/dp_mst: Enable link training fallback (rev3) URL : https://patchwork.freedesktop.org/series/133624/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/a

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp_mst: Enable link training fallback (rev3)

== Series Details == Series: drm/i915/dp_mst: Enable link training fallback (rev3) URL : https://patchwork.freedesktop.org/series/133624/ State : warning == Summary == Error: dim checkpatch failed 3901134df2a3 drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs 28d65f0e37e3 drm/i

✓ Fi.CI.BAT: success for drm/xe: Cleanup xe_mmio.h

== Series Details == Series: drm/xe: Cleanup xe_mmio.h URL : https://patchwork.freedesktop.org/series/133825/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133825v1 Summary --- **SUCCESS** No re

✗ Fi.CI.SPARSE: warning for drm/xe: Cleanup xe_mmio.h

== Series Details == Series: drm/xe: Cleanup xe_mmio.h URL : https://patchwork.freedesktop.org/series/133825/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./arch/x86/include/asm/bitops.h:116:1: warning

✗ Fi.CI.CHECKPATCH: warning for drm/xe: Cleanup xe_mmio.h

== Series Details == Series: drm/xe: Cleanup xe_mmio.h URL : https://patchwork.freedesktop.org/series/133825/ State : warning == Summary == Error: dim checkpatch failed ff7fd69a1372 drm/i915/display: Add missing include to intel_vga.c ce3839510f9f drm/xe: Don't rely on indirect includes from x

[PATCH v2 16/21] drm/i915/dp_mst: Enable link training fallback for MST

Reduce the link parameters after a link training failure for MST outputs, similarly to how this is done for SST. For now allow the reduction only by staying in the 8b/10b vs. 128b/132b mode. Enabling the mode switch is left for a follow-up patchset, after taking measures ensuring that the mode swi

[PATCH v2 20/21] drm/i915/dp: Add debugfs entry to force link retrain

Add a connector debugfs entry to force retrain an active link. This can be used to test both custom link parameters (previously set via the target link lane count/rate entries) or link train failure scenarios (previously forced via the force-failure entry). The entry will autoreset after the link-r

[PATCH v2 21/21] drm/i915/dp: Add debugfs entry for link training info

Add counters for link training pass/failure events and a connector debugfs entry showing these and relevant link training information. This is meant to be used by automated testing of the driver's link retraining and link parameter fallback functionality. v2: - Add the entry from intel_dp_link_tra

[PATCH v2 11/21] drm/i915/dp: Use check link state work in the hotplug handler

Simplify things by retraining a DP link if a bad link is detected in the hotplug handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/g4x_dp.c| 20 +---

[PATCH v2 19/21] drm/i915/dp: Add debugfs entry to force link training failure

Add a connector debugfs entry to force a failure during the following 1-2 link training. The entry will auto-reset after the specified link training events are complete. v2: Add the entry from intel_dp_link_training.c (Jani) Cc: Jani Nikula Signed-off-by: Imre Deak --- .../drm/i915/display/int

[PATCH v2 14/21] drm/i915/dp: Disable link retraining after the last fallback step

After a link training failure if the link parameters can't be further reduced, there is no point in trying to retrain the link in the driver. This avoids excessive retrain attempts after detecting a bad link, for instance while handling MST HPD IRQs, which is likely redundant as the link training f

[PATCH v2 13/21] drm/i915/dp: Use check link state work in the HPD IRQ handler

Simplify things by retraining a DP link if a bad link is detected in the HPD IRQ handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 10 ++ 1 file cha

[PATCH v2 17/21] drm/i915/dp: Add debugfs entries to set a target link rate/lane count

Add connector debugfs entries to set a target link rate/lane count to be used by a link training afterwards. After setting a target link rate/lane count reset the link training parameters and for a non-auto target disable reducing the link parameters via the fallback logic. The former one can be u

[PATCH v2 09/21] drm/i915/dp: Pass atomic state to link training function

From: Imre Deak The next patch adds sending a modeset-retry uevent after a link training failure to all MST connectors on link. This requires the atomic state, so pass it to intel_dp_start_link_train(). In case of SST where retraining still happens by calling this function directly instead of a m

[PATCH v2 15/21] drm/i915/dp_mst: Reset intel_dp->link_trained during disabling

Reset the flag indicating an active link after disabling an MST link, similarly to how this is done for SST outputs. This avoids trying to retrain an MST link while its disabled. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+) di

[PATCH v2 18/21] drm/i915/dp: Add debugfs entries to get the max link rate/lane count

Add connector debugfs entries to get the maximum link rate and lane count. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_dp_link_training.c | 46 +++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/

[PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset

Recheck the link state after a passing link training, with a 2 sec delay to account for cases where the link goes bad following the link training and the sink doesn't report this via an HPD IRQ. The delayed work added here will be also used by a later patch after a failed link training to try to r

[PATCH v2 04/21] drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values()

Reduce the indentation in intel_dp_get_link_train_fallback_values() by adding separate helpers to reduce the link rate and lane count. Also simplify things by passing crtc_state to the function. This also prepares for later patches in the patchset adding a limitation on how the link params are red

[PATCH v2 12/21] drm/i915/dp: Use check link state work in the detect handler

Simplify things by retraining a DP link if a bad link is detected in the connector detect handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 7 ++- 1 fil

[PATCH v2 02/21] drm/i915/dp: Move link train params to a substruct in intel_dp

For clarity move the link training parameters updated during link training based on the pass/fail LT result under a substruct in intel_dp. This prepares for later patches in this patchset adding similar params here. Rename intel_dp_reset_max_link_params() to intel_dp_reset_link_params() to better r

[PATCH v2 08/21] drm/i915/dp: Reduce link params only after retrying with unchanged params

Try to maintain the current link parameters by retrying the link training with unchanged link parameters before reducing these parameters (sending an uevent to userspace to retrain the link instead). Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display_types.h| 2 ++ drive

[PATCH v2 06/21] drm/i915/dp: Use a commit modeset for link retraining MST links

Instead of direct calls to the link train functions, retrain the link via a commit modeset. The direct call means that the output port will be disabled/re-enabled while the rest of the pipeline (transcoder) is active, which doesn't seem to work on MST at least. It leads to underruns and black scree

[PATCH v2 10/21] drm/i915/dp: Send a link training modeset-retry uevent to all MST connectors

Send a modeset-retry uevent to all connectors in the same MST topology after a link training failure and reduction of the link parameters. This matches the way the same uevent is sent after a DP tunnel BW allocation failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c

[PATCH v2 05/21] drm/i915: Factor out function to modeset commit a set of pipes

Factor out a function to modeset commit a set of pipes, which a later patch will reuse for DP link retraining. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 31 +- drivers/gpu/drm/i915/display/intel_display.c | 34 drivers/gpu/dr

[PATCH v2 03/21] drm/i915/dp: Move link train fallback to intel_dp_link_training.c

Move the functions used to reduce the link parameters during link training to intel_dp_link_training.c . Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 76 +-- drivers/gpu/drm/i915/display/intel_dp.h | 4 +- .../drm/i915/display/intel_dp_link_

[PATCH v2 00/21] drm/i915/dp_mst: Enable link training fallback

This is v2 of [1], addressing the feedback comments from Jani and Ville: - Use a more generic 'link' substruct instead of 'link_train'. (Patch 2) - Add the debugfs entries from intel_dp_link_training.c . (Patch 17-21) - Add the link state check work to intel_digital_port instead of intel_dp, to

[PATCH v2 01/21] drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs

Symbols consisting of multiple (4) TU timeslots may get split across MTPs when using 2 or 1 link lanes. Avoid this, as required by Bspec by aligning the allocated TUs to 2 when using 2 lanes and 4 when using 1 lane. Atm, we also have to align the PBNs used to allocate BW along the MST path, since

✓ Fi.CI.BAT: success for drm/i915/dpt: Make DPT object unshrinkable (rev2)

== Series Details == Series: drm/i915/dpt: Make DPT object unshrinkable (rev2) URL : https://patchwork.freedesktop.org/series/133818/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133818v2 Summary ---

✗ Fi.CI.SPARSE: warning for drm/i915/dpt: Make DPT object unshrinkable (rev2)

== Series Details == Series: drm/i915/dpt: Make DPT object unshrinkable (rev2) URL : https://patchwork.freedesktop.org/series/133818/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [PATCH 2/5] drm/i915: Implement basic functions for ultrajoiner support

On Mon, May 20, 2024 at 10:38:36AM +0300, Stanislav Lisovskiy wrote: > Lets implement or change basic functions required for ultrajoiner > support from atomic commit/modesetting point of view. > > Signed-off-by: Stanislav Lisovskiy > --- > drivers/gpu/drm/i915/display/intel_display.c | 66 ++

✓ Fi.CI.BAT: success for drm/i915: Plane register cleanups (rev3)

== Series Details == Series: drm/i915: Plane register cleanups (rev3) URL : https://patchwork.freedesktop.org/series/133701/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133701v3 Summary --- **SUC

[PATCH 3/3] drm/xe: Cleanup xe_mmio.h

We don't need include since commit 5c09bd6ccd41 ("drm/xe/mmio: Move xe_mmio_wait32() to xe_mmio.c"). We don't need include since commit 54c659660d63 ("drm/xe: Make xe_mmio_read|write() functions non- inline"). And since commit 924e6a9789a0 ("drm/xe/uapi: Remove MMIO ioctl") we don't need forwar

[PATCH 2/3] drm/xe: Don't rely on indirect includes from xe_mmio.h

These compilation units use udelay() or some GT oriented printk functions without explicitly including proper header files, and relying on #includes from the xe_mmio.h instead. Fix that. Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/xe/xe_device.c | 2 ++ drivers/gpu/drm/xe/xe_gsc.

[PATCH 0/3] drm/xe: Cleanup xe_mmio.h

Unfortunately, this is cross i915/Xe series. Cc: Jani Nikula Cc: Lucas De Marchi Michal Wajdeczko (3): drm/i915/display: Add missing include to intel_vga.c drm/xe: Don't rely on indirect includes from xe_mmio.h drm/xe: Cleanup xe_mmio.h drivers/gpu/drm/i915/display/intel_vga.c | 1 + dr

[PATCH 1/3] drm/i915/display: Add missing include to intel_vga.c

This compilation unit uses udelay() function without including it's header file. Fix that to break dependency on other code. Signed-off-by: Michal Wajdeczko Cc: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vga.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/disp

✗ Fi.CI.SPARSE: warning for drm/i915: Plane register cleanups (rev3)

== Series Details == Series: drm/i915: Plane register cleanups (rev3) URL : https://patchwork.freedesktop.org/series/133701/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev3)

== Series Details == Series: drm/i915: Plane register cleanups (rev3) URL : https://patchwork.freedesktop.org/series/133701/ State : warning == Summary == Error: dim checkpatch failed 9638afbf50ae drm/i915: Add skl+ plane name aliases to enum plane_id 4d3ce0118a4b drm/i915: Clean up the cursor

✓ Fi.CI.IGT: success for Link off between frames for edp (rev5)

== Series Details == Series: Link off between frames for edp (rev5) URL : https://patchwork.freedesktop.org/series/130650/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785_full -> Patchwork_130650v5_full Summary ---

✗ Fi.CI.BAT: failure for drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+ (rev2)

== Series Details == Series: drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+ (rev2) URL : https://patchwork.freedesktop.org/series/133716/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133716v2 Summ

[PATCH] drm/i915/dpt: Make DPT object unshrinkable

In some scenarios, the DPT object gets shrunk but the actual framebuffer did not and thus its still there on the DPT's vm->bound_list. Then it tries to rewrite the PTEs via a stale CPU mapping. This causes panic. Credits-to: Ville Syrjala Shawn Lee Cc: sta...@vger.kernel.org Fixes:

[PATCH v2 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()

From: Ville Syrjälä Split the cursor stuff from the rest of the selective fetch plane registers so that we can collect all cursor registers in intel_cursor_regs.h. Also take the opportunity to rename the registers to match the spec. v2: Pass the correct register offset fpr pipe B (Jani) s/mt

RE: [PATCH] drm/i915/dpt: Make DPT object unshrinkable

> -Original Message- > From: Ville Syrjälä > Sent: Monday, May 20, 2024 10:10 PM > To: Srinivas, Vidya > Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville > ; Lee, > Shawn C ; srini...@freedesktop.org > Subject: Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable > > On Mon, May

Re: [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()

On Mon, May 20, 2024 at 12:27:20PM +0300, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Split the cursor stuff from the rest of the selective fetch > > plane registers so that we can collect all cursor registers > > in intel_cursor_regs.h. Also tak

[PATCH v2] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL-S/ADL-P/DG2+

From: Ville Syrjälä Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2. Bump our limit to match. v2: Bump for ADL-S as well (Jani) Cc: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) d

Re: [PATCH] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+

On Mon, May 20, 2024 at 01:37:26PM +0300, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2. > > *max > > There's also ADL-S with display 12 and 6 Gbps support? Looks like it. Too many weird plat

Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable

On Mon, May 20, 2024 at 08:54:10PM +0530, Srinivas, Vidya wrote: > In some scenarios, the DPT object gets shrunk but > the actual framebuffer did not and thus its still > there on the DPT's vm->bound_list. Then it tries to > rewrite the PTEs via a stale CPU mapping. This causes panic. > > Credits-

Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines

On Mon, 20 May 2024, Ville Syrjälä wrote: > On Mon, May 20, 2024 at 12:10:30PM +0300, Jani Nikula wrote: >> On Thu, 16 May 2024, Ville Syrjala wrote: >> I also think it's kind of unnecessary when they're only >> passed on as parameters. Or is there some corner case where it matters? > > I think c

✓ Fi.CI.BAT: success for drm/i915/dpt: Make DPT object unshrinkable

== Series Details == Series: drm/i915/dpt: Make DPT object unshrinkable URL : https://patchwork.freedesktop.org/series/133818/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133818v1 Summary --- **S

[linux-next:master] BUILD REGRESSION 632483ea8004edfadd035de36e1ab2c7c4f53158

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 632483ea8004edfadd035de36e1ab2c7c4f53158 Add linux-next specific files for 20240520 Error/Warning reports: https://lore.kernel.org/oe-kbuild-all/202405202243.shvs2otq-...@intel.com https

Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines

On Mon, May 20, 2024 at 12:10:30PM +0300, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Group the cursor register defines such that everything to > > do with one register is in one place. > > > > Signed-off-by: Ville Syrjälä > > Reviewed-by: Jani

✗ Fi.CI.SPARSE: warning for drm/i915/dpt: Make DPT object unshrinkable

== Series Details == Series: drm/i915/dpt: Make DPT object unshrinkable URL : https://patchwork.freedesktop.org/series/133818/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [PATCH 2/7] drm/i915: Extract intel_dp_has_dsc()

On Mon, May 20, 2024 at 01:47:34PM +0300, Jani Nikula wrote: > On Fri, 17 May 2024, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Extract a helper to check whether the source+sink combo > > supports DSC. That basic check is needed both during mode > > validation and compute config. We'll a

[PATCH] drm/i915/dpt: Make DPT object unshrinkable

In some scenarios, the DPT object gets shrunk but the actual framebuffer did not and thus its still there on the DPT's vm->bound_list. Then it tries to rewrite the PTEs via a stale CPU mapping. This causes panic. Credits-to: Ville Syrjala Shawn Lee Signed-off-by: Srinivas, Vidya --

Re: Is it possible to distinguish between HDMI and DVI in i915?

On Mon, 20 May 2024, Arkadiusz Drabczyk wrote: > My Asus Z97-A motherboard has DVI and HDMI connectors but i915 shows > 2x HDMI ports (and the 3rd one for DP but a separate DP1 is also > shown). Would it be possible to distinguish between DVI and HDMI in > the driver code for example by reading so

Is it possible to distinguish between HDMI and DVI in i915?

My Asus Z97-A motherboard has DVI and HDMI connectors but i915 shows 2x HDMI ports (and the 3rd one for DP but a separate DP1 is also shown). Would it be possible to distinguish between DVI and HDMI in the driver code for example by reading some undocumented VBT registers or testing port characteri

✓ Fi.CI.BAT: success for Link off between frames for edp (rev5)

== Series Details == Series: Link off between frames for edp (rev5) URL : https://patchwork.freedesktop.org/series/130650/ State : success == Summary == CI Bug Log - changes from CI_DRM_14785 -> Patchwork_130650v5 Summary --- **SUCCE

Re: [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Make a more thorough split between universal planes vs. cursors > by defining the contents of the cursor WM/DDB registers separately. > > Signed-off-by: Ville Syrjälä I like this better than exposing the reg val functions. Rev

Re: [PATCH 13/13] drm/i915: Document which platforms use which sprite registers

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Note which sprite registers are valid for which platforms. > > Signed-off-by: Ville Syrjälä Acked-by: Jani Nikula > --- > .../gpu/drm/i915/display/intel_sprite_regs.h | 19 +++ > 1 file changed, 11 insertion

Re: [PATCH 12/13] drm/i915: Polish sprite plane register definitions

On Mon, 20 May 2024, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: >> From: Ville Syrjälä >> >> Group the sprite plane register definitions such that everything >> to do wiht the same register is in one place. *with >> >> Signed-off-by: Ville Syrjälä > > Reviewed-by: Jani Nik

Re: [PATCH 12/13] drm/i915: Polish sprite plane register definitions

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Group the sprite plane register definitions such that everything > to do wiht the same register is in one place. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../gpu/drm/i915/display/intel_sprite_regs.h

Re: [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Add some notes indicatign which plane registers/bits are *indicating > valid for which platforms. > > Signed-off-by: Ville Syrjälä Acked-by: Jani Nikula because I'm not going to chase through all the specs for these. ;) >

Re: [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Group the pre-skl primary plane register definitions > sensible, and toss in a few comments to indicate which > platforms have what. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../gpu/drm/i915/display/

Re: [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > PIPEGCMAX was left behind when all other gamma registers moved > into intel_color_regs.h. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_color_regs.h | 5 + > drivers

✗ Fi.CI.SPARSE: warning for Link off between frames for edp (rev5)

== Series Details == Series: Link off between frames for edp (rev5) URL : https://patchwork.freedesktop.org/series/130650/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

✗ Fi.CI.CHECKPATCH: warning for Link off between frames for edp (rev5)

== Series Details == Series: Link off between frames for edp (rev5) URL : https://patchwork.freedesktop.org/series/130650/ State : warning == Summary == Error: dim checkpatch failed 70ca27e269fd drm/i915/alpm: Move alpm parameters from intel_psr -:83: WARNING:LONG_LINE: line length of 104 exce

Re: [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Relocate all pre-skl primary plane register definitions > into their own declutter i915_reg.h. > > Cc: Zhenyu Wang > Cc: Zhi Wang > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display

Re: [linux-next:master] [mm/slab] 7bd230a266: WARNING:at_mm/util.c:#kvmalloc_node_noprof

this looks like an i915 bug On Wed, May 15, 2024 at 10:41:19AM +0800, kernel test robot wrote: > > > Hello, > > as we understand, this commit is not the root-cause of this WARNING. the > WARNING > just shows in another way by commit changes. > > 53ed0af496422959 7bd230a26648ac68ab3731ebbc4 >

Re: [PATCH] drm/i915/gt: Fix CCS id's calculation for CCS mode setting

> On May 17, 2024, at 17:06, Andi Shyti wrote: > > The whole point of the previous fixes has been to change the CCS > hardware configuration to generate only one stream available to > the compute users. We did this by changing the info.engine_mask > that is set during device probe, reset during

Re: [PATCH 1/2] drm/i915/pciids: switch to xe driver style PCI ID macros

On Wed, 15 May 2024, Jani Nikula wrote: > The PCI ID macros in xe_pciids.h allow passing in the macro to operate > on each PCI ID, making it more flexible. Convert i915_pciids.h to the > same pattern. > > INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and > unconditionally uses INT

Re: [PATCH v5 6/6] drm/i915/alpm: Add debugfs for LOBF

On Mon, 20 May 2024, Animesh Manna wrote: > For validation purpose add debugfs for LOBF. > > v1: Initial version. > v2: Add aux-wake/less info along with lobf status. [Jouni] > > Signed-off-by: Animesh Manna > --- > drivers/gpu/drm/i915/display/intel_alpm.c | 49 +++ > driver

Re: [PATCH v5 4/6] drm/i915/alpm: Add compute config for lobf

On Mon, 20 May 2024, Animesh Manna wrote: > Link Off Between Active Frames, is a new feature for eDP > that allows the panel to go to lower power state after > transmission of data. This is a feature on top of ALPM, AS SDP. > Add compute config during atomic-check phase. > > v1: RFC version. > v2:

Re: [PATCH v2 6/6] drm/ci: update xfails for the new testlist

On Fri, May 17, 2024 at 02:55:02PM +0530, Vignesh Raman wrote: > Now the testlist is used from IGT build, so update > xfails with the new testlist. > > Set the timeout of all i915 jobs to 1h30m since some jobs > takes more than 1 hour to complete. > > Signed-off-by: Vignesh Raman > --- > > v2:

[PATCH v5 3/6] drm/display: Add missing aux less alpm wake related bits

From: Jouni Högander eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Signed-off-by: Jouni Högander --- include/drm/display/drm_dp.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/drm/display

[PATCH v5 6/6] drm/i915/alpm: Add debugfs for LOBF

For validation purpose add debugfs for LOBF. v1: Initial version. v2: Add aux-wake/less info along with lobf status. [Jouni] Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_alpm.c | 49 +++ drivers/gpu/drm/i915/display/intel_alpm.h | 2 + .../drm/i91

[PATCH v5 5/6] drm/i915/alpm: Enable lobf from source in ALPM_CTL

Set the Link Off Between Frames Enable bit in ALPM_CTL register. Note: Lobf need to be enabled adaptive sync fixed refresh mode where vmin = vmax = flipline, which will arise after cmmr feature enablement. Will add enabling sequence in a separate patch. v1: Initial version. v2: Condition check mo

[PATCH v5 4/6] drm/i915/alpm: Add compute config for lobf

Link Off Between Active Frames, is a new feature for eDP that allows the panel to go to lower power state after transmission of data. This is a feature on top of ALPM, AS SDP. Add compute config during atomic-check phase. v1: RFC version. v2: Add separate flag for auxless-alpm. [Jani] v3: - intel_

[PATCH v5 2/6] drm/i915/alpm: Move alpm related code to a new file

Move ALPM feature related code as it will be used for non-psr panel also thorugh LOBF feature. v1: Initial version. v2: Correct ordering in makefile. [Jani] Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_alpm.c | 295 ++

[PATCH v5 1/6] drm/i915/alpm: Move alpm parameters from intel_psr

ALPM can be enabled for non psr panel and currenly aplm-params are encapsulated under intel_psr struct, so moving out to intel_dp struct. Signed-off-by: Animesh Manna --- .../drm/i915/display/intel_display_types.h| 21 + drivers/gpu/drm/i915/display/intel_psr.c | 44 +---

[PATCH v5 0/6] Link off between frames for edp

Link Off Between Active Frames (LOBF) allows an eDP link to be turned Off and On durning long VBLANK durations without enabling any of the PSR/PSR2/PR modes of operation. Bspec: 71477 Note: Lobf need to be enabled adaptive sync fixed refresh mode where vmin = vmax = flipline, which will arise af

Re: [PATCH v2 5/6] drm/ci: skip driver specific tests

On Fri, May 17, 2024 at 02:55:01PM +0530, Vignesh Raman wrote: > Skip driver specific tests and skip kms tests for > panfrost driver since it is not a kms driver. > > Signed-off-by: Vignesh Raman > --- I didn't perform a through check, but generally looks good. Reviewed-by: Dmitry Baryshkov -

Re: [PATCH 0/7] drm/i915: DSC stuff

On Fri, 17 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Respect the VBT's edp_disable_dsc bit, and do a bunch > of refactoring around checking for DSC support. > > Also threw in a bonus cleanup to intel_dp_has_audio() > that caught my eye. The dropping of const here and there sticks

Re: [PATCH v2 4/6] drm/ci: uprev IGT

On Fri, May 17, 2024 at 02:55:00PM +0530, Vignesh Raman wrote: > test-list.txt and test-list-full.txt are not generated for > cross-builds and they are required by drm-ci for testing > arm32 targets. > > This is fixed in igt-gpu-tools. So uprev IGT to include the > commit which fixes this issue. D

Re: [PATCH v2 3/6] drm/ci: build virtual GPU driver as module

On Fri, May 17, 2024 at 02:54:59PM +0530, Vignesh Raman wrote: > With latest IGT, the tests tries to load the module and it > fails. So build the virtual GPU driver for virtio as module. Why? If the test fails on module loading (if the driver is built-in) then it's the test that needs to be fixed,

Re: [PATCH 7/7] drm/i915: Remove bogus MST check in intel_dp_has_audio()

On Fri, 17 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > No idea what this MST checks is doing in intel_dp_has_audio(). > Looks completely pointless, so get rid of it. 2e775f2d41ef ("drm/i915/display: update intel_dp_has_audio to support MST") 6297ee90f682 ("drm/i915/display: configur

Re: [PATCH v2 2/6] drm/ci: generate testlist from build

On Fri, May 17, 2024 at 02:54:58PM +0530, Vignesh Raman wrote: > Stop vendoring the testlist into the kernel. Instead, use the > testlist from the IGT build to ensure we do not miss renamed > or newly added tests. > > Signed-off-by: Vignesh Raman > --- > > v2: > - Fix testlist generation for a

Re: [PATCH 2/7] drm/i915: Extract intel_dp_has_dsc()

On Fri, 17 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Extract a helper to check whether the source+sink combo > supports DSC. That basic check is needed both during mode > validation and compute config. We'll also need to add extra > checks to both places, so having a single place f

Re: [PATCH v2 1/6] drm/ci: uprev mesa version

On Fri, May 17, 2024 at 02:54:57PM +0530, Vignesh Raman wrote: > zlib.net is not allowing tarball download anymore and results > in below error in kernel+rootfs_arm32 container build, > urllib.error.HTTPError: HTTP Error 403: Forbidden > urllib.error.HTTPError: HTTP Error 415: Unsupported Media Typ

✓ Fi.CI.BAT: success for Ultrajoiner basic functionality series

== Series Details == Series: Ultrajoiner basic functionality series URL : https://patchwork.freedesktop.org/series/133800/ State : success == Summary == CI Bug Log - changes from CI_DRM_14784 -> Patchwork_133800v1 Summary --- **SUCCE

Re: [PATCH] drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL/DG2+

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Bspec lists the mas TMDS bitrate as 6 Gbps on ADL/DG2. *max There's also ADL-S with display 12 and 6 Gbps support? BR, Jani. > Bump our limit to match. > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/i

✗ Fi.CI.CHECKPATCH: warning for Ultrajoiner basic functionality series

== Series Details == Series: Ultrajoiner basic functionality series URL : https://patchwork.freedesktop.org/series/133800/ State : warning == Summary == Error: dim checkpatch failed f1c5de795401 drm/i915: Rename all bigjoiner to joiner -:200: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match

Re: [PATCH 2/2] drm/i915/hdcp: Check mst_port to determine connector type

On Mon, May 20, 2024 at 06:58:19AM +0300, Kandpal, Suraj wrote: > > > > -Original Message- > > From: Deak, Imre > > Sent: Friday, May 17, 2024 6:19 PM > > To: Kandpal, Suraj > > Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar > > ; Shankar, Uma > > ; Nautiyal, Ankit K > > S

Re: [PATCH 1/5] drm/i915: Rename all bigjoiner to joiner

On Mon, 20 May 2024, Stanislav Lisovskiy wrote: > Lets unify both bigjoiner and ultrajoiner under simple "joiner" name, > because in future we might have multiple configurations, involving > multiple bigjoiners, ultrajoiner, however it is possible to use > same api for handling both. If you're do

✗ Fi.CI.BAT: failure for Fixes in hdcp remote capability (rev3)

== Series Details == Series: Fixes in hdcp remote capability (rev3) URL : https://patchwork.freedesktop.org/series/133047/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14784 -> Patchwork_133047v3 Summary --- **FAILU

Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition

On Mon, 2024-05-20 at 12:37 +0300, Jani Nikula wrote: > On Mon, 20 May 2024, Jani Nikula wrote: > > On Thu, 16 May 2024, Ville Syrjala > > wrote: > > > From: Ville Syrjälä > > > > > > PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 > > > range. > > > so using _MMIO_TRANS2() for

Re: [PATCH 05/13] drm/i915: Rename selective fetch plane registers

On Thu, 16 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Rename the selective fetch plane registers to match the spec. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +- > drivers/gpu/drm/i915/displ

Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition

On Mon, 20 May 2024, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: >> From: Ville Syrjälä >> >> PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x7 range. >> so using _MMIO_TRANS2() for it is not really correct. Also since this >> is a pipe register, and not present

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