== Series Details ==
Series: drm/i915/guc: Enable w/a 14019882105 for DG2 and MTL
URL : https://patchwork.freedesktop.org/series/134039/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14816 -> Patchwork_134039v1
Summary
== Series Details ==
Series: drm/i915/guc: Enable w/a 14019882105 for DG2 and MTL
URL : https://patchwork.freedesktop.org/series/134039/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/guc: Enable w/a 14019882105 for DG2 and MTL
URL : https://patchwork.freedesktop.org/series/134039/
State : warning
== Summary ==
Error: dim checkpatch failed
963da89c742d drm/i915/guc: Enable w/a 14019882105 for DG2 and MTL
-:46: WARNING:AVOID_BUG: Do not
From: John Harrison
Enable another workaround that is implemented inside the GuC.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 32 ---
2 files changed, 21 insertions(+), 12 deletions(-)
d
The WA should be extended to cover VDBOX engine. We found that
28-channels 1080p VP9 encoding may hit this issue.
v3: update the WA number and explain the reason why
this workaround is needed
v2: add WA number
v1: initial version
Signed-off-by: Chen, Angus
---
drivers/gpu/drm/i915/gt/intel_
== Series Details ==
Series: drm/i915: Fix SEL_FETCH_{SIZE,OFFSET} registers
URL : https://patchwork.freedesktop.org/series/134026/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14816 -> Patchwork_134026v1
Summary
---
On 2024-05-23 12:45:34 [+0300], Jani Nikula wrote:
>
> Thanks for testing! I suggest filing an issue at [1], attaching dmesg
> from boot with drm.debug=14 module parameter set.
>
> Cc: xe driver maintainers.
Thanks. Submitted as [0]. No idea how to Cc someone there.
[0] https://gitlab.freedeskto
== Series Details ==
Series: drm/i915: Fix SEL_FETCH_{SIZE,OFFSET} registers
URL : https://patchwork.freedesktop.org/series/134026/
State : warning
== Summary ==
Error: dim checkpatch failed
f0f015e3695b drm/i915: Fix SEL_FETCH_{SIZE,OFFSET} registers
-:33: WARNING:LONG_LINE: line length of 11
On Fri, May 24, 2024 at 01:26:41PM +0200, Andi Shyti wrote:
> Hi,
>
> > > On Mon, May 13, 2024 at 02:19:17PM +, Chen, Angus wrote:
> > > > The WA should be extended to cover VDBOX engine. We found that
> > > > 28-channels 1080p VP9 encoding may hit this issue.
> > > >
> > > > Signed-off-by: C
From: Ville Syrjälä
Fix up the SEL_FETCH_{SIZE,OFFSET} registers. A classic
copy-paste fail on my part.
I even had a small test to confirm that the old and new register
offsets match, but somehow I must have screwed things up when
running it, and likely just ended up comparing the old defines
ag
On Fri, May 24, 2024 at 01:58:53AM +0200, Andi Shyti wrote:
> Following the guidelines it takes 3 seconds to perform an FLR
> reset. Let's give it a bit more slack because this time can
> change depending on the platform and on the firmware
But did we see any issue with that?
if that changes per
On Fri, May 24, 2024 at 11:17:32AM +0300, Jani Nikula wrote:
> On Thu, 23 May 2024, Rodrigo Vivi wrote:
> > On Wed, May 22, 2024 at 08:33:42PM +0300, Jani Nikula wrote:
> >> We'll need to start identifying the platforms independently in display
> >> code in order to break free from the i915 and xe
On Wed, May 22, 2024 at 06:44:40AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Fix audio component initialization
> URL : https://patchwork.freedesktop.org/series/133882/
> State : success
Thanks for the review, patch is pushed to drm-intel-next with the
correct Fixes:
Hi,
> > On Mon, May 13, 2024 at 02:19:17PM +, Chen, Angus wrote:
> > > The WA should be extended to cover VDBOX engine. We found that
> > > 28-channels 1080p VP9 encoding may hit this issue.
> > >
> > > Signed-off-by: Chen, Angus
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c |
== Series Details ==
Series: Implement CMRR Support (rev9)
URL : https://patchwork.freedesktop.org/series/126443/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14815 -> Patchwork_126443v9
Summary
---
**FAILURE**
S
== Series Details ==
Series: Implement CMRR Support (rev9)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Implement CMRR Support (rev9)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
569f89bc8d2a drm/i915: Define and compute Transcoder CMRR registers
-:48: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'na
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +
1 file changed, 9 insert
Set cmrr.enable flag during intel_vrr_compute_config.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 07be70f7c536..a981c8384f91
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/dr
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame dro
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enab
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based o
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
with VRR timing generator or not. Make CMRR as s
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
Signed-off-by: Mitul Golani
Reviewed-by: Arun R Murthy
---
include/drm/display/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display/
Hello. I am graduate student at Korea University studying Intel GPU.
The functionality I need is to find out the 'context identifier' that was
just switched-out when a (or specific) context is switched-in to an engine
(Render Engine etc.).
I'd like to implement such functionality, especially with
On Wed, May 22, 2024 at 02:40:56PM +0300, Ville Syrjälä wrote:
> On Wed, May 22, 2024 at 11:01:32AM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 21, 2024 at 09:09:16PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 21, 2024 at 11:25:31AM +0300, Lisovskiy, Stanislav wrote:
> > > > On Mon, May 2
On Thu, 23 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Eliminate the crtc_state->state footgun from intel_color_check(),
> and hide some mundane C8 plane details inside it.
On the series,
Reviewed-by: Jani Nikula
>
> Ville Syrjälä (3):
> drm/i915: Plumb the entire atomic state
On Thu, 23 May 2024, Jani Nikula wrote:
> On Thu, 23 May 2024, Ville Syrjälä wrote:
>> On Thu, May 23, 2024 at 03:59:44PM +0300, Jani Nikula wrote:
>>> Avoid the implicit dev_priv local variable use, and pass dev_priv
>>> explicitly to the PIPEGCMAX register macro.
>>>
>>> Signed-off-by: Jani Ni
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 24, 2024 11:49 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Kahola, Mika
> Subject: Re: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
>
> On Fri, 2024-05-24 at 05:55 +, Manna, Animesh
On Thu, 23 May 2024, Rodrigo Vivi wrote:
> On Wed, May 22, 2024 at 08:33:42PM +0300, Jani Nikula wrote:
>> We'll need to start identifying the platforms independently in display
>> code in order to break free from the i915 and xe IS_()
>> macros. This is fairly straightforward, as we already ident
On Fri, 2024-05-24 at 05:59 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Tuesday, May 21, 2024 2:17 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v2 04/17] drm/i91
On Fri, 2024-05-24 at 05:53 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Tuesday, May 21, 2024 2:17 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v2 00/17] Panel R
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