== Series Details ==
Series: drm/i915/display: Update vtotal math to address 32b build (rev2)
URL : https://patchwork.freedesktop.org/series/134737/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14922 -> Patchwork_134737v2
Hi @De Marchi, Lucas
> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, June 12, 2024 10:02 AM
> To: Golani, Mitulkumar Ajitkumar
> Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [RFC] drm/i915/display: Update vtotal math to address 32b b
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: a957267fa7e9159d3d2ee1421359ebf228570c68 Add linux-next specific
files for 20240611
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202406111949.9wfztbkm-...@intel.com
https
Fix vtotal division calculation which works for 32b systems.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
1 file chan
On Wed, Jun 12, 2024 at 12:02:08AM GMT, Mitul Golani wrote:
Fix few divisions which may not work on 32b builds.
Use DIV_ROUND_UP, with that expecting deviate params
from +/- 1 accuracy in value.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Signed-off-by: Mitul Golani
---
Hi all,
After merging the drm-intel tree, today's linux-next build (i386
defconfig) failed like this:
x86_64-linux-gnu-ld: drivers/gpu/drm/i915/display/intel_vrr.o: in function
`intel_vrr_compute_config':
intel_vrr.c:(.text+0x4e4): undefined reference to `__udivdi3'
Caused by commit
1676ecd3
On Tue, Jun 11, 2024 at 06:12:20PM GMT, Rodrigo Vivi wrote:
On Tue, Jun 11, 2024 at 11:45:17PM +0200, Michal Wajdeczko wrote:
On 11.06.2024 22:32, John Harrison wrote:
> On 6/11/2024 07:30, Michal Wajdeczko wrote:
>> There are many GuC ABI definitions named in the same way by the i915
>> and X
Hi all,
After merging the drm-intel tree, today's linux-next build (htmldocs)
produced this warning:
include/drm/display/drm_dp_helper.h:127: warning: Function parameter or struct
member 'target_rr_divider' not described in 'drm_dp_as_sdp'
Introduced by commit
a20c6d954d75 ("drm/dp: Add refr
On Tue, Jun 11, 2024 at 05:14:26PM +0200, Sebastian Andrzej Siewior wrote:
> On 2024-06-11 14:06:00 [+0100], Tvrtko Ursulin wrote:
> >
> > Hi Sebastian,
> Hi Tvrtko,
>
> > Previous CI results have unfortunately expired by now. I have tried
> > re-queuing it but it also does not apply any longer s
On Fri, Apr 05, 2024 at 04:18:27PM +0200, Sebastian Andrzej Siewior wrote:
> intel_guc_send_busy_loop() looks at in_atomic() and irqs_disabled() to
> decide if it should busy-spin while waiting or if it may sleep.
> Both checks will report false on PREEMPT_RT if sleeping spinlocks are
> acquired le
On Tue, Jun 11, 2024 at 11:45:17PM +0200, Michal Wajdeczko wrote:
>
>
> On 11.06.2024 22:32, John Harrison wrote:
> > On 6/11/2024 07:30, Michal Wajdeczko wrote:
> >> There are many GuC ABI definitions named in the same way by the i915
> >> and Xe drivers, preventing proper generation of the docu
On 11.06.2024 22:32, John Harrison wrote:
> On 6/11/2024 07:30, Michal Wajdeczko wrote:
>> There are many GuC ABI definitions named in the same way by the i915
>> and Xe drivers, preventing proper generation of the documentation.
>>
>> Promote GuC ABI definitions to shared location that can be u
On 6/11/2024 07:30, Michal Wajdeczko wrote:
There are many GuC ABI definitions named in the same way by the i915
and Xe drivers, preventing proper generation of the documentation.
Promote GuC ABI definitions to shared location that can be used by
both drivers and can be included in documentation
== Series Details ==
Series: drm/i915/display: Update vtotal math to address 32b build
URL : https://patchwork.freedesktop.org/series/134737/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14921 -> Patchwork_134737v1
Summary
Fix few divisions which may not work on 32b builds.
Use DIV_ROUND_UP, with that expecting deviate params
from +/- 1 accuracy in value.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++
1
== Series Details ==
Series: drm/i915/dp_mst: Fix DSC input BPP computation
URL : https://patchwork.freedesktop.org/series/134726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14920 -> Patchwork_134726v1
Summary
---
The branch or sink device decompressing a stream may have a limitation
on the input/uncompressed BPP, which is lower than the base line BPP
(determined by the sink's EDID). In some cases a stream with an input
BPP higher than this limit will be converted automatically by the device
decompressing th
== Series Details ==
Series: Promote GuC ABI headers to shared location
URL : https://patchwork.freedesktop.org/series/134723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14919 -> Patchwork_134723v1
Summary
---
**S
== Series Details ==
Series: Promote GuC ABI headers to shared location
URL : https://patchwork.freedesktop.org/series/134723/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Promote GuC ABI headers to shared location
URL : https://patchwork.freedesktop.org/series/134723/
State : warning
== Summary ==
Error: dim checkpatch failed
daf8e761d0ce drm/xe/guc: Promote GuC ABI headers to shared location
-:14: WARNING:FILE_PATH_CHANGES: added,
On 2024-06-11 14:06:00 [+0100], Tvrtko Ursulin wrote:
>
> Hi Sebastian,
Hi Tvrtko,
> Previous CI results have unfortunately expired by now. I have tried
> re-queuing it but it also does not apply any longer so I'm afraid you will
> have to respin before anyone can see the results.
No worries, I
On Tue, Jun 11, 2024 at 04:30:01PM GMT, Michal Wajdeczko wrote:
rename drivers/gpu/drm/{xe => intel/guc}/abi/guc_actions_sriov_abi.h (100%)
rename drivers/gpu/drm/{xe => intel/guc}/abi/guc_communication_ctb_abi.h (98%)
rename drivers/gpu/drm/{xe => intel/guc}/abi/guc_communication_mmio_abi.h (100
On 6/11/2024 3:58 PM, Tvrtko Ursulin wrote:
On 10/06/2024 10:24, Nirmoy Das wrote:
Hi Andi,
On 6/7/2024 4:51 PM, Andi Shyti wrote:
The forcewake count and domains listing is multi process critical
and the uncore provides a spinlock for such cases.
Lock the forcewake evaluation section in t
== Series Details ==
Series: drm/i915/dsb: DSB prep stuff
URL : https://patchwork.freedesktop.org/series/134719/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14919 -> Patchwork_134719v1
Summary
---
**SUCCESS**
No
Some KLVs were not used by the Xe driver, but are used by the i915.
Add scheduling policy update key and another workaround key.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/intel/guc/abi/guc_klvs_abi.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/intel/guc/
GuC ABI definitions are not strictly tied to the i915 driver.
Move them to a separate section.
Signed-off-by: Michal Wajdeczko
---
Documentation/gpu/drivers.rst | 1 +
Documentation/gpu/guc.rst | 16
Documentation/gpu/i915.rst| 9 -
3 files changed, 17 insertio
Move SR-IOV GuC ABI definitions to shared location and include
them in the generated GuC documentation chapter.
Signed-off-by: Michal Wajdeczko
---
Documentation/gpu/guc.rst | 7 +++
.../gpu/drm/{xe => intel/guc}/abi/guc_actions_sriov_abi.h | 0
.../gpu/drm/
We no longer need to maintain some of the GuC ABI definitions
inside the i915 driver as the shared one are exactly the same.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/Makefile | 5 +
.../gt/uc/abi/guc_communication_ctb_abi.h | 170 ---
.../gt/uc/abi/g
Add missing definition of the CTB_STATUS_UNUSED bit.
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/intel/guc/abi/guc_communication_ctb_abi.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/intel/guc/abi/guc_communication_ctb_abi.h
b/drivers/gpu/drm/intel/guc/abi/guc_
For documentation purposes, use shared GuC ABI definitions instead
of local i915 definitions.
Signed-off-by: Michal Wajdeczko
---
Documentation/gpu/guc.rst | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/gpu/guc.rst b/Documentation/gpu/guc.rst
index b0fc
GuC ABI definitions do not have to be the Xe driver specific.
Move them to shared location for later reuse by the i915 driver.
While at it, fixup few improper kernel-doc annotations.
Signed-off-by: Michal Wajdeczko
---
.../{xe => intel/guc}/abi/guc_communication_ctb_abi.h | 0
.../{xe => intel
There are many GuC ABI definitions named in the same way by the i915
and Xe drivers, preventing proper generation of the documentation.
Promote GuC ABI definitions to shared location that can be used by
both drivers and can be included in documentation.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Luca
Hi Angus,
On Fri, May 24, 2024 at 05:33:49PM +, Chen, Angus wrote:
> The WA should be extended to cover VDBOX engine. We found that
> 28-channels 1080p VP9 encoding may hit this issue.
>
> v3: update the WA number and explain the reason why
> this workaround is needed
> v2: add WA number
== Series Details ==
Series: drm/i915/dsb: DSB prep stuff
URL : https://patchwork.freedesktop.org/series/134719/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dsb: DSB prep stuff
URL : https://patchwork.freedesktop.org/series/134719/
State : warning
== Summary ==
Error: dim checkpatch failed
30ef78394aeb drm/i915: Extract intel_crtc_arm_vblank_event()
9c42649bdcc3 drm/i915: Add async flip tracepoint
-:96: CHECK:
On 10/06/2024 10:24, Nirmoy Das wrote:
Hi Andi,
On 6/7/2024 4:51 PM, Andi Shyti wrote:
The forcewake count and domains listing is multi process critical
and the uncore provides a spinlock for such cases.
Lock the forcewake evaluation section in the fw_domains_show()
debugfs interface.
Signe
Hi Daniele,
thanks for checking this patch.
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 0eaa1064242c..1181043bc5e9 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm
Hi Rodrigo,
...
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > index 4fcba42cfe34..0437fd8217e0 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > @@ -7
== Series Details ==
Series: Panel Replay eDP support (rev8)
URL : https://patchwork.freedesktop.org/series/133684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14919 -> Patchwork_133684v8
Summary
---
**SUCCESS**
From: Ville Syrjälä
The ATS faults have something to do with some new iommu stuff
on mtl+. Document that the relevant DSB interrupt bits aren't
valid for earlier platforms.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb_regs.h | 4 ++--
1 file changed, 2 insertions(+),
From: Ville Syrjälä
DSB_STATUS bit 16 is supposed to be a sticky bit informing us whether
the DSB was idle or not when the pipe's delayed vblank (when double
buffered registers latch) occurred. Unfortunately it turns out this
is a level triggred signal, ie. the bit will be set whenever the
DSB is
From: Ville Syrjälä
intel_crtc.c doens't need intel_dsb.h so don't include it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
in
From: Ville Syrjälä
The future direction will be to mainly use intel_display
rather than i915 in the display code. Start on that path
for the DSB code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 52
1 file changed, 26 insertions(+), 26
From: Ville Syrjälä
As we extend the use of DSB for critical pipe/plane register
programming, it'll be nice to have an escape valve at hand,
in case things go very poorly. To that end, add a i915.enable_dsb
modparam by which we can force the driver to take the pure mmio
path instead.
Signed-off-
From: Ville Syrjälä
The DSB code will need to examine both the old and new crtc
states. Pass in the whole atomic state so we can dig up
what we need.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 11 +++
From: Ville Syrjälä
We'll have need to examine both the old and new crtc states in
intel_color_prepare_commit(), so let's just pass in the whole
atomic state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 11 ---
drivers/gpu/drm/i915/display/intel_colo
From: Ville Syrjälä
The DSB code will need to know the hardware's idea of vertical
active, as that is also what defines the start of undelayed
vblank. Introduce a helper that gives us that information,
in line with the other intel_mode_v*() functions.
Signed-off-by: Ville Syrjälä
---
drivers/g
From: Ville Syrjälä
Add a tracepoint to see exactly when async flips complete.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_display_irq.c | 1 +
.../drm/i915/display/intel_display_trace.h| 23 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/
From: Ville Syrjälä
Add a separate tracepoint for async flips vs. sync plane updates
to make it a bit easier to figure out what is happening.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 22 +++
.../gpu/drm/i915/display/intel_atomic_plane.h | 4
From: Ville Syrjälä
We'll need to arm the vblank event also from the future
DSB based codepath. Extract the function that does the
whold dance for us.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 29 +++
drivers/gpu/drm/i915/display/intel_crt
From: Ville Syrjälä
More prep work extracted from my upcoming DSB based plane
programming series.
Ville Syrjälä (11):
drm/i915: Extract intel_crtc_arm_vblank_event()
drm/i915: Add async flip tracepoint
drm/i915: Add flip done tracepoint
drm/i915: Introduce intel_mode_vdisplay()
drm/i91
== Series Details ==
Series: Panel Replay eDP support (rev8)
URL : https://patchwork.freedesktop.org/series/133684/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: war
== Series Details ==
Series: drm/i915/display: Send vrr vsync params whne vrr is enabled (rev2)
URL : https://patchwork.freedesktop.org/series/134714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14919 -> Patchwork_134714v2
Hi Sebastian,
On 05/06/2024 11:01, Sebastian Andrzej Siewior wrote:
On 2024-04-05 16:18:18 [+0200], To intel-gfx@lists.freedesktop.org wrote:
Hi,
The following patches are from the PREEMPT_RT queue. It is mostly about
disabling interrupts/preemption which leads to problems. Unfortunately
…
On 6/11/2024 5:35 PM, Mitul Golani wrote:
Compute trans vrr vsync params only when either VRR or CMRR
is enabled.
Fixes: 5922f45329cd ("drm/i915/display: Compute vrr vsync params")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
---
driv
== Series Details ==
Series: drm/i915/display: Send vrr vsync params whne vrr is enabled
URL : https://patchwork.freedesktop.org/series/134714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14919 -> Patchwork_134714v1
Summa
== Series Details ==
Series: drm/i915/display: Send vrr vsync params whne vrr is enabled
URL : https://patchwork.freedesktop.org/series/134714/
State : warning
== Summary ==
Error: dim checkpatch failed
711332181393 drm/i915/display: Send vrr vsync params whne vrr is enabled
-:26: CHECK:PARENT
Scanline indication needs to be checked and configure for both PSR2 and
Panel Replay Selective Update. Move this check to
intel_sel_update_config_valid.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d.
We want to notice possible issues faced with PSR2 Region Early Transport as
early as possible -> let's revert patch disabling Region Early Transport by
default. Also eDP 1.5 Panel Replay requires Early Transport.
Signed-off-by: Jouni H
Add new debug bit to be used with i915_edp_psr_debug debugfs
interface. This can be used to disable Panel Replay.
v2: ensure that fastset is performed when the bit changes
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/i
Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake
if panel supports it despite psr_enable value. Prevent SU Region Early
Transport if psr_enable is set to than -1 which is the default.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 13 +
There are couple of bits in PSR2_CTL which needs to be written in case of
eDP Panel Replay
Bspec: 68920
v2: use boolean instead of assuming eDP Panel Replay mean Early Transport
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 13 +
1 file changed, 13 in
If enable_psr module parameter is set as disabled, PSR1 or PSR2: Panel
Replay is disabled.
Signed-off-by: Jouni Högander
---
.../gpu/drm/i915/display/intel_display_params.c| 3 +--
drivers/gpu/drm/i915/display/intel_psr.c | 14 ++
2 files changed, 15 insertions(+), 2 d
Move Early Transport validity check to be performed for Panel Replay as
well and use Early Transport for eDP Panel Replay always.
v2:set crtc_state->enable_psr2_su_region_et directly (not in if block)
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++---
1 file
eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM
related things for Panel Replay as well.
Bspec: 68920
v4:
- do not move _compute_psr2_sdp_prior_scanline_indication
- move ALPM related checks to separate function
v3: move vblank check as well
v2: do not move Vblank >= PSR2
Intel_alpm_compute_params doesn't change crtc_state. Let's convert it as
const.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_alpm.c | 9 +
drivers/gpu/drm/i915/display/intel_alpm.h | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/
Take into account that 128b/132b Panel Replay is not supported on eDP.
Bspec: 68920
v2:
- make crtc_state as const
- add debug message to print out why Panel Replay is not possible
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 23 +--
1 fi
eDP1.5 allows Panel Replay on eDP as well. Take this into account when
enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register
accordingly.
v3:
- set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2
- PANEL_REPLAY_CONFIG2 is available in DP2.1 as well
v2: do not config
Take into account in Panel Replay compute config that HW will not allow PR
on eDP when HDCP enabled.
v2: add debug message to print out why Panel Replay is not possible
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 14 ++
1 file changed, 14 insertions
We are about to add more checks for Panel Replay. Due to that it makes
sense to add now Panel Replay compute config helper.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i
Display version >= 20 support eDP 1.5. Inform Panel Replay source support
on eDP for display version >= 20.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
Our HW doesn't support panel replay without Early Transport on eDP.
Bspec: 68920
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/
Wa 16021440873 is writing wrong register. Instead of PIPE_SRCSZ_ERLY_TPT
write CURPOS_ERLY_TPT.
Fixes: 29cdef8539c3 ("drm/i915/display: Implement Wa_16021440873")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check
panel support for this and prevent eDP panel replay if it doesn't exits.
Bspec: 68920
v2: use intel_alpm_aux_less_wake_supported
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
1 fil
Currently SU area width is set as MAX_INT. This is causing
problems. Instead set it as pipe src width.
Fixes: 86b26b6aeac7 ("drm/i915/psr: Carry su area in crtc_state")
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
This patch set is implementing eDP1.5 Panel Replay for Intel hw. Patch
to disable Region Early Transport by default is reverted as it is
needed by eDP Panel Replay.
v7:
- fix improper SU area width
- writing wrong register in Wa 16021440873
- disable Panel Replay if psr_enable is set != -1
Compute trans vrr vsync params only when either VRR or CMRR
is enabled.
Fixes: 5922f45329cd ("drm/i915/display: Compute vrr vsync params")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
1
Compute trans vrr vsync params only when either VRR or CMRR
is enabled.
Fixes: 5922f45329cd ("drm/i915/display: Compute vrr vsync params")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
1
On Mon, 2024-06-10 at 09:30 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Friday, June 7, 2024 7:19 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH 00/13] Panel Repla
Acked-by: Maarten Lankhorst
Den 2024-06-07 kl. 15:49, skrev Jouni Högander:
Add missing Panel Replay Enable SU Region ET bit defined in DP2.1
specification.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
include/drm/display/drm_dp.h | 1 +
1 file changed, 1 insertion(+)
dif
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