For the series:
Tested-by: Anuj Phogat
On Fri, Jun 28, 2019 at 5:07 AM Lionel Landwerlin
wrote:
>
> When a register is readonly there is not much we can tell about its
> value (apart from its default value?). This can be covered by tests
> exercising the value of the register fr
_INVOCATION_COUNT);
> + whitelist_reg(w, PS_INVOCATION_COUNT_UDW);
> break;
>
> case VIDEO_DECODE_CLASS:
> --
> 2.21.0.392.gf8f6787159e
>
> ___
> Intel-gfx mailing list
> Intel-g
On Sun, Apr 28, 2019 at 10:57 PM Tvrtko Ursulin
wrote:
>
>
> On 26/04/2019 17:58, Anuj Phogat wrote:
> >
> > Joonas,
> >
> > Mesa now applies this WA on ICL and we're not seeing any regressions in CI.
> > I tested Mesa with and without this patch
teCacheRedirectToCS:icl */
> + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> --
> 2.19.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freed
Joonas,
Mesa now applies this WA on ICL and we're not seeing any regressions in CI.
I tested Mesa with and without this patch applied to kernel. I don't see any
performance impact to Manhattan from GfxBench5. I'm little surprised to
see it's not really helping benchmark performance in Mesa.
Fixes multiple gpu hangs in piglit and vulkancts.
Both patches are:
Tested-by: Anuj Phogat
On Tue, Mar 5, 2019 at 4:48 AM Michał Winiarski
wrote:
>
> We assumed that the default preemption granularity is fine for ICL.
> Unfortunately, it turns out that some drivers don't support m
pdate the "workaround" naming.
>
> Signed-off-by: Michał Winiarski
> Cc: Anuj Phogat
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: Rafael Antognolli
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 9 +++--
> 1 file changed, 7 insertion
>
> _______
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Tested and Reviewed-by: Anuj Phogat
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
ests with Mesa i965
driver.
Cc: Radhakrishna Sripada
Signed-off-by: Anuj Phogat
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/
ests with Mesa i965
driver.
Cc: Radhakrishna Sripada
Signed-off-by: Anuj Phogat
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/
On Mon, Aug 6, 2018 at 9:14 AM Chris Wilson
wrote:
> Quoting Anuj Phogat (2018-08-03 20:24:09)
> >
> >
> > On Mon, Jul 30, 2018 at 5:07 AM Mika Kuoppala <
> mika.kuopp...@linux.intel.com>
> > wrote:
> >
> > The register for 0xe420 is unab
apology and humble request for
> Mesa folks to resurrect their state setup for this as they
> were on right track from start.
>
> This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.
>
> Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")
>
On Tue, May 29, 2018 at 5:47 AM, Lionel Landwerlin
wrote:
> FYI, we're setting this in Mesa :
> https://cgit.freedesktop.org/mesa/mesa/tree/src/intel/vulkan/genX_state.c#n130
> https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/drivers/dri/i965/brw_state_upload.c#n67
> I don't think we realized
> is not 100% clear and we don't need this info now anyway.
>
> v2: Use the new ICL_11 naming (Kelvin Gardiner).
> v3: Latest IDs as per BSpec (Oscar).
> v4: Make it compile (Paulo).
> v5: Remove comments (Lucas).
> v6: Multile rebases (Paulo).
> v7: Rebase (Mika)
>
On Thu, Jan 11, 2018 at 10:31 AM, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> On Thu, Jan 11, 2018 at 06:20:53PM +0000, Anuj Phogat wrote:
>> Rodrigo, Can you push it upstream for me?
>
> I just pushed the libdrm.
>
> Do I also need to push the mesa one?
>
No, I've
Rodrigo, Can you push it upstream for me?
Thanks
Anuj
On Wed, Jan 10, 2018 at 4:50 PM, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> On Wed, Jan 10, 2018 at 11:51:02PM +0000, Anuj Phogat wrote:
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> Cc: Anusha Srivatsa
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
intel/intel_chipset.h | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/intel/intel
On Thu, Sep 21, 2017 at 2:58 PM, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> In sync with 41693fd52373 ("drm/i915/kbl: Change a KBL pci id
> to GT2 from GT1.5")
>
> "See Mesa commit 9c588ff"
>
> Cc: Anuj Phogat <anuj.pho...@gmail.com>
>
On Wed, Sep 20, 2017 at 2:35 PM, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> On Wed, Sep 20, 2017 at 07:11:03PM +0000, Anuj Phogat wrote:
>> See Mesa commit 9c588ff
>>
>> Cc: Matt Turner <matts...@gmail.com>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.co
On Wed, Sep 20, 2017 at 2:34 PM, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> On Wed, Sep 20, 2017 at 08:31:26PM +0000, Anuj Phogat wrote:
>> See Mesa commit 9c588ff
>>
>> Cc: Matt Turner <matts...@gmail.com>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.co
See Mesa commit 9c588ff
Cc: Matt Turner <matts...@gmail.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
include/drm/i915_pciids.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/i915_pcii
On Wed, Sep 20, 2017 at 12:13 PM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
> Any comments on this one. Sent out v2 after dropping
> [PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids
Correction. Dropped patch for libdrm is:
[PATCH libdrm 1/2] intel: Remove unused Kaby
Dropping this patch.
On Mon, Sep 11, 2017 at 9:22 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
> These PCI IDs are not used in any Kabylake SKUs.
> See Mesa commits: ebc5ccf and b2dae9f
>
> Cc: Matt Turner <matts...@gmail.com>
> Cc: Rodrigo Vivi <rodrigo.v...@in
Any comments on this one. Sent out v2 after dropping
[PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids
On Mon, Sep 11, 2017 at 9:22 AM, Anuj Phogat <anuj.pho...@gmail.com> wrote:
> See Mesa commit 9c588ff
>
> Cc: Matt Turner <matts...@gmail.com>
> Cc: Rodrigo Vivi
See Mesa commit 9c588ff
Cc: Matt Turner <matts...@gmail.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
intel/intel_chipset.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/intel/intel
Dropping this patch.
On Tue, Sep 12, 2017 at 5:31 PM, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> On Tue, Sep 12, 2017 at 08:30:47PM +, Paulo Zanoni wrote:
>> Em Seg, 2017-09-11 às 10:10 -0700, Rodrigo Vivi escreveu:
>> > On Mon, Sep 11, 2017 at 04:11:33PM
On Mon, Sep 11, 2017 at 10:10 AM, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> On Mon, Sep 11, 2017 at 04:11:33PM +0000, Anuj Phogat wrote:
>> See Mesa commits: ebc5ccf and b2dae9f
>
> I believe we need to be in sync between multiple gfx stack components,
> but I don't
See Mesa commit 9c588ff
Cc: Matt Turner <matts...@gmail.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
intel/intel_chipset.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/intel/intel
These PCI IDs are not used in any Kabylake SKUs.
See Mesa commits: ebc5ccf and b2dae9f
Cc: Matt Turner <matts...@gmail.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
intel/intel_chipset.h | 26 --
See Mesa commits: ebc5ccf and b2dae9f
Cc: Matt Turner <matts...@gmail.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
include/drm/i915_pciids.h | 15 ++-
2 files cha
See Mesa commit 9c588ff
Cc: Matt Turner <matts...@gmail.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
include/drm/i915_pciids.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/i915_pcii
(dev) || \
> --
> 2.10.2
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
IDs cross checked in graphics specs.
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.c
behavior.
V2: Add a condition to avoid allocation from cache. (Ben)
V3: Make no changes in cache allocation strategy. Just update the alignment.
Update the aperture size estimate including the alignment.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Cc: Ben Widawsky b...@bwidawsk.net
---
intel
split sentences across the one-line header and the changelog. (Chris)
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Cc: Ben Widawsky b...@bwidawsk.net
Cc: Chris Wilson ch...@chris-wilson.co.uk
---
intel/intel_bufmgr_gem.c | 35 +--
1 file changed, 21 insertions
:52PM -0700, Anuj Phogat wrote:
On Mon, Jun 22, 2015 at 1:04 PM, Chris Wilson
ch...@chris-wilson.co.uk wrote:
On Mon, Jun 22, 2015 at 09:51:08PM +0200, Daniel Vetter wrote:
On Mon, Jun 22, 2015 at 11:47:02AM -0700, Anuj Phogat wrote:
and use it to initialize the align variable
On Mon, Jun 22, 2015 at 12:49 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Jun 22, 2015 at 10:21:46AM -0700, Ben Widawsky wrote:
On Fri, Jun 19, 2015 at 03:52:01PM -0700, Anuj Phogat wrote:
+Ben
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
Signed-off
On Mon, Jun 22, 2015 at 1:04 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Mon, Jun 22, 2015 at 09:51:08PM +0200, Daniel Vetter wrote:
On Mon, Jun 22, 2015 at 11:47:02AM -0700, Anuj Phogat wrote:
and use it to initialize the align variable in drm_intel_bo.
In case of YF/YS tiled
On Mon, Jun 22, 2015 at 10:01 AM, Ben Widawsky b...@bwidawsk.net wrote:
On Fri, Jun 19, 2015 at 03:50:44PM -0700, Anuj Phogat wrote:
+Ben.
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
and use it to initialize the align variable in drm_intel_bo.
In case of YF
behavior.
V2: Add a condition to avoid allocation from cache. (Ben)
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Cc: Ben Widawsky b...@bwidawsk.net
---
intel/intel_bufmgr_gem.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b
+Ben.
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
and use it to initialize the align variable in drm_intel_bo.
In case of YF/YS tiled buffers libdrm need not know about the tiling
format because these buffers don't have hardware support to be tiled
or detiled
+Ben
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index
On Wed, Jun 10, 2015 at 1:47 AM, Damien Lespiau
damien.lesp...@intel.com wrote:
On Tue, Jun 09, 2015 at 02:59:33PM -0700, Anuj Phogat wrote:
This patch is on the list for 8 weeks now. Please take a look so I can push
it upstream.
Could I suggest you nominate a mesa team member working on SKL
On Wed, May 20, 2015 at 2:01 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
and use it to initialize the align variable in drm_intel_bo.
In case of YF/YS tiled buffers libdrm need not know about the tiling
format because
On Wed, May 20, 2015 at 2:01 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
and use it to initialize the align variable in drm_intel_bo.
In case of YF/YS tiled buffers libdrm need not know about the tiling
format because these buffers don't have hardware support to be tiled
or detiled through
On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 51d87ae
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 51d87ae..92701a5 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
behavior.
Cc: Kristian Høgsberg k...@bitplanet.net
Cc: Damien Lespiau damien.lesp...@intel.com
Cc: Daniel Vetter dan...@ffwll.ch
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/intel
On Tue, Mar 31, 2015 at 11:11 PM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Mar 31, 2015 at 06:57:07PM +0100, Damien Lespiau wrote:
On Tue, Mar 31, 2015 at 10:49:22AM -0700, Anuj Phogat wrote:
On Tue, Mar 31, 2015 at 7:26 AM, Damien Lespiau
damien.lesp...@intel.com wrote:
On Mon, Mar
On Tue, Mar 31, 2015 at 7:26 AM, Damien Lespiau
damien.lesp...@intel.com wrote:
On Mon, Mar 30, 2015 at 02:00:07PM -0700, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
On Tue, Mar 31, 2015 at 7:28 AM, Damien Lespiau
damien.lesp...@intel.com wrote:
On Mon, Mar 30, 2015 at 02:00:08PM -0700, Anuj Phogat wrote:
This is required due to new macros added to i915_drm.h.
These macros are used by i965 driver.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
Hi
On Tue, Mar 31, 2015 at 6:17 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Mon, Mar 30, 2015 at 02:00:04PM -0700, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
include/drm/i915_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/i915_drm.h b
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
include/drm/i915_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index ded43b1..a6c167c 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -842,6 +842,8 @@ struct
Series is available at:
https://github.com/aphogat/drm.git, branch: tiling-yf-ys
Anuj Phogat (5):
i965/skl: Add macros for Yf/Ys tiling formats
i965/skl: Move tile_width computations out of
drm_intel_gem_bo_tile_pitch
i965/skl: Set tile width and height for YF/YS tiling
Align YS tile
I'm still passing tiling=I915_TILING_Y in drm_intel_gem_bo_alloc_internal()
in case of YF/YS tiling. Passing tiling=I915_TILING_{YF,YS} causes bo
allocation failure. Any advice what's the right thing to do here?
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 49
This is required due to new macros added to i915_drm.h.
These macros are used by i965 driver.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 155d577..17c0e71 100644
This will be utilized by next patch in this series.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 23 ++-
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 5a67f53
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
intel/intel_bufmgr_gem.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 7c50e26..775a9f9 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
On Mon 27 Feb 2012 11:45:46 AM PST, Anuj Phogat wrote:
This patch handles a case when mapping a large texture fails
in drm_intel_gem_bo_map_gtt(). These changes avoid assertion
failure later in the driver as reported in following bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=44970
https
-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 26 ---
src/mesa/drivers/dri/intel/intel_regions.c |7 -
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src
with another patch which I posted on mesa-dev
(intel: Fix a case when mapping large texture fails) resolve
above mentioned bugs. Recently posted piglit test case (large-textures)
also passes with these patches.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
This fix doesn't limit developers
width, height parameter of glTexImage2D() includes: texture image
width + 2 * border (if any). So when doing the texture size check
in _mesa_test_proxy_teximage() width and height should not exceed
maximum supported size for target texture type.
i.e. 1 (ctx-Const.MaxTextureLevels
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