> -Original Message-
> From: Jani Nikula
> Sent: Friday, October 21, 2022 1:47 AM
> To: Vivekanandan, Balasubramani
> ; Srivatsa, Anusha
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce
> HAS_CDCLK_SQUASH m
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15
No functional change. Introduce dg2_cdclk_squash_programming and
move squash_ctl register programming bits to this.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
1 file changed, 14
in terms of checking
if the platform supports them or not. With the changes introduced,
both are a display feature flag.
- Move code from bxt_set_cdclk() to make it more modularized
and easy to read and understand.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Anusha Srivatsa (4):
drm/
No functional change. Moving segments out to simplify
bxt_set_cdlck()
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git
No functional changes. Changing terminolgy in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, October 20, 2022 8:15 AM
> To: Vivekanandan, Balasubramani
>
> Cc: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl an
> -Original Message-
> From: Vivekanandan, Balasubramani
>
> Sent: Thursday, October 20, 2022 7:42 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and
> squash when changing
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, October 20, 2022 4:33 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/i915/display: Do both crawl and squash when
> changing cdclk
>
> On Thu, Oct 1
From: Patchwork
Sent: Thursday, October 13, 2022 9:57 PM
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/display:
Do both crawl and squash when changing cdclk
Patch Details
Series:
series starting with [1/2] drm
crawl capability checks.(Ville)
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 157 +
1 file changed, 128 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/d
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
---
drivers/gpu
the
previous debugs entries to reflect which firmware is needed
and if the needed firmware is loaded or not.
MTL needs both Pipe A and Pipe B DMC to be loaded
along with Main DMC.
BSpec: 49788
Cc: Lucas De Marchi
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
the
previous debugs entries to reflect which firmware is needed
and if the needed firmware is loaded or not.
MTL needs both Pipe A and Pipe B DMC to be loaded
along with Main DMC.
BSpec: 49788
Cc: Lucas De Marchi
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display
@ville.syrj...@linux.intel.com<mailto:ville.syrj...@linux.intel.com> The
mid_cdclk_config logic actually showing issues during cdclk sanitize
“cdclk 0 not valid for refclk abc”
Though that part logic should not be affected…..
Looking into it.
Anusha
From: Patchwork
Sent: Friday, Sep
check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 144 +
1 file changed, 116 insertions(
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
---
drivers/gpu
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, September 28, 2022 12:24 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for
> MTL
>
> On Wed, Sep 2
adding the cdclk table, align cdclk support with the
new cdclk_crawl_and_squash() introduced in previous patch.
BSpec: 65243
Cc: Radhakrishna Sripada
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 95 +-
1 file changed, 93 insertions(+), 2
check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 144 +
1 file changed, 116 insertions(
check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)
Signed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 144 +
1 file changed, 116 insertions(
ed-off-by: Anusha Srivatsa
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 121 -
1 file changed, 96 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a12e86
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, September 26, 2022 10:30 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> ; Vivi, Rodrigo ; Navare,
> Manasi D ; Roper, Matthew D
>
> Subject: Re: [PATCH 0/6]
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, September 23, 2022 12:04 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> ; Vivi, Rodrigo ; Navare,
> Manasi D ; Roper, Matthew D
>
> Subject: Re: [PATCH 0/6]
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, September 20, 2022 2:59 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> ; Vivi, Rodrigo
> Subject: Re: [PATCH 0/6] Introduce struct cdclk_step
>
> On Tue, Sep 2
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, September 20, 2022 1:20 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
> ; Vivi, Rodrigo
> Subject: Re: [PATCH 0/6] Introduce struct cdclk_step
>
> On Fri, Sep 1
> -Original Message-
> From: Jani Nikula
> Sent: Tuesday, September 20, 2022 12:27 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 6/6] drm/i915/display: Dump the new cdclk
> config values
>
> On Fri, 1
> -Original Message-
> From: Navare, Manasi D
> Sent: Monday, September 19, 2022 12:39 PM
> To: Jani Nikula
> Cc: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/6] drm/i915/display: Embed the new struct
> steps for sq
> -Original Message-
> From: Navare, Manasi D
> Sent: Monday, September 19, 2022 12:33 PM
> To: Jani Nikula
> Cc: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/6] drm/i915/display: add cdclk action struct
> to cdclk
Add a helper function to get stringify values of the
desired cdclk action and dump it with rest of the
cdclk config values
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git
Modularising steps and moving them out of
bxt_set_cdclk().
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915
Populate the new struct steps for the legacy modeset
case.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +-
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +-
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm
The struct has the action to be performed - squash, crawl
or modeset and the corresponding cdclk which is the desired
cdclk. This is the structure that gets populated during
atomic check once it is determined what the cdclk change looks
like
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm
Populate the new struct steps for squash case.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index
Populate the new struct steps for crawl case.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index
Cc: Rodrigo Vivi
Anusha Srivatsa (6):
drm/i915/display Add dg2_prog_squash_ctl() helper
drm/i915/display: add cdclk action struct to cdclk_config
drm/i915/display: Embed the new struct steps for squashing
drm/i915/display: Embed the new struct steps for crawling
drm/i915/display: Embed
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, September 14, 2022 2:43 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to
> intel_cdclk_state
>
> On
Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
v2: Move crawling steps to a switch case (anusha)
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c
Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
v2: Move squashing bits to switch case.(Anusha)
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c
to intel_cdclk_squash()
and intel_cdclk_crawl().
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 61 ++
1 file changed, 38 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index
This is a prep patch for what the rest of the series does.
Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display
this.
Anusha Srivatsa (4):
drm/i915/display: Add CDCLK actions to intel_cdclk_state
drm/i915/squash: s/intel_cdclk_can_squash/intel_cdclk_squash
drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
drm/i915/display: Add cdclk checks to atomic check
drivers/gpu/drm/i915/display
gt; On Wed, Jul 27, 2022 at 06:34:18PM -0700, Radhakrishna Sripada wrote:
> > From: Anusha Srivatsa
> >
> > MTL needs both Pipe A and Pipe B DMC to be loaded along with Main DMC.
> > Patch also adds
>
> That's true, but it's unrelated to this patch. intel_dmc_load_p
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Wednesday, July 27, 2022 6:34 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha
> Subject: [PATCH 06/23] drm/i915/mtl: Add PCH support
>
> Add support for Meteorpoint(MTP) PCH used with M
With the latest DMC in place, enabling DC5 on DG2.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915
With the latest DMC in place, enabling DC5 on DG2.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915
to intel_cdclk_squash()
and intel_cdclk_crawl().
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 108 +++--
1 file changed, 77 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display
Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++---
1 file changed, 11
Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 21 +++--
1 file changed, 11
This is a prep patch for what the rest of the series does.
Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display
: Matt Roper
Anusha Srivatsa (4):
drm/i915/display: Add CDCLK actions to intel_cdclk_state
drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash
drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
drm/i915/display: Add cdclk checks to atomic check
drivers/gpu/drm/i915/display
The intention is to check for squashing, crawling conditions
at atomic check phase and prepare for commit phase. This basically
means the in-flight cdclk state is available. intel_cdclk_can_squash(),
intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes
to accommodate this.
Anusha
Thanks Tvrtko :)
@Roper, Matthew D Did you have any other feedback on this patch?
Anusha
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Tuesday, July 26, 2022 1:59 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org; Ursulin, Tvrtko
> Subject: Re:
Cleanup the intel_phy_is_combo
to accommodate for cases where combo phy is not available.
v2: retain comment that explains DG2 returning false from
intel_phy_is_combo() (Arun)
Cc: Arun R Murthy
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Reviewed-by: Matt Roper
Reviewed-by: Arun R Murthy
@Ursulin, Tvrtko Is this wat you had in mind?
Anusha
> -Original Message-
> From: Srivatsa, Anusha
> Sent: Thursday, July 21, 2022 3:51 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Ursulin, Tvrtko
> ; Roper, Matthew D
>
> Subject
> -Original Message-
> From: Roper, Matthew D
> Sent: Thursday, July 21, 2022 1:50 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Murthy, Arun R
>
> Subject: Re: [PATCH] drm/i915/display: Cleanup intel_phy_is_combo()
>
> On Thu, Jul 2
gen11_gu_misc_irq_handler() and gen11_gu_misc_ack() do nothing tile
specific.
v2: gen11_gu_misc_irq_ack() tile agnostic like gen11_gu_misc_irq_handler()
(Tvrtko)
Cc: Tvrtko Ursulin
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_irq.c | 16
1 file
No functional change. Cleanup the intel_phy_is_combo
to accommodate for cases where combo phy is not available.
v2: retain comment that explains DG2 returning false from
intel_phy_is_combo() (Arun)
Cc: Arun R Murthy
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Wednesday, July 20, 2022 2:38 AM
> To: Roper, Matthew D ; Srivatsa, Anusha
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Pass drm_i915_private struct
> instead of gt for g
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, July 19, 2022 7:34 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/display: Cleanup
> intel_phy_is_combo()
>
> > > -Origina
> -Original Message-
> From: Murthy, Arun R
> Sent: Monday, July 18, 2022 8:32 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/display: Cleanup
> intel_phy_is_combo()
>
> > -Original Me
No functional change. Cleanup the intel_phy_is_combo
to accomodate for cases where combo phy is not available.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/gpu
gen11_gu_misc_irq_handler() does not do anything tile specific.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_irq.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index
treating each bit in the EU fuse register as a single EU instead of a
> pair of EUs, then that also cuts the number of potential EUs per subslice in
> half.
>
> Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes")
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivats
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, May 20, 2022 4:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Vudum,
> Lakshminarayana
> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Enable DC5
>
> On
Enable DC5 on dg2.
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
t; Bspec: 49193, 72486, 72487
>
> Signed-off-by: Imre Deak
Thanks for the patch.
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 89 ++-
> drivers/gpu/drm/i915/display/intel_dmc_regs.h | 74 +++
> 2 files changed,
Bspec has added some steps that check forDMC MMIO range before
programming them
v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean
Bspec has added some steps that check forDMC MMIO range before
programming them
v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
v4: Add FIXME (Rodrigo)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
v4: Add FIXME (Rodrigo)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
drivers/gpu
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
drivers/gpu
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
drivers/gpu
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Bspec has added some steps that check forDMC MMIO range before
programming them
v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean
> -Original Message-
> From: De Marchi, Lucas
> Sent: Tuesday, May 3, 2022 5:31 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org
> Subject: Re: [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Tue, May 03,
Bspec has added some steps that check forDMC MMIO range before
programming them
v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean
5 took only dc9 paths.
Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue
Cc: Rodrigo Vivi
Cc: Imre Deak
Anusha Srivatsa (1):
drm/i915/dmc: Load DMC on DG2
drivers/gpu/drm/i915/d
Add Support for DC states on Dg2.
v2: Add dc9 as the max supported DC states and disable DC5.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi (v1)
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4 +++-
drivers/gpu/drm/i915/display/intel_dmc.c
Bspec has added some steps that check forDMC MMIO range before
programming them
v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean
Bspec has added some steps that check forDMC MMIO range before
programming them
v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean
> -Original Message-
> From: De Marchi, Lucas
> Sent: Friday, April 29, 2022 1:50 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org
> Subject: Re: [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Fri, Apr 29,
> -Original Message-
> From: De Marchi, Lucas
> Sent: Tuesday, April 26, 2022 10:42 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org
> Subject: Re: [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Tue, Apr 26,
Bspec has added some steps that check forDMC MMIO range before
programming them
v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
BSpec: 49193
Cc:
Cc: Lucas De Marchi
Signed-off-by: Anusha
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Wednesday, April 20, 2022 12:09 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Vivi, Rodrigo ; Deak, Imre
> ; Gupta, Anshuman ;
> Srivatsa, Anusha
> Subject: [PATCH] drm/i915: Disable DC5 before going to DC9
will be very useful.
Thanks,
Anusha
From: Patchwork
Sent: Thursday, April 14, 2022 11:04 AM
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org
Subject: ✓ Fi.CI.BAT: success for drm/i915/dmc: Load DMC on DG2 (rev4)
Patch Details
Series:
drm/i915/dmc: Load DMC on DG2 (rev4)
URL:
https
From: Patchwork
Sent: Wednesday, April 13, 2022 1:01 PM
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/dmc: Load DMC on DG2
Patch Details
Series:
drm/i915/dmc: Load DMC on DG2
URL:
https://patchwork.freedesktop.org/series/102630/
State
Add Support for DC states on Dg2.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, April 6, 2022 10:46 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Wed, Apr 06, 2022 at
> -Original Message-
> From: De Marchi, Lucas
> Sent: Tuesday, April 5, 2022 11:03 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions
>
> On Tue, Apr 05, 2022 at
Bspec has added some steps that check for DMC MMIO range before
programming them.
v2: Fix for CI failure for v1
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 42
1 file changed, 42 insertions(+)
diff --git a/drivers
Bspec has added some steps that check for DMC MMIO range before
programming them.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 42
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
We need add some checks around DMC reloading to
prevents the rare possibility of some adversary
writing to a random mmio register
BSpec: 49193
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
---
.../drm/i915/display/intel_display_power.c| 23 +++
drivers/gpu/drm/i915
DG2 has same DC states as DG1 - upto DC5.
Bspec: 49193
Cc: Madhumitha Tolakanahalli Pradeep
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display
Add Support to load dmc v2.06
Cc: Madhumitha Tolakanahalli Pradeep
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display
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