>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, October 16, 2018 2:03 PM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Jani
>Nikula
>; Ville Syrjala
>Subject: Re: [PATCH v5 20/28] drm/i915/dp: Configur
>-Original Message-
>From: Navare, Manasi D
>Sent: Friday, October 5, 2018 4:23 PM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PATCH v5 20/28] drm
enabling FEC.
v2:
- Change commit message. Configure fec state after
link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)
v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
v4: rebased.
Cc: Gaurav K Singh
Cc
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915
/series/47514/
Tested on Odelia Board after applying the FEC workaround.
Anusha Srivatsa (6):
i915/dp/fec: Cache the FEC_CAPABLE DPCD register
i915/dp/fec: Check for FEC Support
drm/dp/fec: DRM helper for Forward Error Correction
drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
i915/dp/fec
: Manasi Navare
Cc: Dhinakaran Pandiyan
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dp.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8a0e0a0b26f6..318494afd14a 100644
changes (Gaurav)
- Use drm_dp_dpcd_readb instead of drm_dp_dpcd_read. (Jani)
v4:
- Avoid aux reads everytime, instead read cached
values of dpcd register (jani)
- Move helper to drm_dp_helper.h like other dsc
helpers.(Anusha)
Cc: Ville Syrjala
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 17 +
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
Suggested-by: Jani Nikula
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
>-Original Message-
>From: Josh Boyer [mailto:jwbo...@kernel.org]
>Sent: Monday, October 1, 2018 6:55 AM
>To: Srivatsa, Anusha
>Cc: Intel Graphics Development ; Kyle McMartin
>; Ben Hutchings
>Subject: Re: linux-firmware pull request(ICL:DMC)
>
>On Wed, Sep 2
/kernel/git/firmware/linux-firmware.git
ICL_DMC
for you to fetch changes up to 18c4c8a73e9af8cfb40b5bd1d8172b29c89a6908:
firmware/icl/dmc: Add v1.07 of DMC for Icelake (2018-09-26 11:46:41 -0700)
Anusha Srivatsa (1):
firmware
et after DC9 for Gen11+, as the
PPS regs are Always On
- Rebase against upstream changes
v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.
v6: (Anusha Srivatsa)
- rebased.Use INTEL_GEN consistently.
- Simplify the code (Rodrigo)
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off
Ping -
Can we have this blob merged to linux-firmware.git please?
Anusha
From: Srivatsa, Anusha
Sent: Friday, September 7, 2018 10:02 AM
To: intel-gfx@lists.freedesktop.org
Subject: FW: linux-firmware pull request(ICL:DMC)
Adding ML.
Anusha
From: Srivatsa, Anusha
Sent: Wednesday, September 5
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Thursday, September 13, 2018 1:14 PM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Manna, Animesh
>; Deak, Imre ; Ausmus,
>James
>Subject: Re: [PATCH] drm/i915/icl: Enable DC9 as lowest possible
Add missing MODULE_FIRMWARE while loading DMC ICL.
v2: Add Fixes tag. (Rodrigo)
Fixes: 4445930f1c4a ("firmware/dmc/icl: load v1.07 on icelake.")
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/d
We were using the default CFGCR0/1 instead of using
TBT specific CFGCR0 and CFGCR1 registers during
PLL sequence.
Add missing TBTPLL_CFGCR0/1 registers and plumb
them in the existing PLL sequence.
Cc: Paulo Zanoni
Cc: Jose Souza
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915
et after DC9 for Gen11+, as the
PPS regs are Always On
- Rebase against upstream changes
v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
Signed-off-by: James Ausmus
Signed-off-by: Anusha Srivatsa
---
drivers/
et after DC9 for Gen11+, as the
PPS regs are Always On
- Rebase against upstream changes
v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
Signed-off-by: James Ausmus
Signed-off-by: Anusha Srivatsa
---
drivers/
>-Original Message-
>From: Wajdeczko, Michal
>Sent: Monday, September 10, 2018 3:42 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Wajdeczko, Michal ; Spotswood, John A
>; Srivatsa, Anusha ;
>Lis, Tomasz ; Ceraolo Spurio, Daniele
>
>Subject: [CI v2 1/2] drm
uld document this somewhere.
>
>Well, there are still quite a few conditionals included, if you ask me.
>
>But if you see the MODULE_FIRMWARE as a separate patch as such a burden that
>we should make the assumptions, I can live with it. At least I know who to
>call in
>case there was
Adding ML.
Anusha
From: Srivatsa, Anusha
Sent: Wednesday, September 5, 2018 1:40 PM
To: jwbo...@kernel.org; b...@decadent.org.uk; k...@kernel.org
Subject: linux-firmware pull request(ICL:DMC)
Hi Josh,Ben,Kyle,
Please consider pulling the following i915 updates to linux-firmware.git
Add missing MODULE_FIRMWARE while loading DMC on Icelake.
Rebased on top of https://patchwork.freedesktop.org/patch/246153/
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Wednesday, September 5, 2018 12:31 PM
>To: Srivatsa, Anusha
>Cc: Deak, Imre ; Nikula, Jani ;
>intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
>Subject: Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on ic
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Monday, September 3, 2018 10:27 PM
>To: Deak, Imre
>Cc: Srivatsa, Anusha ; Nikula, Jani
>; intel-gfx@lists.freedesktop.org; Zanoni, Paulo R
>
>Subject: Re: [Intel-gfx] [PATCH 1/1] firmware/dmc/icl: load v1.07 on ic
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Singh, Gaurav K ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha ; Navare, Manasi D
>
>Subject: [PATCH v2 23/23] drm/i915/dp: Disable
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, August 6, 2018 12:41 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PATCH v3] drm/i915/dp: Configure Display stream splitt
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PATCH v2 20/23] drm/i915/dp: Populate DSC PPS SDP and sen
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Singh, Gaurav K ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha ; Navare, Manasi D
>
>Subject: [PATCH v2 17/23] drm/i915/dp: En
elgaumkar, Vinay ; Ye, Tony
>; Srivatsa, Anusha ; Mcgee,
>Jeff ; Argenziano, Antonio
>; Sundaresan, Sujaritha
>
>Subject: [PATCH 02/21] drm/i915/guc: Don't allow GuC submission on pre-Gen11
>
>Upcoming Gen11 GuC firmware requires new interface that is incompatible with
>existing p
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PATCH v2 19/23] drm/i915/dp: Use the existing write_infof
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, July 30, 2018 7:13 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Srivatsa,
>Anusha
>; Singh, Gaurav K ;
>Navare, Manasi D
>Subject: [PATCH
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Singh, Gaurav K ; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha ; Navare, Manasi D
>
>Subject: [PATCH v2 15/23] drm/i915/dsc: Defin
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, July 30, 2018 7:13 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Srivatsa,
>Anusha
>; Singh, Gaurav K ; dri-
>de...@lists.freedesktop.org; Na
>-Original Message-
>From: Harry Wentland [mailto:harry.wentl...@amd.com]
>Sent: Thursday, August 23, 2018 1:01 PM
>To: Navare, Manasi D ; intel-
>g...@lists.freedesktop.org
>Cc: Singh, Gaurav K ; dri-
>de...@lists.freedesktop.org; Jani Nikula ; Ville
>Sy
>-Original Message-
>From: Deak, Imre
>Sent: Tuesday, August 28, 2018 10:16 AM
>To: Yadav, Jyoti R
>Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
>; Saarinen, Jani
>Subject: Re: [PATCH] [intel-gfx] drm/i915/intel_csr.c Fix DMC FW Loading issue
>on ICL.
: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c| 7 +++
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1ec4f09c61f6..6d9d47322405
for you to fetch changes up to 50364020f96f8deb075830d9992899ba3a7babc7:
Merge remote-tracking branch 'official/master' (2018-08-27 17:24:49 -0700)
Anusha Srivatsa (7):
Merge remote-tracking branch 'official/master' into drm
>-Original Message-
>From: Navare, Manasi D
>Sent: Thursday, August 23, 2018 6:48 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Srivatsa, Anusha
>
>Subject: [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC
>engine
>
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, August 20, 2018 12:32 PM
>To: Jani Nikula
>Cc: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org; Ville Syrjala
>Subject: Re: [PATCH 1/5] drm/dp/fec: DRM helper for Forward Error Correction
>
>
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, August 20, 2018 12:32 PM
>To: Jani Nikula
>Cc: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org; Ville Syrjala
>Subject: Re: [PATCH 1/5] drm/dp/fec: DRM helper for Forward Error Correction
>
>
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, July 30, 2018 7:13 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Srivatsa,
>Anusha
>; Singh, Gaurav K ;
>Navare, Manasi D ; Vivi, Rodrigo
&
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Singh, Gaurav K
>; Jani Nikula ; Ville
>Syrjala ; Srivatsa, Anusha
>
>Subject: [PATCH v2 11/23] drm/i915/dp: Ad
This patch needs to now incorporate the newly added slice_row_per_frame
parameter in PPS_16.
Anusha
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Singh, Gau
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Singh, Gaurav K
>; Jani Nikula ; Ville
>Syrjala ; Srivatsa, Anusha
>; Pandiyan, Dhinakaran
>
>Subject: [PATCH v2 0
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Singh, Gaurav K
>; Jani Nikula ; Ville
>Syrjala ; Srivatsa, Anusha
>
>Subject: [PATCH v2 05/23] drm/i915/dp: Validate
Let us reuse the already defined has_csr check and not
redefine it.
Suggested-by: Imre Deak
Cc: Imre Deak
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm
cted and
>+usable" we
>+ * define a port as "connected" when it is not only connected, but also
>+when it
>+ * is usable by the rest of the driver. That maintains the old
>+assumption that
>+ * connected ports are usable, and avoids exposing to the users objects
>+
>-Original Message-
>From: Deak, Imre
>Sent: Wednesday, August 15, 2018 4:35 AM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Yadav, Jyoti R ;
>Vivi, Rodrigo ; Zanoni, Paulo R
>
>Subject: Re: [PATCH 1/1] firmware/dmc/icl: load v1.07 on icelake.
Add Support to load DMC on Icelake.
While at it, also add support to load the firmware
during system resume.
v2: load firmware during system resume.(Imre)
v3: enable has_csr for icelake.(Jyoti)
Cc: Jyoti Yadav
Cc: Imre Deak
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
/ master
for you to fetch changes up to d79b57351cda7cb91e79c61175f53946937f0bcd:
Merge remote-tracking branch 'official/master' (2018-08-13 21:25:53 -0500)
Anusha Srivatsa (9):
Merge remote-tracking branch 'official/master
/ master
for you to fetch changes up to d79b57351cda7cb91e79c61175f53946937f0bcd:
Merge remote-tracking branch 'official/master' (2018-08-13 21:25:53 -0500)
Anusha Srivatsa (9):
Merge remote-tracking branch 'official/master
/ master
for you to fetch changes up to d79b57351cda7cb91e79c61175f53946937f0bcd:
Merge remote-tracking branch 'official/master' (2018-08-13 21:25:53 -0500)
Anusha Srivatsa (9):
Merge remote-tracking branch 'official/master
From: "Srivatsa, Anusha"
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the contro
From: "Srivatsa, Anusha"
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
--
From: "Srivatsa, Anusha"
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
If FEC support exists, write to the FEC_READY bit
in the FEC_CONFIGURATION DPCD register.
v2: Mention External DP where ever FEC is
on top of:
https://patchwork.freedesktop.org/series/47514/
Srivatsa, Anusha (5):
drm/dp/fec: DRM helper for Forward Error Correction
i915/dp/fec: Check for FEC Support
drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
i915/dp/fec: Configure the Forward Error Correction bits.
drm/i915/fec
From: "Srivatsa, Anusha"
DP 1.4 has Forward Error Correction Support(FEC).
Add helper function to check if the sink device
supports FEC.
v2: Separate the helper and the code that uses the helper into
two separate patches. (Manasi)
v3:
- Move the code to drm_dp_helper.c (Manasi
From: "Srivatsa, Anusha"
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
Cc: Gaurav K
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff
>-Original Message-
>From: Yadav, Jyoti R
>Sent: Wednesday, August 1, 2018 10:34 PM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org; Zanoni, Paulo R
>Cc: Sarvela, Tomi P ; Vivi, Rodrigo
>; Zanoni, Paulo R ; intel-
>g...@lists.freedesktop.org
>Subj
>-Original Message-
>From: Sarvela, Tomi P
>Sent: Thursday, August 2, 2018 12:51 AM
>To: Vivi, Rodrigo ; Zanoni, Paulo R
>
>Cc: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org; Martin Peres
>Subject: Re: [Intel-gfx] [PATCH] firmware/dmc/icl: load v1.07 on i
to fetch changes up to 1e54a19c7a2c300aabb9ca69901dd94b1f6e5b70:
firmware/icl/dmc: Add DMC v1.07 for Icelake. (2018-07-30 15:13:45 -0700)
Anusha Srivatsa (5):
linux-firmware: Add GuC v11.98 for geminilake
linux-firmware: Add
Add Support to load DMC on Icelake.
While at it, also add support to load the firmware
during system resume.
v2: load firmware during system resume.(Imre)
Cc: Imre Deak
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c| 7
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Singh, Gaurav K
>; dri-de...@lists.freedesktop.org; Jani Nikula
>; Ville Syrjala ;
>Srivatsa, Anusha
>Subject: [PAT
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; Jani Nikula
>; Ville Syrjala ;
>Daniel
>Vetter ; Srivatsa, Anusha ;
>Singh, Gaurav K
>Subject: [PATCH v2 02/23]
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D ; dri-
>de...@lists.freedesktop.org; Jani Nikula ; Ville
>Syrjala ; Srivatsa, Anusha
>; Singh, Gaurav K
>Subject: [PAT
>-Original Message-
>From: Navare, Manasi D
>Sent: Monday, July 30, 2018 7:13 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: ville.syrj...@linux.intel.com; jani.nik...@linux.intel.com; Srivatsa,
>Anusha
>; Singh, Gaurav K ;
>Navare, Manasi D ; dri-
>de...@lis
to fetch changes up to 1e54a19c7a2c300aabb9ca69901dd94b1f6e5b70:
firmware/icl/dmc: Add DMC v1.07 for Icelake. (2018-07-30 15:13:45 -0700)
Anusha Srivatsa (5):
linux-firmware: Add GuC v11.98 for geminilake
linux-firmware: Add
Add Support to load DMC on Icelake.
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index cf9b600..393d419
For a TBT sequence, we need to set the IO type to TBT
in DDI_AUX_CTL.
v2: Avoid duplications.(Paulo)
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 26 +-
2 files changed, 18 insertions
Add missing TBT check in the Pll calculation.
v2: do not use a auxiliary function to check if status is
TBT or not. (Paulo)
v3: Code style changes. (Paulo)
Cc: Paulo Zanoni
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +++-
1 file changed
>-Original Message-
>From: Zanoni, Paulo R
>Sent: Wednesday, July 25, 2018 3:41 PM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Cc: De Marchi, Lucas
>Subject: Re: [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations
>
>Em Qua, 2018-0
>-Original Message-
>From: Zanoni, Paulo R
>Sent: Wednesday, July 25, 2018 4:08 PM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Subject: Re: [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction
>
>Em Qua, 2018-07-25 às 14:28 -0700, Anusha Srivats
For a TBT sequence, we need to set the IO type to TBT
in DDI_AUX_CTL.
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 34 +-
2 files changed, 26 insertions(+), 9 deletions(-)
diff
Add missing TBT check in the Pll calculation.
v2: do not use a auxiliary function to check if status is
TBT or not. (Paulo)
Cc: Paulo Zanoni
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion
From: "Srivatsa, Anusha"
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.
v2:
- Add define to conditionally check the buffer target depth (James Ausmus)
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, July 20, 2018 3:59 PM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Navare, Manasi D
>
>Subject: Re: [v3] drm/i915/dsc: Add missing _MMIO() from PPS registers
>
>On Fri, Jul 20, 2018
This patch fixes the commit -
<2efbb2f099fb> ("i915/dp/dsc: Add DSC PPS register definitions"),
which did not have _MMIO() for DSCA and DSCC.
v2: Fix typos. (manasi)
v3: Change the commit message (Rodrigo)
Cc: Rodrigi Vivi
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Rev
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Friday, July 20, 2018 1:37 PM
>To: Srivatsa, Anusha
>Cc: Navare, Manasi D ; intel-
>g...@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [v2] drm/i915/dsc: Add missing _MMIO() from PPS
>registers
>
>On Fri, Ju
>-Original Message-
>From: Navare, Manasi D
>Sent: Friday, July 20, 2018 1:29 PM
>To: Vivi, Rodrigo
>Cc: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [v2] drm/i915/dsc: Add missing _MMIO() from PPS
>registers
>
>On Fri, Ju
FIXME: This fixes the patch:
Link:
https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-2-git-send-email-anusha.sriva...@intel.com
Which did not have _MMIO() for DSCA and DSCC.
v2: Fix typos. (manasi)
Cc: Rodrigi Vivi
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers
FIXME: This fixes the patch:
Link:
https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-2-git-send-email-anusha.sriva...@intel.com
Which did not have _MMIO() for DSCA and DSCC.
Cc: Rodrigi Vivi
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_reg.h
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Wednesday, July 18, 2018 1:54 PM
>To: Navare, Manasi D
>Cc: Srivatsa, Anusha ; Nikula, Jani
>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
>
>On
From: "Srivatsa, Anusha"
Display Stream Compression(DSC) has a set of Picture
Parameter Set(PPS) components that the encoder must
communicate to the decoder.
This patch adds register definitions to
the PPS parameters for eDP/MIPI case and Display Port.
v2:
- Use _MMIO_PIPE instea
From: "Srivatsa, Anusha"
Add register defines and shifts that control the RC buffer threshold
between encoder and decoder for eDP/MIPI and DP cases.
The actual values are calculated usung a helper function.
This patch adds the shifts to registers where the value will
be written dur
From: "Srivatsa, Anusha"
The Picture Parameter Set metadata for DSC has to be sent
to the panel through secondary data packets. Add the error
correction registers, data registers and control registers
for the same.
The control registers for transcoders A and B are alrea
From: "Srivatsa, Anusha"
RC model has these parameters that correspond with each of
15 ranges of RC buffer threshold value in the RC model.
The three elements are range_min_qp, range_max_qp and
range_bpg_offset.
Add the Rate Control range values for eDP/MIPI and DP case.
The act
pages for the DFLEXDPPMS and DFLEXDPCSSS
>registers are wrong, so you should only trust the flows described by the "Gen11
>TypeC Programming" page in our spec.
>
>Cc: Animesh Manna
>Signed-off-by: Paulo Zanoni
Reviewed-by: Anusha Srivatsa
ming for previously defined MG PHY
>registers in original commit id (c92f47b5ec977a "drm/i915/icl:
>Add register defs for voltage swing sequences for MG PHY DDI").
>Since the MG PHY registers are first defined in ICL platform, there is no need
>for
>_ICL prefix.
>
>v2:
>* C
registers in original commit id (c92f47b5ec977a "drm/i915/icl:
Add register defs for voltage swing sequences for MG PHY DDI").
Since the MG PHY registers are first defined in ICL platform, there
is no need for _ICL prefix.
v2:
* Change the MG_TX_DRVCTL registers names to match the sp
Marchi
Cc: Paulo Zanoni
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjala
Signed-off-by: Anusha Srivatsa
[Paulo: coding style bikesheds and rebases].
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 134 +++-
drivers/gpu/drm/i915/i915_reg.h | 42
From: Zanoni, Paulo R
Sent: Monday, June 25, 2018 4:17 PM
To: Srivatsa, Anusha; intel-gfx@lists.freedesktop.org
Cc: Pandiyan, Dhinakaran
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/icp: Add Interrupt Support
Em Qua, 2018-06-20 às 14:36 -0700, Anusha
for enable_guc=2
(load huc; disable submission)
v2:
- Change commit title.
- Correct the shifts. (Daniele)
Credits to: Daniele Ceraolo Spurio
Cc: John Spotswood
Cc: Oscar Mateo
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
Reviewed-by: Daniele Ceraolo Spurio
Reviewed-by: John
>-Original Message-
>From: Ceraolo Spurio, Daniele
>Sent: Friday, June 22, 2018 10:26 AM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Cc: Spotswood, John A ; Mateo Lozano, Oscar
>
>Subject: Re: [PATCH] firmware/guc: Remove USES_GUC_SUBMISSION for
&
for enable_guc=2
(load huc; disable submission)
Credits to: Daniele Ceraolo Spurio
Cc: John Spotswood
Cc: Oscar Mateo
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git
available lanes for DP enablement.
>
>Signed-off-by: Animesh Manna
>[Paulo: significant rewrite of the patch.]
>Signed-off-by: Paulo Zanoni
Looks good.
Reviewed-by: Anusha Srivatsa
>---
> drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_dp.c |
>33
>+ * in between, so try to avoid the write when we can.
>+ */
So, in the sequences to enable, it does tell that enabling suitable aux power
domains is optional. But in the disable sequence, disable AUX_PWR is mentioned
as a non-optional step.
In which case it has t
consistent with
previous platforms (Lucas)
Cc: Lucas De Marchi
Cc: Paulo Zanoni
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjala
Signed-off-by: Anusha Srivatsa
[Paulo: coding style bikesheds and rebases].
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 134
: Animesh Manna
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 5
drivers/gpu/drm/i915/intel_dp.c | 57 +
2 files changed, 62 insertions(+)
diff --git
consistent with
previous platforms (Lucas)
Cc: Lucas De Marchi
Cc: Paulo Zanoni
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjala
Signed-off-by: Anusha Srivatsa
[Paulo: coding style bikesheds and rebases].
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 134
801 - 900 of 1318 matches
Mail list logo
