[PATCH] drm/i915/display/bmg: Add platform descriptor

Platform descriptor defined and PCI IDs added for Battlemage. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_device.c | 5 + drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++ include/drm/intel/i915_pciids.h | 8

[PATCH v4 19/19] drm/xe/bmg: Enable the display support

Enable the display support for Battlemage Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/xe/xe_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 3b30353dbc09..5289cc651c8b 100644

[PATCH v4 18/19] drm/i915/display: perform transient flush

-by: Balasubramani Vivekanandan Acked-by: Nirmoy Das Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ .../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++ drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++ drivers/gpu/drm/xe/Makefile

[PATCH v4 17/19] drm/xe/device: implement transient flush

a routine for this which we can then call from the display code. Signed-off-by: Nirmoy Das Co-developed-by: Matthew Auld Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++ drivers/gpu/drm/xe/xe_device.c

[PATCH v4 16/19] drm/xe/gt_print: add xe_gt_err_once()

From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Nirmoy Das --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed

[PATCH v4 15/19] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5

Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display

[PATCH v4 14/19] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"

From: Ankit Nautiyal This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by: Ankit Nautiyal Signed-off-by: Balasubramani Vivekanandan Reviewed

[PATCH v4 12/19] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits

From: José Roberto de Souza No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL register. Restrict the programming only to Xe_LPD+. BSpec: 49213 CC: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --

[PATCH v4 13/19] drm/i915/bmg: BMG should re-use MTL's south display logic

From: Matt Roper Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Dnyaneshwar Bhadane --- drivers/gpu/drm/i915/soc/intel_pch.c

[PATCH v4 10/19] drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes

From: Anusha Srivatsa Add step 9 from initialize display sequence. v2: Commit subject improved Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 drivers/gpu/drm/i915

[PATCH v4 11/19] drm/i915/xe2hpd: Add max memory bandwidth algorithm

From: Matt Roper Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 CC: Jani Nikula Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Radhakrishna

[PATCH v4 08/19] drm/i915/xe2hpd: update pll values in sync with Bspec

From: Ravi Kumar Vodapalli DP/eDP and HDMI pll values are updated for Xe2_HPD platform v2: Removed the unsupported mtl_c20_dp_uhbr20 from xehpd_c20_dp_tables Bspec: 74165 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu

[PATCH v4 09/19] drm/i915/xe2hpd: Add display info

From: Lucas De Marchi Add initial display info for xe2hpd. It is similar to xelpdp, but with no PORT_B. v2: Inherit from XE_LPDP_FEATURES instead of XE_LPD_FEATURES Bspec: 67066 CC: Matt Roper Signed-off-by: Lucas De Marchi Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper

[PATCH v4 07/19] drm/i915/xe2hpd: Add support for eDP PLL configuration

Tables for eDP PHY PLL configuration for different link rates added for Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas Xe2_HPD has C20 PHY. v2: Updated with a more appropriate Bspec number. Bspec: 74165 CC: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed

[PATCH v4 06/19] drm/i915/xe2hpd: Add new C20 PHY SRAM address

sure it is the only display using them in the driver. v2: * Redesigned how the right offsets are selected for different display IP versions. Bspec: 67610 Cc: Clint Taylor Cc: Gustavo Sousa Cc: Jani Nikula Signed-off-by: Balasubramani Vivekanandan Signed-off-by: Lucas De Marchi --- drivers

[PATCH v4 05/19] drm/i915/xe2hpd: Properly disable power in port A

From: José Roberto de Souza Xe2_HPD has a different value to power down port A. BSpec: 65450 Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++--- 1 file changed, 14

[PATCH v4 04/19] drm/i915/bmg: Extend DG2 tc check to future

-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a92b67adee9c..67697d9a559c 100644

[PATCH v4 03/19] drm/i915/xe2hpd: Initial cdclk table

From: Clint Taylor Add Xe2_HPD specific CDCLK table and use MTL Funcs. Bspec: 65243 CC: Lucas De Marchi Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++ 1 file changed, 11

[PATCH v4 02/19] drm/i915/bmg: Define IS_BATTLEMAGE macro

from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- d

[PATCH v4 01/19] drm/xe/display: Lane reversal requires writes to both context lanes

From: Clint Taylor Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. Bspec: 64539 CC: Jani Nikula Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +- 1 file

[PATCH v4 00/19] Enable display support for Battlemage

1): drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes Balasubramani Vivekanandan (5): drm/i915/bmg: Define IS_BATTLEMAGE macro drm/i915/xe2hpd: Add new C20 PHY SRAM address drm/i915/xe2hpd: Add support for eDP PLL configuration drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 drm/

[PATCH v3 21/21] drm/xe/bmg: Enable the display support

Enable the display support for Battlemage Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/xe/xe_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 3b30353dbc09..5289cc651c8b 100644

[PATCH v3 20/21] drm/i915/display: perform transient flush

-by: Balasubramani Vivekanandan Acked-by: Nirmoy Das --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ .../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++ drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++ drivers/gpu/drm/xe/Makefile | 3 ++- drivers/gpu

[PATCH v3 19/21] drm/xe/device: implement transient flush

a routine for this which we can then call from the display code. CC: Matt Roper Signed-off-by: Nirmoy Das Co-developed-by: Matthew Auld Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++ drivers/gpu/drm/xe/xe_device.c

[PATCH v3 18/21] drm/xe/gt_print: add xe_gt_err_once()

From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Nirmoy Das --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed

[PATCH v3 17/21] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5

Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display

[PATCH v3 16/21] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"

From: Ankit Nautiyal This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by: Ankit Nautiyal Signed-off-by: Balasubramani Vivekanandan Reviewed

[PATCH v3 15/21] drm/i915/bmg: BMG should re-use MTL's south display logic

From: Matt Roper Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Dnyaneshwar Bhadane --- drivers/gpu/drm/i915/soc/intel_pch.c

[PATCH v3 14/21] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits

From: José Roberto de Souza No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL register. Restrict the programming only to Xe_LPD+. BSpec: 49213 CC: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i9

[PATCH v3 13/21] drm/i915/xe2hpd: Add max memory bandwidth algorithm

From: Matt Roper Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 CC: Jani Nikula Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915

[PATCH v3 12/21] drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes

From: Anusha Srivatsa Add step 9 from initialize display sequence. v2: Commit subject improved Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 drivers/gpu/drm/i915

[PATCH v3 11/21] drm/i915/xe2hpd: Add display info

From: Lucas De Marchi Add initial display info for xe2hpd. It is similar to xelpdp, but with no PORT_B. v2: Inherit from XE_LPDP_FEATURES instead of XE_LPD_FEATURES Bspec: 67066 CC: Matt Roper Signed-off-by: Lucas De Marchi Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915

[PATCH v3 10/21] drm/i915/xe2hpd: update pll values in sync with Bspec

From: Ravi Kumar Vodapalli DP/eDP and HDMI pll values are updated for Xe2_HPD platform v2: Removed the unsupported mtl_c20_dp_uhbr20 from xehpd_c20_dp_tables Bspec: 74165 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper base.dev

[PATCH v3 09/21] drm/i915/xe2hpd: Add support for eDP PLL configuration

Tables for eDP PHY PLL configuration for different link rates added for Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas Xe2_HPD has C20 PHY. v2: Updated with a more appropriate Bspec number. Bspec: 74165 CC: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed

[PATCH v3 08/21] drm/i915/xe2hpd: Add new C20 PHY SRAM address

sure it is the only display using them in the driver. v2: * Redesigned how the right offsets are selected for different display IP versions. Bspec: 67610 Cc: Clint Taylor Cc: Gustavo Sousa Cc: Jani Nikula Signed-off-by: Balasubramani Vivekanandan Signed-off-by: Lucas De Marchi --- drivers

[PATCH v3 06/21] drm/i915/bmg: Extend DG2 tc check to future

-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a92b67adee9c..67697d9a559c 100644

[PATCH v3 07/21] drm/i915/xe2hpd: Properly disable power in port A

From: José Roberto de Souza Xe2_HPD has a different value to power down port A. BSpec: 65450 Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++--- 1 file changed, 14

[PATCH v3 04/21] drm/i915/xe2hpd: Skip CCS modifiers

or not. v2: * Improved the commit description with more details * Removed the redundant display IP version check for 20. Display version check for each modifier above would take care of it. CC: Juha-Pekka Heikkilä CC: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm

[PATCH v3 05/21] drm/i915/xe2hpd: Initial cdclk table

From: Clint Taylor Add Xe2_HPD specific CDCLK table and use MTL Funcs. Bspec: 65243 CC: Lucas De Marchi Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++ 1 file changed, 11

[PATCH v3 03/21] drm/i915/bmg: Define IS_BATTLEMAGE macro

from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- d

[PATCH v3 01/21] drm/xe/display: Lane reversal requires writes to both context lanes

From: Clint Taylor Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. Bspec: 64539 CC: Jani Nikula Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +- 1 file changed, 5 insertions

[PATCH v3 02/21] drm/i915/display: Enable RM timeout detection

: Jani Nikula Signed-off-by: Mitul Golani Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display

[PATCH v3 00/21] Enable display support for Battlemage

ifferent display IP versions v2: Rebased on latest drm-tip Ankit Nautiyal (1): Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Anusha Srivatsa (1): drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes Balasubramani Vivekanandan (6): drm/i915/bmg: Define IS_

[PATCH v2 25/25] drm/xe/bmg: Enable the display support

Enable the display support for Battlemage Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index b3158053baee..835c18ec8fb9 100644 --- a/drivers/gpu/drm/xe

[PATCH v2 24/25] drm/i915/display: perform transient flush

-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ .../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++ drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++ drivers/gpu/drm/xe/Makefile | 3 ++- drivers/gpu/drm/xe/display/xe_tdf.c

[PATCH v2 23/25] drm/xe/device: implement transient flush

a routine for this which we can then call from the display code. Signed-off-by: Nirmoy Das Co-developed-by: Matthew Auld Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++ drivers/gpu/drm/xe/xe_device.c | 52

[PATCH v2 22/25] drm/xe/gt_print: add xe_gt_err_once()

From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed, 3 insertions(+) diff

[PATCH v2 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5

Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm

[PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic

From: Matt Roper Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++-- 1 file changed, 2

[PATCH v2 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits

From: José Roberto de Souza Xe2_HPD doesn't have DBOX BW credits, so here programing it with zero. BSpec: 49213 Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH v2 18/25] drm/i915/display: Enable RM timeout detection

-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c

[PATCH v2 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm

From: Matt Roper Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display

[PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR

Defined a new DRAM type to be used in the following patches. The following patch first makes use of this new type in the i915 display. So without this define, build would fail when the shared display code is built for Xe. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe

[PATCH v2 15/25] drm/xe/display: Lane reversal requires writes to both context lanes

From: Clint Taylor Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. BSPEC: 64539 Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions

[PATCH v2 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming

From: Anusha Srivatsa Add step 9 from initialize display sequence. Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 drivers/gpu/drm/i915/i915_reg.h| 1 + 2 files changed

[PATCH v2 13/25] drm/i915/xe2hpd: Add display info

From: Lucas De Marchi Add initial display info for xe2hpd. It is similar to xelpd, but with no PORT_B. Bspec: 67066 Signed-off-by: Lucas De Marchi Signed-off-by: Balasubramani Vivekanandan --- .../gpu/drm/i915/display/intel_display_device.c | 16 1 file changed, 16

[PATCH v2 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec

From: Ravi Kumar Vodapalli DP/eDP and HDMI pll values are updated for Xe2_HPD platform Bspec: 74165 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++- 1 file changed, 45 insertions(+), 2

[PATCH v2 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration

Tables for eDP PHY PLL configuration for different link rates added for Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas Xe2_HPD has C20 PHY. Bpsec: 64568 CC: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147

[PATCH v2 10/25] drm/i915/xe2hpd: Add new C20 PLL register address

make sure it is the only display using them in the driver. Bspec: 67610 Cc: Clint Taylor Cc: Gustavo Sousa Signed-off-by: Balasubramani Vivekanandan Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 +-- .../gpu/drm/i915/display

[PATCH v2 09/25] drm/i915/xe2hpd: Properly disable power in port A

From: José Roberto de Souza Xe2_HPD has a different value to power down port A. BSpec: 65450 CC: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++--- 1 file changed, 14 insertions

[PATCH v2 08/25] drm/i915/bmg: Extend DG2 tc check to future

-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 614e60420a29..aed25890b6f5 100644 --- a/drivers/gpu/drm/i915

[PATCH v2 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"

From: Ankit Nautiyal This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by: Ankit Nautiyal Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu

[PATCH v2 06/25] drm/i915/xe2hpd: Initial cdclk table

From: Clint Taylor Add Xe2_HPD specific CDCLK table and use MTL Funcs. Bspec: 65243 Cc: Matt Roper CC: Lucas De Marchi Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++ 1 file changed, 11 insertions

[PATCH v2 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms

Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled through PAT. No CCS modifiers required for Xe2 platforms. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_fb.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git

[PATCH v2 04/25] drm/i915/bmg: Define IS_BATTLEMAGE macro

nings from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/

[PATCH v2 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro

Common display code requires IS_BATTLEMAGE macro. Defined the macro. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat

[PATCH v2 02/25] drm/xe/bmg: Add BMG platform definition

From: Matt Roper BMG is a discrete GPU based on the Xe2 architecture. Bspec: 68090 Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_pci.c| 7 +++ drivers/gpu/drm/xe/xe_platform_types.h | 1 + include/drm/xe_pciids.h

[PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address

-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 53 +-- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 36 ++--- 2 files changed, 65 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu

[PATCH v2 00/25] Enable dislay support for Battlemage

dgfx: DGFX uses direct VBT pin mapping" Anusha Srivatsa (1): drm/i915/xe2hpd: Add missing chicken bit register programming Balasubramani Vivekanandan (9): drm/i915/display: Prepare to handle new C20 PLL register address drm/xe/bmg: Define IS_BATTLEMAGE macro drm/i915/bmg: Define IS_BA

[PATCH 25/25] drm/xe/bmg: Enable the display support

Enable the display support for Battlemage Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index b3158053baee..835c18ec8fb9 100644 --- a/drivers/gpu/drm/xe

[PATCH 24/25] drm/i915/display: perform transient flush

-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ .../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++ drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++ drivers/gpu/drm/xe/Makefile | 3 ++- drivers/gpu/drm/xe/display/xe_tdf.c

[PATCH 23/25] drm/xe/device: implement transient flush

a routine for this which we can then call from the display code. Signed-off-by: Nirmoy Das Co-developed-by: Matthew Auld Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++ drivers/gpu/drm/xe/xe_device.c | 49

[PATCH 22/25] drm/xe/gt_print: add xe_gt_err_once()

From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed, 3 insertions(+) diff

[PATCH 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5

Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm

[PATCH 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic

From: Matt Roper Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++-- 1 file changed, 2

[PATCH 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits

From: José Roberto de Souza Xe2_HPD doesn't have DBOX BW credits, so here programing it with zero. BSpec: 49213 Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH 15/25] drm/xe/display: Lane reversal requires writes to both context lanes

From: Clint Taylor Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. BSPEC: 64539 Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions

[PATCH 18/25] drm/i915/display: Enable RM timeout detection

-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c

[PATCH 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm

From: Matt Roper Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display

[PATCH 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR

Defined a new DRAM type to be used in the following patches. The following patch first makes use of this new type in the i915 display. So without this define, build would fail when the shared display code is built for Xe. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe

[PATCH 08/25] drm/i915/bmg: Extend DG2 tc check to future

-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 614e60420a29..aed25890b6f5 100644 --- a/drivers/gpu/drm/i915

[PATCH 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec

From: Ravi Kumar Vodapalli DP/eDP and HDMI pll values are updated for Xe2_HPD platform Bspec: 74165 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++- 1 file changed, 45 insertions(+), 2

[PATCH 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming

From: Anusha Srivatsa Add step 9 from initialize display sequence. Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 drivers/gpu/drm/i915/i915_reg.h| 1 + 2 files changed

[PATCH 09/25] drm/i915/xe2hpd: Properly disable power in port A

From: José Roberto de Souza Xe2_HPD has a different value to power down port A. BSpec: 65450 CC: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++--- 1 file changed, 14 insertions

[PATCH 13/25] drm/i915/xe2hpd: Add display info

From: Lucas De Marchi Add initial display info for xe2hpd. It is similar to xelpd, but with no PORT_B. Bspec: 67066 Signed-off-by: Lucas De Marchi Signed-off-by: Balasubramani Vivekanandan --- .../gpu/drm/i915/display/intel_display_device.c | 16 1 file changed, 16

[PATCH 10/25] drm/i915/xe2hpd: Add new C20 PLL register address

make sure it is the only display using them in the driver. Bspec: 67610 Cc: Clint Taylor Cc: Gustavo Sousa Signed-off-by: Balasubramani Vivekanandan Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 +-- .../gpu/drm/i915/display

[PATCH 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"

From: Ankit Nautiyal This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by: Ankit Nautiyal Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu

[PATCH 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration

Tables for eDP PHY PLL configuration for different link rates added for Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas Xe2_HPD has C20 PHY. Bpsec: 64568 CC: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147

[PATCH 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms

Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled through PAT. No CCS modifiers required for Xe2 platforms. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_fb.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git

[PATCH 06/25] drm/i915/xe2hpd: Initial cdclk table

From: Clint Taylor Add Xe2_HPD specific CDCLK table and use MTL Funcs. Bspec: 65243 Cc: Matt Roper CC: Lucas De Marchi Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++ 1 file changed, 11 insertions

[PATCH 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro

Common display code requires IS_BATTLEMAGE macro. Defined the macro. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat

[PATCH 04/25] drm/i915/bmg: Define IS_BATTLEMAGE macro

nings from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/

[PATCH 02/25] drm/xe/bmg: Add BMG platform definition

From: Matt Roper BMG is a discrete GPU based on the Xe2 architecture. Bspec: 68090 Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_pci.c| 7 +++ drivers/gpu/drm/xe/xe_platform_types.h | 1 + include/drm/xe_pciids.h

[PATCH 01/25] drm/i915/display: Prepare to handle new C20 PLL register address

-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 53 +-- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 36 ++--- 2 files changed, 65 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu

[PATCH 00/25] Enable dislay support for Battlemage

apping" Anusha Srivatsa (1): drm/i915/xe2hpd: Add missing chicken bit register programming Balasubramani Vivekanandan (9): drm/i915/display: Prepare to handle new C20 PLL register address drm/xe/bmg: Define IS_BATTLEMAGE macro drm/i915/bmg: Define IS_BATTLEMAGE macro drm/i915/xe2

[Intel-gfx] [PATCH] drm/i915/display: Fix IP version of the WAs

WAs 14011508470, 14011503030 were applied on IP versions beyond which they are applicable. Fixed the IP version checks for these workarounds. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add Wa_22016670082

On 25.10.2023 18:47, Dnyaneshwar Bhadane wrote: > Implemented workaround for XeLPM+ > BSpec: 51762 > > Signed-off-by: Dnyaneshwar Bhadane > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Balasubramani Vivekan

[Intel-gfx] [PATCH v2] drm/i915/display: Print display info inside driver display initialization

) Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_driver.c | 5 + drivers/gpu/drm/i915/i915_driver.c | 2 -- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm

Re: [Intel-gfx] [PATCH] drm/i915/display: Print display info inside driver display initialization

On 21.09.2023 10:38, Jani Nikula wrote: > On Thu, 21 Sep 2023, Balasubramani Vivekanandan > wrote: > > Separate the printing of display version and feature flags from the main > > driver probe to inside the display initialization. This is in alignment > > with isolati

[Intel-gfx] [PATCH] drm/i915/display: Print display info inside driver display initialization

Separate the printing of display version and feature flags from the main driver probe to inside the display initialization. This is in alignment with isolating the display code from the main driver and helps Xe driver to resuse it. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm

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